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SN74LV4052A
SCLS429K – MAY 1999 – REVISED NOVEMBER 2016
SN74LV4052A Dual 4-Channel Analog Multiplexers and Demultiplexers
1 Features
3 Description
•
•
•
•
•
•
The SN74LV4052A device is a dual, 4-channel
CMOS analog multiplexer and demultiplexer that is
designed for 2-V to 5.5-V VCC operation.
1
•
2-V to 5.5-V VCC Operation
Fast Switching
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Extremely Low Input Current
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22:
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
Telecomunications
Infotainment
Signal Gating and Isolation
Home Appliances
Programmable Logic Circuits
Modulation and Demodulation
The SN74LV4052A device handles both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LV4052AD
SOIC (16)
9.90 mm × 3.91 mm
SN74LV4052ADB
SSOP (16)
6.20 mm × 5.30 mm
SN74LV4052ADGV
TVSOP (16)
3.60 mm × 4.40 mm
SN74LV4052ANS
SO (16)
10.30 mm × 5.30 mm
SN74LV4052AN
PDIP (16)
19.30 mm × 6.35 mm
SN74LV4052APW
TSSOP (16)
5.00 mm × 4.40 mm
SN74LV4052ARGY
VQFN (16)
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
13
12
A
14
9
11
1
5
2
INH
1Y0
10
15
B
1-COM
6
4
3
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2-COM
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74LV4052A
SCLS429K – MAY 1999 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
5
5
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: VCC = 2.5 V ± 0.2 V ........
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........
Switching Characteristics: VCC = 5 V ± 0.5 V ...........
Switching Characteristics: Analog.............................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (October 2012) to Revision K
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Deleted SN54LV4052A from data sheet ................................................................................................................................ 1
•
Changed Package thermal impedance, RθJA, values in the Thermal Information table From: 73 To: 90.9 (D), From:
82 To: 102.8 (DB), From: 120 To: 125.7 (DGV), From: 67 To: 54.8 (N), From: 64 To: 89.7 (NS), From: 108 To:
113.2 (PW), and From: 39 To: 48.9 (RGY) ............................................................................................................................ 5
2
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SCLS429K – MAY 1999 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
D, DB, DGV, N, NS, or PW Package
16-Pin SOIC, SSOP, TVSOP, SO, PDIP, or TSSOP
Top View
2
15
1Y2
2-COM
3
14
1Y1
2Y3
4
13
1-COM
2Y1
5
12
1Y0
INH
6
11
1Y3
GND
7
10
A
GND
8
9
B
VCC
2Y2
16
VCC
2Y2
2
15
1Y2
2-COM
3
14
1Y1
2Y3
4
13
1-COM
Thermal
Pad
2Y1
5
12
1Y0
INH
6
11
1Y3
GND
7
10
A
9
16
2Y0
1
8
2Y0
1
RGY Package
16-Pin VQFN With Thermal Pad
Top View
B
GND
Not to scale
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
2Y0
I/O
Port 2 channel 0
2
2Y2
I/O
Port 2 channel 2
3
2-COM
I/O
Port 2 common channel
4
2Y3
I/O
Port 2 channel 3
5
2Y1
I/O
Port 2 channel 1
6
INH
I
7
GND
—
Device ground
8
GND
—
Device ground
9
B
I
Logic input selector B
10
A
I
Logic input selector A
11
1Y3
I/O
Port 1 channel 3
12
1Y0
I/O
Port 1 channel 0
13
1-COM
I/O
Port 1 common channel
14
1Y1
I/O
Port 1 channel 1
15
1Y2
I/O
Port 1 channel 2
16
VCC
—
Device power
Inhibit input
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SN74LV4052A
SCLS429K – MAY 1999 – REVISED NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VI
(2)
Switch I/O voltage, VIO (2) (3)
MIN
MAX
UNIT
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
V
–20
mA
Input clamp current, IIK
VI < 0
I/O diode current, IIOK
VIO < 0 and VIO > VCC
50
mA
Switch through current, IT
VIO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Tested on D
package
6.3 Recommended Operating Conditions
see (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage (control inputs)
MIN
MAX
2 (2)
5.5
UNIT
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 2 V
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VIL
Low-level input voltage (control inputs)
VI
Control input voltage
0
5.5
V
VIO
Input or output voltage
0
VCC
V
Δt/Δv
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
(2)
4
Operating free-air temperature
V
ns/V
20
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs (SCBA004).
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. TI recommends that only digital
signals be transmitted at these low supply voltages.
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SCLS429K – MAY 1999 – REVISED NOVEMBER 2016
6.4 Thermal Information
SN74LV4052A
THERMAL METRIC (1)
D
(SOIC)
DB
(SSOP)
DGV
(TVSOP)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
RGY
(VQFN)
UNIT
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
90.9
102.8
125.7
54.8
89.7
113.2
48.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.9
53.3
50.9
42.1
48.1
48.2
46.9
°C/W
RθJB
Junction-to-board thermal resistance
48
53.4
57.5
34.8
50.1
58.3
25
°C/W
ψJT
Junction-to-top characterization parameter
18.6
16.5
5.6
26.9
16.7
6.3
2
°C/W
ψJB
Junction-to-board characterization parameter
47.8
52.9
57
34.7
49.8
57.8
25
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
—
—
—
11.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 2.3 V
ron
On-state switch resistance
IT = 2 mA, VI = VCC
or GND, VINH = VIL
(see Figure 2)
VCC = 3 V
VCC = 4.5 V
VCC = 2.3 V
ron(p)
Peak on-state resistance
IT = 2 mA, VI = VCC
to GND, VINH = VIL
VCC = 3 V
VCC = 4.5 V
VCC = 2.3 V
Δron
Difference in on-state
resistance between switches
IT = 2 mA, VI = VCC
to GND, VINH = VIL
VCC = 3 V
VCC = 4.5 V
MIN
TA = 25°C
TYP
MAX
43
180
TA = –40 to 85°C
TA = 25°C
225
34
TA = –40 to 85°C
TA = 25°C
25
133
TA = –40 to 85°C
35
1.5
TA = –40 to 85°C
0.7
VI = 5.5 V or GND, and VCC = 0 to 5.5 V
OFF-state switch leakage
current
VI = VCC and VO = GND, or VI = GND
and VO = VCC, VINH = VIH , and
VCC = 5.5 V (see Figure 3)
TA = 25°C
IS(off)
IS(on)
ON-state switch leakage
current
VI = VCC or GND, VINH = VIL, and
VCC = 5.5 V (see Figure 4)
TA = 25°C
ICC
Supply current
VI = VCC or GND, VCC = 5.5 V, and TA = –40 to 85°C
CIC
Control input capacitance
f = 10 MHz, VCC = 3.3 V, and TA = 25°C
CIS
Common terminal
capacitance
COS
CF
30
20
Ω
15
20
TA = 25°C
Control input current
100
30
TA = –40 to 85°C
II
Ω
40
1.1
TA = 25°C
180
125
TA = –40 to 85°C
TA = 25°C
500
225
TA = –40 to 85°C
TA = 25°C
75
600
63
TA = 25°C
Ω
100
TA = –40 to 85°C
TA = 25°C
150
190
TA = –40 to 85°C
TA = 25°C
UNIT
±0.1
TA = –40 to 85°C
±1
µA
±0.1
TA = –40 to 85°C
±1
±0.1
TA = –40 to 85°C
±1
20
µA
µA
µA
2.1
pF
VCC = 3.3 V and TA = 25°C
13.1
pF
Switch terminal capacitance
VCC = 3.3 V and TA = 25°C
5.6
pF
Feedthrough capacitance
VCC = 3.3 V and TA = 25°C
0.5
pF
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6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range and VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 15 pF
(see Figure 5)
TA = 25°C
tPZH
tPZL
Enable delay time
INH
COM or Y
CL = 15 pF
(seeFigure 6 )
TA = 25°C
tPHZ
tPLZ
Disable delay time
INH
COM or Y
CL = 15 pF
(see Figure 6)
TA = 25°C
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF
(see Figure 5)
TA = 25°C
tPZH
tPZL
Enable delay time
INH
COM or Y
CL = 50 pF
(see Figure 6)
TA = 25°C
tPHZ
tPLZ
Disable delay time
INH
COM or Y
CL = 50 pF
(see Figure 6)
TA = 25°C
TEST CONDITIONS
MIN
TYP
MAX
1.9
10
TA = –40 to 85°C
UNIT
ns
16
8
18
TA = –40 to 85°C
ns
23
8.3
18
TA = –40 to 85°C
ns
23
3.8
12
TA = –40 to 85°C
ns
18
9.4
28
TA = –40 to 85°C
ns
35
12.4
28
TA = –40 to 85°C
ns
35
6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range and VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 15 pF
(see Figure 5)
TA = 25°C
tPZH
tPZL
Enable delay time
INH
COM or Y
CL = 15 pF
(seeFigure 6 )
TA = 25°C
tPHZ
tPLZ
Disable delay time
INH
COM or Y
CL = 15 pF
(see Figure 6)
TA = 25°C
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF
(see Figure 5)
TA = 25°C
tPZH
tPZL
Enable delay time
INH
COM or Y
CL = 50 pF
(see Figure 6)
TA = 25°C
tPHZ
tPLZ
Disable delay time
INH
COM or Y
CL = 50 pF
(see Figure 6)
TA = 25°C
TEST CONDITIONS
MIN
TYP
1.2
TA = –40 to 85°C
MAX
UNIT
6
ns
10
5.7
TA = –40 to 85°C
12
ns
15
6.6
TA = –40 to 85°C
12
ns
15
2.5
TA = –40 to 85°C
9
ns
12
6.7
TA = –40 to 85°C
20
ns
25
9.5
TA = –40 to 85°C
20
ns
25
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range and VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
COM or Y
Y or COM
CL = 15 pF
(see Figure 5)
TA = 25°C
TEST CONDITIONS
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable delay time
INH
COM or Y
CL = 15 pF
(seeFigure 6 )
TA = 25°C
tPHZ
tPLZ
Disable delay
time
INH
COM or Y
CL = 15 pF
(see Figure 6)
TA = 25°C
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF
(see Figure 5)
TA = 25°C
tPZH
tPZL
Enable delay time
INH
COM or Y
CL = 50 pF
(see Figure 6)
TA = 25°C
6
MIN
TYP
MAX
0.7
4
TA = –40 to 85°C
7
4
TA = –40 to 85°C
5
TA = –40 to 85°C
TA = –40 to 85°C
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8
10
1.5
6
8
4.7
TA = –40 to 85°C
8
10
14
18
UNIT
ns
ns
ns
ns
ns
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Switching Characteristics: VCC = 5 V ± 0.5 V (continued)
over recommended operating free-air temperature range and VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
tPHZ
tPLZ
Disable delay
time
FROM
(INPUT)
TO
(OUTPUT)
INH
COM or Y
TEST CONDITIONS
MIN
TA = 25°C
CL = 50 pF
(see Figure 6)
TYP
MAX
6.9
14
TA = –40 to 85°C
18
UNIT
ns
6.9 Switching Characteristics: Analog
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Frequency response
(switch on)
Crosstalk (between any
switches)
Crosstalk (control input
to signal output)
Feedthrough
attenuation
(switch off)
TO
(OUTPUT)
COM or Y
Y or COM
COM or Y
Y or COM
INH
COM or Y
COM or Y
Sine-wave distortion
(1)
(2)
FROM
(INPUT)
Y or COM
COM or Y
Y or COM
TEST CONDITIONS
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7) (1)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 8) (2)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 10) (2)
CL = 50 pF,
RL = 10 kΩ,
fin = 1 kHz
(sine wave)
(see Figure 11)
MIN
TYP
VCC = 2.3 V
30
VCC = 3 V
35
VCC = 4.5 V
50
VCC = 2.3 V
–45
VCC = 3 V
–45
VCC = 4.5 V
–45
VCC = 2.3 V
20
VCC = 3 V
35
VCC = 4.5 V
65
VCC = 2.3 V
–45
VCC = 3 V
–45
VCC = 4.5 V
–45
VI = 2 Vp-p and
VCC = 2.3 V
0.1%
VI = 2.5 Vp-p and
VCC = 3 V
0.1%
VI = 4 Vp-p and
VCC = 4.5 V
0.1%
MAX
UNIT
MHz
dB
mV
dB
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF and f = 10 MHz
TYP
UNIT
11.8
pF
6.11 Typical Characteristics
3.9
CL =15pF
CL= 50pF
3.6
3.3
TPD typ (ns)
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
2.5
2.75
3
3.25
3.5
3.75 4
Vcc (V)
4.25
4.5
4.75
5
D001
Figure 1. Typical Propagation Delay vs Vcc
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7 Parameter Measurement Information
VCC
VINH = VIL
VCC
VI = VCC or GND
VO
(ON)
GND
r on
VI – VO
2
10 –3
W
2 mA
V
VI − V O
Figure 2. ON-State Resistance Test Circuit
VCC
VINH = VIH
VCC
A
VI
VO
(OFF)
GND
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
Figure 3. OFF-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
VI
A
(ON)
Open
GND
VI = VCC or GND
Figure 4. ON-State Switch Leakage-Current Test Circuit
8
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Parameter Measurement Information (continued)
VCC
VINH = VIL
VCC
Input
Output
(ON)
50 Ω
GND
CL
Figure 5. Propagation Delay Time, Signal Input to Signal Output
VCC
50 Ω
VINH
VCC
VO
VI
S1
RL = 1 kΩ
S2
TEST
S1
S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
VCC
GND
CL
GND
TEST CIRCUIT
VCC
VCC
VINH
VINH
50%
0V
50%
0V
tPZL
tPZH
VOH
≈VCC
VO
VO
50%
VOL
(tPZL, tPZH)
VCC
VCC
VINH
50%
≈0 V
VINH
50%
0V
50%
0V
tPLZ
tPHZ
≈VCC
VO
VOL
VOH
VO
VOL + 0.3 V
(tPLZ, tPHZ)
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
Figure 6. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
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Parameter Measurement Information (continued)
VCC
VINH = GND
0.1 μF V
I
fin
VCC
VO
(ON)
GND
50 Ω
RL = 600 Ω
CL = 50 pF
VCC/2
NOTE A: fin is a sine wave.
Figure 7. Frequency Response (Switch ON)
VCC
VINH = GND
0.1 μF
VCC
VI
fin
VO1
(ON)
600 Ω
GND
CL = 50 pF
RL = 600 Ω
50 Ω
VCC/2
VCC
VINH = VCC
VCC
(OFF)
GND
600 Ω
VO2
RL = 600 Ω
CL = 50 pF
VCC/2
Figure 8. Crosstalk Between Any Two Switches
10
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Parameter Measurement Information (continued)
VCC
50 Ω
VINH
VCC
fin
VO
GND
600 Ω
CL = 50 pF
RL = 600 Ω
VCC/2
VCC/2
Figure 9. Crosstalk Between Control Input and Switch Output
VCC
VINH = VCC
0.1 μF
VI
fin
50 Ω
VCC
VO
(OFF)
GND
600 Ω
RL = 600 Ω
CL = 50 pF
VCC/2
VCC/2
Figure 10. Feedthrough Attenuation (Switch OFF)
VCC
VINH = GND
10 μF
VI
fin
VCC
GND
600 Ω
VO
(ON)
RL = 10 kΩ
CL = 50 pF
VCC/2
Figure 11. Sine-Wave Distortion
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8 Detailed Description
8.1 Overview
The SN74LV4052A device is a dual, 4-channel CMOS analog multiplexer and demultiplexer that is designed for
2-V to 5.5-V VCC operation. It has low input current consumption at the digital input pins and low crosstalk
between switches. The active low Inhibit (INH) tri-state all the channels when high and when low, depending on
the A and B inputs, one of the four independent input/outputs (nY0 - nY3) connects to the COM channel. The
SN74LV4052A is available in multiple package options including TSSOP (PW) and QFN (RGY).
8.2 Functional Block Diagram
13
12
A
14
9
11
1
5
2
INH
1Y0
10
15
B
1-COM
6
4
3
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2-COM
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Logic Diagram (Positive Logic)
8.3 Feature Description
•
•
The SN74LV4052A operates from 2-V to 5.5-V VCC with extremely low input current consumption at the
CMOS input pins of A, B and INH.
The SN74LV4052A enables fast switching with low crosstalk between the switches. 5.5 V peak level
bidirectional transmission allowed with the either analog or digital signals.
8.4 Device Functional Modes
Table 1 lists the functional modes of SN74LV4052A.
Table 1. Function Table
INPUTS
12
A
ON
CHANNELS
L
L
1Y0, 2Y0
L
H
1Y1, 2Y1
H
L
1Y2, 2Y2
H
H
1Y3, 2Y3
X
X
None
INH
B
L
L
L
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Typical applications for the SN74LV4052A include signal gating, chopping, modulation or demodulation (modem),
and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.
9.2 Typical Application
3.3V
SDA1
SDA2
SDA3
SDA4
SCL1
2Y1
SCL2
2Y2
SCL3
2Y3
B INH
A
4.7k
2Y0
2COM
4.7k
SCLx
4.7k
1Y3
4.7k
1Y2
1COM
4.7k
SDAx
4.7k
1Y1
4.7k
1Y0
4.7k
SN74LV4052A
SCL4
MCU
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Typical I2C Multiplexing Application
9.2.1 Design Requirements
Designing with the SN74LV4052A device requires a stable input voltage between 2 V and 5.5 V (see
Recommended Operating Conditions for details). Another important design consideration are the characteristics
of the signal being multiplexed which ensures no important information is lost due to timing or incompatibility with
this device.
9.2.2 Detailed Design Procedure
The SN74LV4052A dual 1- to 4-channel multiplexer is ideal for I2C selection. The I2C data and clock lines are
selected using A,B select lines from the MCU. The pullup resistors are selected based on the capability of the
driver. Low pullup resistor results in faster rise time; however, it generates additional current during the low state
into the driver. See to the Recommended Operating Conditions of the datasheet for the input transition rates (VIH
and VIL) of the CMOS inputs.
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Typical Application (continued)
9.2.3 Application Curve
18
CL=15pF
CL = 50pF
17
16
TPD max (ns)
15
14
13
12
11
10
9
8
7
2.5
2.75
3
3.25
3.5
3.75 4
Vcc(V)
4.25
4.5
4.75
5
D001
Figure 14. Maximum Propagation Delay vs Vcc
14
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10 Power Supply Recommendations
Most systems have a common 3.3-V or 5-V rail that can supply the VCC pin of this device. If this rail is not
available, a switched-mode power supply (SMPS) or a low dropout regulator (LDO) can supply this device from a
higher-voltage rail.
See the Recommended Operating Conditions for operating voltage range for this device. Having bypass
capacitors of 0.1 µF is highly recommended.
11 Layout
11.1 Layout Guidelines
TI recommends keeping the signal lines as short and as straight as possible (see Figure 15). Incorporation of
microstrip or stripline techniques are also recommended when signal lines are more than 1 in. long. These traces
must be designed with a characteristic impedance of either 50-Ω or 75-Ω as required by the application. Do not
place this device too close to high-voltage switching components because they may cause interference. Not all
PCB traces can be straight and therefore some traces must turn corners. Figure 16 shows progressively better
techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes
reflections.
11.2 Layout Example
Figure 15. Layout Schematic
BETTER
BEST
2W
WORST
1W min.
W
Figure 16. Trace Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV4052AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4052A
SN74LV4052ADBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052ADBRE4
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052ADGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052ADR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
LV4052A
SN74LV4052AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74LV4052AN
SN74LV4052ANSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV4052A
SN74LV4052APW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052APWE4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052APWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052APWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052APWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052APWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052APWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW052A
SN74LV4052ARGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LW052A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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