SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
D
2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
SN54LV541A . . . J OR W PACKAGE
SN74LV541A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
20
A2
A1
OE1
VCC
1
A3
A4
A5
A6
A7
19 OE2
18 Y1
2
3
17 Y2
16 Y3
4
5
15 Y4
14 Y5
6
7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
13 Y6
12 Y7
8
9
10
11
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
20
VCC
1
SN54LV541A . . . FK PACKAGE
(TOP VIEW)
SN74LV541A . . . RGY PACKAGE
(TOP VIEW)
Y8
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
D
OE1
D
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
GND
D
D Ioff Supports Partial-Power-Down Mode
OE2
D 2-V to 5.5-V VCC Operation
D Max tpd of 6 ns at 5 V
D Typical VOLP (Output Ground Bounce)
description/ordering information
The ’LV541A devices are octal buffers/drivers designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
QFN − RGY
SN74LV541ARGYR
Tube of 25
SN74LV541ADW
Reel of 2000
SN74LV541ADWR
SOP − NS
Reel of 2000
SN74LV541ANSR
74LV541A
SSOP − DB
Reel of 2000
SN74LV541ADBR
LV541A
Tube of 70
SN74LV541APW
Reel of 2000
SN74LV541APWR
Reel of 250
SN74LV541APWT
TVSOP − DGV
Reel of 2000
SN74LV541ADGVR
LV541A
CDIP − J
Tube of 20
SNJ54LV541AJ
SNJ54LV541AJ
CFP − W
Tube of 85
SNJ54LV541AW
SNJ54LV541AW
LCCC − FK
Tube of 55
SNJ54LV541AFK
SNJ54LV541AFK
TSSOP − PW
−55°C to 125°C
†
TOP-SIDE
MARKING
Reel of 1000
SOIC − DW
−40°C
40 C to 85°C
85 C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV541A
LV541A
LV541A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices are ideal for driving bus lines or buffer memory address registers. They feature inputs and
outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or
OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted
data when they are not in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer/driver)
INPUTS
A
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
logic diagram (positive logic)
OE1
OE2
A1
1
19
2
18
To Seven Other Channels
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Y1
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
VCC
SN54LV541A
SN74LV541A
MIN
MAX
MIN
MAX
2
5.5
2
5.5
Supply voltage
VCC = 2 V
VIH
High level input voltage
High-level
1.5
Low level input voltage
Low-level
VI
Input voltage
VO
Output voltage
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC × 0.7
0.5
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
−50
−50
VCC = 2.3 V to 2.7 V
−2
−2
VCC = 3 V to 3.6 V
−8
−8
−16
−16
VCC = 2 V
Low level output current
Low-level
Δt/Δv
Input transition rise or fall rate
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
8
8
VCC = 4.5 V to 5.5 V
16
16
VCC = 2.3 V to 2.7 V
200
200
VCC = 3 V to 3.6 V
100
100
20
20
VCC = 4.5 V to 5.5 V
TA
Operating free-air temperature
−55
125
V
VCC × 0.3
0
VCC = 4.5 V to 5.5 V
IOL
0.5
VCC × 0.3
VCC = 2 V
High level output current
High-level
V
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
−40
V
V
μA
mA
μA
mA
ns/V
°C
85
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV541A
PARAMETER
VOH
TEST CONDITIONS
MIN
TYP
MAX
MIN
2 V to 5.5 V
IOH = −2 mA
2.3 V
2
2
IOH = −8 mA
3V
2.48
2.48
4.5 V
3.8
VCC−0.1
TYP
MAX
UNIT
VCC−0.1
V
3.8
IOL = 50 μA
2 V to 5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
4.5 V
0.55
0.55
IOL = 16 mA
0.1
0.1
V
II
VI = 5.5 V or GND
0 to 5.5 V
±1
±1
μA
IOZ
VO = VCC or GND
5.5 V
±5
±5
μA
ICC
VI = VCC or GND,
5.5 V
20
20
μA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
μA
Ci
VI = VCC or GND
IO = 0
3.3 V
2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
SN74LV541A
IOH = −50 μA
IOH = −16 mA
VOL
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
pF
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
ten
OE
tdis
OE
PARAMETER
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
SN54LV541A
MIN
MAX
MIN
MAX
6.7*
11.3*
1*
13.5*
1
13.5
8.5*
16.6*
1*
19.5*
1
19.5
8.4*
13.1*
1*
15*
1
15
Y
8.7
15.9
1
18.5
1
18.5
Y
10.5
20.7
1
24
1
24
12.3
17.9
1
20
1
20
CL = 15 pF
CL = 50 pF
Y
tsk(o)
∗
SN74LV541A
MAX
2
UNIT
ns
ns
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
Y
ten
OE
Y
tdis
OE
PARAMETER
LOAD
CAPACITANCE
TA = 25°C
MIN
CL = 15 pF
CL = 50 pF
Y
SN54LV541A
TYP
MAX
MIN
MAX
MIN
MAX
4.8*
7*
1*
8.5*
1
8.5
6.1*
10.5*
1*
12.5*
1
12.5
5.8*
11*
1*
12*
1
12
6.1
10.5
1
12
1
12
7.4
14
1
16
1
16
8.8
15.4
1
17.5
1
17.5
tsk(o)
∗
SN74LV541A
1.5
UNIT
ns
ns
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
tpd
ten
tdis
OE
Y
PARAMETER
LOAD
CAPACITANCE
TA = 25°C
MIN
SN54LV541A
MAX
MIN
3.5*
5*
4.3*
7.2*
Y
3.9*
A
Y
OE
Y
CL = 15 pF
CL = 50 pF
TYP
MIN
1*
6*
1
6
1*
8.5*
1
8.5
7.5*
1*
8*
1
8
4.3
7
1
8
1
8
5.3
9.2
1
10.5
1
10.5
5.6
8.8
1
10
1
10
tsk(o)
∗
SN74LV541A
MAX
1
MAX
UNIT
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV541A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.5
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
−0.4
−0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
2.9
V
2.31
V
0.99
V
UNIT
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
POST OFFICE BOX 655303
CL = 50 pF,
pF
• DALLAS, TEXAS 75265
f = 10 MHz
VCC
TYP
3.3 V
16.3
5V
17.8
pF
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410I − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
tPHL
50% VCC
tPHL
50% VCC
VOL
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
50% VCC
tPZL
VOH
In-Phase
Output
Out-of-Phase
Output
0V
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV541ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
LV541A
SN74LV541ADGVR
OBSOLETE
TVSOP
DGV
20
TBD
Call TI
Call TI
-40 to 85
SN74LV541ADGVRE4
OBSOLETE
TVSOP
DGV
20
TBD
Call TI
Call TI
-40 to 85
SN74LV541ADGVRG4
OBSOLETE
TVSOP
DGV
20
TBD
Call TI
Call TI
-40 to 85
SN74LV541ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ADWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV541A
SN74LV541ANSRE4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV541A
SN74LV541ANSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV541A
SN74LV541APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV541APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541APWTG4
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV541A
SN74LV541ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LV541A
SN74LV541ARGYRG4
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LV541A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV541ADBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74LV541ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV541ANSR
SO
NS
20
2000
330.0
24.4
8.2
13.0
2.5
12.0
24.0
Q1
SN74LV541APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV541APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV541ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV541ADBR
SN74LV541ADWR
SSOP
DB
20
2000
367.0
367.0
38.0
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV541ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV541APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LV541APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LV541ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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