SN74LV573ADGVR

SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 20 2 19 3 18 4 17 16 5 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 1D 2D 3D 4D 5D 6D 7D 8D 1 20 19 1Q 18 2Q 2 3 17 3Q 16 4Q 4 5 15 5Q 14 6Q 6 7 SN54LV573A . . . FK PACKAGE (TOP VIEW) 2D 1D OE VCC VCC 1 SN74LV573A . . . RGY PACKAGE (TOP VIEW) 3D 4D 5D 6D 7D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 13 7Q 12 8Q 8 9 10 11 LE OE 1D 2D 3D 4D 5D 6D 7D 8D GND Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 2Q 3Q 4Q 5Q 6Q 8D GND LE 8Q 7Q SN54LV573A . . . J OR W PACKAGE SN74LV573A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) D OE D D 2.3 V at VCC = 3.3 V , TA = 25°C Support Mixed-Mode Voltage Operation on All Ports GND D D Ioff Supports Partial-Power-Down Mode 1Q D 2-V to 5.5-V VCC Operation D Max tpd of 8 ns at 5 V D Typical VOLP (Output Ground Bounce) description/ordering information ORDERING INFORMATION QFN − RGY SN74LV573ARGYR Tube of 25 SN74LV573ADW Reel of 2000 SN74LV573ADWR SOP − NS Reel of 2000 SN74LV573ANSR 74LV573A SSOP − DB Reel of 2000 SN74LV573ADBR LV573A Tube of 70 SN74LV573APW Reel of 2000 SN74LV573APWR Reel of 250 SN74LV573APWT Reel of 2000 SN74LV573ADGVR LV573A −40°C 40°C to 85°C TSSOP − PW TVSOP − DGV † TOP-SIDE MARKING Reel of 1000 SOIC − DW −55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA LV573A LV573A LV573A VFBGA − GQN Reel of 1000 SN74LV573AGQNR LV573A CDIP − J Tube of 20 SNJ54LV573AJ SNJ54LV573AJ CFP − W Tube of 85 SNJ54LV573AW SNJ54LV573AW LCCC − FK Tube of 55 SNJ54LV573AFK SNJ54LV573AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2005, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) The ’LV573A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. GQN PACKAGE (TOP VIEW) 1 2 3 terminal assignments 4 1 2 3 4 A A 1D OE VCC 1Q B B 3D 3Q 2D 2Q C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E E GND 8D LE 8Q FUNCTION TABLE (each latch) INPUTS 2 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1D 1Q To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) VCC SN54LV573A SN74LV573A MIN MAX MIN MAX 2 5.5 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 5.5 High or low state 0 VCC 0 VCC 3-state 0 5.5 0 5.5 −50 −50 VCC = 2.3 V to 2.7 V −2 −2 VCC = 3 V to 3.6 V −8 −8 −16 −16 VCC = 2 V Low level output current Low-level Δt/Δv Input transition rise or fall rate 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 8 8 VCC = 4.5 V to 5.5 V 16 16 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 20 VCC = 4.5 V to 5.5 V TA Operating free-air temperature −55 125 V VCC × 0.3 0 VCC = 4.5 V to 5.5 V IOL 0.5 VCC × 0.3 VCC = 2 V High level output current High-level V VCC = 2.3 V to 2.7 V VCC = 4.5 V to 5.5 V IOH V 1.5 VCC = 2 V VIL UNIT −40 V V μA mA μA mA ns/V °C 85 NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV573A PARAMETER VOH TEST CONDITIONS MIN TYP MAX MIN 2 V to 5.5 V IOH = −2 mA 2.3 V 2 2 IOH = −8 mA 3V 2.48 2.48 4.5 V 3.8 VCC−0.1 TYP MAX UNIT VCC−0.1 V 3.8 IOL = 50 μA 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 0.4 IOL = 8 mA 3V 0.44 0.44 4.5 V 0.55 0.55 IOL = 16 mA 0.1 0.1 V II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 μA IOZ VO = VCC or GND 5.5 V ±5 ±5 μA ICC VI = VCC or GND, 5.5 V 20 20 μA Ioff VI or VO = 0 to 5.5 V 0 5 5 μA Ci VI = VCC or GND IO = 0 3.3 V 1.8 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN74LV573A IOH = −50 μA IOH = −16 mA VOL VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.8 pF SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER MIN SN54LV573A MAX MIN MAX SN74LV573A MIN MAX UNIT tw Pulse duration LE high 6.5 6.5 6.5 ns tsu Setup time Data before LE↓ 5 5 5 ns th Hold time Data after LE↓ 2 2 2 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER MIN SN54LV573A MAX MIN MAX SN74LV573A MIN MAX UNIT tw Pulse duration LE high 5 5 5 ns tsu Setup time Data before LE↓ 3.5 3.5 3.5 ns th Hold time Data after LE↓ 1.5 1.5 1.5 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER MIN tw Pulse duration LE high tsu Setup time th Hold time SN54LV573A MAX MIN MAX SN74LV573A MIN MAX UNIT 5 5 5 ns Data before LE↓ 3.5 3.5 3.5 ns Data after LE↓ 1.5 1.5 1.5 ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D Q LE Q LOAD CAPACITANCE TA = 25°C MIN CL = 15 pF SN54LV573A SN74LV573A TYP MAX MIN MAX MIN MAX 8.9* 15.8* 1* 18* 1 18 9.6* 16.2* 1* 19* 1 19 9.3* 16.2* 1* 19* 1 19 ten OE Q tdis OE Q 6.7* 12.6* 1* 15* 1 15 D Q 10.9 18.7 1 21 1 21 LE Q 11.6 19.1 1 23 1 23 ten OE Q 11.4 19 1 22 1 22 tdis OE Q 8.6 17.3 1 19 1 19 tpd CL = 50 pF p tsk(o) 2 UNIT ns ns 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D Q LOAD CAPACITANCE TA = 25°C MIN SN54LV573A SN74LV573A TYP MAX MIN MAX MIN MAX 6.2* 11* 1* 13* 1 13 6.8* 11.9* 1* 14* 1 14 6.6* 11.5* 1* 13.5* 1 13.5 LE Q ten OE Q tdis OE Q 4.9* 11* 1* 13* 1 13 D Q 7.7 14.5 1 16.5 1 16.5 LE Q 8.2 15.4 1 17.5 1 17.5 ten OE Q 8 15 1 17 1 17 tdis OE Q 6.2 14.5 1 16.5 1 16.5 tpd CL = 15 pF CL = 50 pF p tsk(o) 1.5 UNIT ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D Q LE Q LOAD CAPACITANCE TA = 25°C MIN CL = 15 pF SN54LV573A SN74LV573A TYP MAX MIN MAX MIN MAX 4.3* 6.8* 1* 8* 1 8 4.7* 7.7* 1* 9* 1 9 4.7* 7.7* 1* 9* 1 9 ten OE Q tdis OE Q 3.5* 7.7* 1* 9* 1 9 D Q 5.3 8.8 1 10 1 10 LE Q 5.7 9.7 1 11 1 11 ten OE Q 5.7 9.7 1 11 1 11 tdis OE Q 4.2 9.7 1 11 1 11 tpd CL = 50 pF p tsk(o) 1 UNIT ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV573A PARAMETER MIN MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.6 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.5 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 2.9 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage V 2.31 V 0.99 NOTE 6: Characteristics are for surface-mount packages only. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 TYP POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS VCC 3.3 V D to Q Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, pF LE to Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz TYP UNIT 16 5V 18 3.3 V 18.2 5V 21.3 pF 7 SN54LV573A, SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411I − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV573ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573ADBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV573A Samples SN74LV573APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV573A Samples SN74LV573ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LV573A Samples SN74LV573ARGYRG4 ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LV573A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of