SN74LV595AIPWREP

  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D Supports Mixed-Mode Voltage Operation on − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 2-V to 5.5-V VCC Operation Max tpd of 7.4 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C D D D All Ports 8-Bit Serial-In, Parallel-Out Shift Ioff Supports Partial-Power-Down Mode Operation Shift Register Has Direct Clear PW PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ description/ordering information The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 85°C TSSOP − PW Reel of 2000 SN74LV595AIPWREP LV595EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated    !"# $ %&'# "$  (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 FUNCTION TABLE INPUTS 2 SER SRCLK X X X X X X L SRCLR FUNCTION RCLK OE X X H X X L Outputs QA−QH are disabled. Outputs QA−QH are enabled. L X X Shift register is cleared. ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X ↓ H X X Shift-register state is not changed. X X X ↑ X Shift-register data is stored in the storage register. X X X ↓ X Storage-register state is not changed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q 15 2D Q C2 R 3D C3 Q 1 2D Q C2 R 3D C3 Q 2 2D Q C2 R 3D C3 Q 3 2D Q C2 R 3D C3 Q 4 2D Q C2 R 3D C3 Q 5 2D Q C2 R 3D C3 Q 6 2D Q C2 R 3D C3 Q 7 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QA QB QC QD QE QF QG QH QH′ 3 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 timing diagram SRCLK SER RCLK SRCLR OE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH′ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 2 5.5 0.5 VCC × 0.3 VCC × 0.3 0 High or low state 0 3-state 0 VCC × 0.3 5.5 V V VCC 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V −50 µA VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V −8 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate V VCC × 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current V 1.5 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current UNIT −2 mA −16 50 µA 2 8 mA 16 200 100 ns/V 20 TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 µA IOH = −2 mA VOH QH′ QA−QH QH′ QA−QH 2 V to 5.5 V 2.3 V IOH = −6 mA IOH = −8 mA QH′ QA−QH QH′ QA−QH 3.8 VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND 3.8 2 V to 5.5 V 0.1 2.3 V 0.4 0.44 3V IOL = 12 mA IOL = 16 mA ICC Ioff UNIT V 2.48 4.5 V IOL = 6 mA IOL = 8 mA VI = 5.5 V or GND VO = VCC or GND MAX 2.48 IOH = −12 mA IOH = −16 mA II IOZ TYP VCC−0.1 2 3V IOL = 50 µA IOL = 2 mA VOL MIN VCC 0.44 V 0.55 4.5 V 0.55 ±1 µA 5.5 V ±5 µA 5.5 V 20 µA 0 5 µA 0 to 5.5 V IO = 0 3.3 V 3.5 pF timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration SRCLK high or low 7 7.5 RCLK high or low 7 7.5 SRCLR low 6 6.5 5.5 5.5 SER before SRCLK↑ SRCLK↑ before RCLK↑† tsu Setup time MIN SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ 8 9 8.5 9.5 4 4 MAX UNIT ns ns th Hold time SER after SRCLK↑ 1.5 1.5 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration SRCLK high or low 5.5 5.5 RCLK high or low 5.5 5.5 5 5 SRCLR low SER before SRCLK↑ tsu Setup time MIN 3.5 3.5 SRCLK↑ before RCLK↑† 8 8.5 SRCLR low before RCLK↑ 8 9 SRCLR high (inactive) before SRCLK↑ 3 3 MAX UNIT ns ns th Hold time SER after SRCLK↑ 1.5 1.5 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration SRCLK high or low 5 RCLK high or low 5 5 5.2 5.2 SER before SRCLK↑ 3 3 SRCLK↑ before RCLK↑† 5 5 SRCLR low before RCLK↑ 5 5 2.5 2.5 SRCLR low tsu Setup time MIN SRCLR high (inactive) before SRCLK↑ MAX UNIT 5 ns ns th Hold time SER after SRCLK↑ 2 2 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL RCLK SRCLK QH′ H tPHL SRCLR QH′ tPZH tPZL OE QA−QH tPHZ tPLZ OE QA−QH tPLH tPHL RCLK QA−QH tPLH tPHL SRCLK QH′ H tPHL SRCLR QH′ tPHZ tPLZ 8 OE OE TA = 25°C TYP MAX MIN 65 80 45 CL = 50 pF 60 70 40 CL = 15 pF CL = 50 pF QA−QH QA−QH POST OFFICE BOX 655303 MIN temperature CL = 15 pF QA−QH tPLH tPHL tPZH tPZL LOAD CAPACITANCE free-air • DALLAS, TEXAS 75265 MAX range, UNIT MHz 8.4 14.2 1 15.8 8.4 14.2 1 15.8 9.4 19.6 1 22.2 9.4 19.6 1 22.2 8.7 14.6 1 16.3 8.2 13.9 1 15 10.9 18.1 1 20.3 8.3 13.7 1 15.6 9.2 15.2 1 16.7 11.2 17.2 1 19.3 11.2 17.2 1 19.3 13.1 22.5 1 25.5 13.1 22.5 1 25.5 12.4 18.8 1 21.1 10.8 17 1 18.3 13.4 21 1 23 12.2 18.3 1 19.5 14 20.9 1 22.6 ns ns 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL RCLK SRCLK QH′ H tPHL SRCLR QH′ tPZH tPZL OE QA−QH OE RCLK QA−QH tPLH tPHL SRCLK QH′ H tPHL SRCLR QH′ tPZH tPZL tPHZ tPLZ OE OE MIN 80 120 70 55 105 50 CL = 15 pF CL = 50 pF QA−QH QA−QH POST OFFICE BOX 655303 TA = 25°C TYP MAX CL = 50 pF QA−QH tPLH tPHL MIN temperature CL = 15 pF QA−QH tPLH tPHL tPHZ tPLZ LOAD CAPACITANCE free-air • DALLAS, TEXAS 75265 MAX range, UNIT MHz 6 11.9 1 13.5 6 11.9 1 13.5 6.6 13 1 15 6.6 13 1 15 6.2 12.8 1 13.7 6 11.5 1 13.5 7.8 11.5 1 13.5 6.1 14.7 1 15.2 6.3 14.7 1 15.2 7.9 15.4 1 17 7.9 15.4 1 17 9.2 16.5 1 18.5 9.2 16.5 1 18.5 9 16.3 1 17.2 7.8 15 1 17 9.6 15 1 17 8.1 15.7 1 16.2 9.3 15.7 1 16.2 ns ns 9 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL RCLK SRCLK QH′ H tPHL SRCLR QH′ tPZH tPZL OE QA−QH OE RCLK QA−QH tPLH tPHL SRCLK QH′ H tPHL SRCLR QH′ tPZH tPZL tPHZ tPLZ TA = 25°C TYP MAX MIN CL = 15 pF 135 170 115 CL = 50 pF 120 140 95 CL = 15 pF QA−QH tPLH tPHL OE CL = 50 pF QA−QH OE temperature LOAD CAPACITANCE QA−QH tPLH tPHL tPHZ tPLZ free-air QA−QH MIN MAX range, UNIT MHz 4.3 7.4 1 8.5 4.3 7.4 1 8.5 4.5 8.2 1 9.4 4.5 8.2 1 9.4 4.5 8 1 9.1 4.3 8.6 1 10 5.4 8.6 1 10 2.4 6 1 7.1 2.7 5.1 1 7.2 5.6 9.4 1 10.5 5.6 9.4 1 10.5 6.4 10.2 1 11.4 6.4 10.2 1 11.4 6.4 10 1 11.1 5.7 10.6 1 12 6.8 10.6 1 12 3.5 10.3 1 11 3.4 10.3 1 11 MIN TYP MAX ns ns noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) PARAMETER UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.3 V Quiet output, minimum dynamic VOL −0.2 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 2.8 V High-level dynamic input voltage 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 114 operating characteristics, TA = 25°C PARAMETER Cpd 10 Power dissipation capacitance TEST CONDITIONS CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 111 pF 
  
 
  
   

SCLS568B − JANUARY 2004 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL VCC Output Control ≈VCC 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV595AIPWREP ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV595EP V62/04696-01XE ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV595EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of