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SN54LV86A, SN74LV86A
SCLS392G – APRIL 1998 – REVISED FEBRUARY 2015
SNx4LV86A Quadruple 2-Input Exclusive-OR Gates
1 Features
3 Description
•
•
•
The ’LV86A devices are quadruple 2-input exclusiveOR gates designed for 2-V to 5.5-V VCC operation.
1
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 8 ns at 5 V
Typical VOLP (Output Ground Bounce) 2.3 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Latch-Up Performance Exceeds 250 mA per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
EPOS
Programmable Logic Controller (PLC)
DCS and PAC: Analog Input Module
Medical Meters: Portable
Server Motherboard
Printer
These devices contain four independent 2-input
exclusive-OR gates. They perform the Boolean
function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement
element. If one of the inputs is low, the other input is
reproduced in true form at the output. If one of the
inputs is high, the signal on the other input is
reproduced inverted at the output.
Device Information(1)
PART NUMBER
LV86A
PACKAGE
BODY SIZE (NOM)
VQFN (14)
3.50 mm × 3.50 mm
SOIC (14)
8.65 mm × 3.91 mm
SOP (14)
10.30 mm × 5.30 mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
=1
A.
These are five equivalent exclusive-OR symbols valid for an ’LV86A gate in positive logic; negation can be shown at
any two ports. See Functional Block Diagram for more information.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV86A, SN74LV86A
SCLS392G – APRIL 1998 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 2.5 V ±0.2 V .........
Switching Characteristics, VCC = 3.3 V ±0.3 V .........
Switching Characteristics, VCC = 5 V ±0.5 V ............
Noise Characteristics for SN74LV86A ......................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ................................................ 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision F (April 2005) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated operating free-air temperature maximum from 85°C to 125°C for SN74LV86A ..................................................... 5
2
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SCLS392G – APRIL 1998 – REVISED FEBRUARY 2015
6 Pin Configuration and Functions
SN54LV86A: J or W Package
SN74LV86A: D, DB, DGV, NS, or PW Package
(Top View)
14
2
13
3
12
4
11
5
10
6
9
7
8
1B
1A
NC
VCC
4B
1
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
SN54LV86A: FK Package
(Top View)
B.
NC − No internal connection
Pin Functions
PIN
I/O
1
1A
A input 1
DESCRIPTION
2
1B
B input 1
3
1Y
Output 1
4
2A
A input 2
5
2B
B input 2
6
2Y
Output 2
7
GND
8
3Y
Output 3
9
3A
A input 3
10
3B
B input 3
11
4Y
Output 4
12
4A
A input 4
13
4B
B input 4
14
VCC
Power pin
ground
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2) (3)
–0.5
VCC + 0.5 V
V
IIK
Input clamp current, VI < 0
–20
mA
IOK
Output clamp current, VO < 0
–50
mA
IO
Continuous output current, VO = 0 to VCC
–25
25
mA
Continuous current through VCC or GND
–50
50
mA
Storage temperature
–65
150
°C
Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
see
(1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
0.5
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
5.5
0
VCC
V
–50
µA
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
Δt/Δv
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
µA
2
VCC = 3 V to 3.6 V
Input transition rise or fall rate
mA
50
VCC = 2.3 V to 2.7 V
Low-level output current
V
–12
VCC = 2 V
IOL
V
0
VCC = 2 V
High-level output current
V
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
mA
ns/V
20
Operating free-air temperature
–55
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
7.4 Thermal Information
D
THERMAL METRIC (1)
DB
DGV
NS
PW
14 PINS
RθJA
Junction-to-ambient thermal resistance (2)
90.6
107.1
129.0
90.7
122.6
RθJC(top)
Junction-to-case (top) thermal resistance
50.9
59.6
52.1
48.3
51.4
RθJB
Junction-to-board thermal resistance
44.8
54.4
62.0
49.4
64.4
ψJT
Junction-to-top characterization parameter
14.7
20.5
6.5
14.6
6.7
ψJB
Junction-to-board characterization parameter
44.5
53.8
61.3
49.1
63.8
(1)
(2)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
VOL
SN74LV86A
–40°C to 125°C
SN54LV86A
VCC
TYP
MAX
MIN
VCC – 0.1
VCC – 0.1
2
2
2.48
2.48
TYP
UNIT
MAX
IOH = –50 µA
2 to 5.5 V
IOH = –2 mA
2.3 V
IOH = –6 mA
3V
IOH = –12 mA
4.5 V
IOL = 50 µA
2 to 5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
3.8
V
3.8
0.1
0.1
V
IOL = 12 mA
4.5 V
0.55
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
±1
±1
µA
ICC
VI = VCC or GND, IO = 0
5.5 V
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
µA
Ci
VI = VCC or GND
3.3 V
1.4
1.4
pF
7.6 Switching Characteristics, VCC = 2.5 V ±0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
(2)
FROM (INPUT)
TO (OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
MIN
MAX UNIT
17.6 (1)
1 (2)
21 (2)
22.6
1
26.5
TYP
MAX
CL = 15 pF
7.9 (1)
CL = 50 pF
10.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV86A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.7 Switching Characteristics, VCC = 3.3 V ±0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
(2)
FROM (INPUT)
TO (OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
MIN
MAX UNIT
11 (1)
1 (2)
13 (2)
14.5
1
16.5
TYP
MAX
CL = 15 pF
5.5 (1)
CL = 50 pF
7.4
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV86A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.8 Switching Characteristics, VCC = 5 V ±0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
(2)
6
FROM (INPUT)
TO (OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
MIN
MAX UNIT
TYP
MAX
CL = 15 pF
3.7 (1)
6.8 (1)
1 (2)
8 (2)
CL = 50 pF
5.3
8.8
1
10
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV86A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
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7.9 Noise Characteristics for SN74LV86A
VCC = 3.3 V, CL = 50 pF, TA = 25°C (see
(1)
)
PARAMETER
MIN
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.2
0.8
VOL(V)
Quiet output, minimum dynamic VOL
–0.1
–0.8
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
3.1
UNIT
V
2.31
0.99
Characteristics are for surface-mount packages only.
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF, ƒ = 10 MHz
VCC
TYP
3.3 V
8.4
5V
8.8
UNIT
pF
7.11 Typical Characteristics
7
9
8
6
7
5
tpd (ns)
tpd (ns)
6
4
3
5
4
3
2
2
1
0
-100
1
0
-50
0
50
Temperature (°C)
100
150
0
1
2
D001
Figure 1. tpd vs Temperature at 3.3 V
3
VCC (V)
4
5
6
D002
Figure 2. tpd vs VCC at 25°C
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8 Parameter Measurement Information
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
VOH
50% VCC
VOL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
VCC
Output
Control
≈VCC
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
50% VCC
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
VOH
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The ’LV86A devices are quadruple 2-input exclusive-OR gates designed for 2-V to 5.5-V VCC operation.
These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y = A ⊕
B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
9.2 Functional Block Diagram
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
=1
A.
These are five equivalent exclusive-OR symbols valid for an ’LV86A gate in positive logic; negation can be shown at
any two ports.
Figure 4. Exclusive OR
2k
=
The output is active
(low) if all inputs
stand at the same
logic level (that is, A
= B).
2k + 1
The output is active
(low) if an even
number of inputs
(that is, 0 or 2) are
active.
Figure 5. Logic-Identity Element
The output is active
(high) if an odd
number of inputs
(that is, only 1 of the
2) are active.
Figure 6. Even-Parity Element
Figure 7. Odd-Parity Element
9.3 Feature Description
•
•
Wide operating voltage range, operates from 2 to 5.5 V
Allows down voltage translation, inputs accept voltages to 5.5 V
9.4 Device Functional Modes
Table 1. Function Table
(Each Gate)
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LV86A is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.
10.2 Typical Application
5-V Bus Driver
5-V Regulated
0.1 PF
5-V Accessory
Figure 8. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Rise time and fall time specs see (Δt/ΔV) in Recommended Operating Conditions.
– Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions.
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part
– Outputs should not be pulled above VCC
10
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Typical Application (continued)
10.2.3 Application Curve
Figure 9. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends 0.1 µF and if there are multiple VCC terminals then .01 or .022 µF is recommended for
each power terminal. It is okay to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1
µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power
terminal as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC whichever make more sense or is more convenient. It is generally okay to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when
asserted. This will not disable the input section of the IOs so they also cannot float when disabled.
12.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 10. Layout Recommendation
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV86A
Click here
Click here
Click here
Click here
Click here
SN74LV86A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: SN54LV86A SN74LV86A
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV86AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV86A
SN74LV86APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
SN74LV86APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV86A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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