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SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs
1 Features
3 Description
•
•
•
•
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
1
•
•
•
•
•
•
3-State Outputs
Separate OE for all 4 buffers
Operates From 1.65 V to 3.6 V
Specified From –40°C to 85°C
and –40°C to 125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
The SN74LVC125A device features independent line
drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Inputs can be driven from either 3.3-V or 5-V devices.
This feature allows the use of this device as a
translator in a mixed 3.3-V/5-V system environment.
Device Information(1)
PART NUMBER
SN74LVC125A
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Cable Modem Termination Systems
IP Phones: Wired and Wireless
Optical Modules
Optical Networking:
– EPON or Video Over Fiber
Point-to-Point Microwave Backhaul
Power: Telecom DC/DC Modules:
– Analog or Digital
Private Branch Exchanges (PBX)
TETRA Base Stations
Telecom Base Band Units
Telecom Shelters:
– Filter Unit s
– Power Distribution Units (PDU)
– Power Monitoring Units (PMU)
– Wireless Battery Monitoring
– Remote Electrical Tilt Units (RET)
– Remote Radio Units (RRU)
– Tower Mounted Amplifiers (TMA)
Vector Signal Analyzers and Generators
Video Conferencing: IP-Based HD
WiMAX and Wireless Infrastructure Equipment
Wireless Communications Testers
xDSL Modems and DSLAM
PACKAGE (PIN)
BODY SIZE
SOIC (14)
8.65 mm × 3.91 mm
SSOP (14)
6.20 mm × 5.30 mm
SOP (14)
10.30 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
VQFN (14)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
3OE
1OE
1A
1Y
3Y
4OE
2OE
2A
3A
2Y
4A
4Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
5
5
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1 Trademarks ........................................................... 13
13.2 Electrostatic Discharge Caution ............................ 13
13.3 Glossary ................................................................ 13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision P (October 2010) to Revision Q
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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6 Pin Configuration and Functions
D, DB, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
VCC
1
14
2
13 4OE
3
12 4A
4
11 4Y
5
10 3OE
9 3A
7
8
3Y
6
GND
1A
1Y
2OE
2A
2Y
1OE
RGY PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
D, DB, NS, PW
and RGY
TYPE
DESCRIPTION
1A
2
I
Input
1OE
1
I
Output enable
1Y
3
O
Output
2A
5
I
Input
2OE
4
I
Output enable
2Y
6
O
Output
3A
9
I
Input
3OE
10
I
Output enable
3Y
8
O
Output
4A
12
I
Input
4OE
13
I
Output enable
4Y
11
O
Output
GND
7
—
Ground
VCC
14
—
Power pin
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SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
500
mW
150
°C
Continuous current through VCC or GND
Ptot
Power dissipation
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
TA = –40°C to 125°C
(4) (5)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
7.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
TA = 25°C
VCC
Supply voltage
VIH
High-level
input voltage
Operating
Data retention only
MIN
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
VIL
VI
Input voltage
VO
Output voltage
High-level
output current
0.35 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
–4
–4
–8
–8
–8
–12
–12
VCC = 3 V
–24
–24
–24
VCC = 1.65 V
4
4
4
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
8
8
8
Input transition rise or fall rate
(1)
–4
–12
Δt/Δv
V
5.5
VCC = 2.7 V
Low-level
output current
V
0
VCC = 2.3 V
IOL
UNIT
V
0.35 × VCC
VCC = 1.65 V
IOH
–40°C to 125°C
1.5
VCC = 1.65 V to 1.95 V
Low-level
input voltage
–40°C to 85°C
mA
mA
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
THERMAL METRIC (1)
RθJA
(1)
(2)
(3)
Junction-to-ambient thermal resistance
D (2)
DB (2)
NS (2)
PW (2)
RGY (3)
113
47
14 PINS
86
96
76
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.65 V to
3.6 V
IOH = –100 μA
VOH
VCC
MIN
TYP
–40°C to 85°C
MAX
MIN
–40°C to 125°C
MAX
MIN MAX
VCC – 0.2
VCC – 0.2
VCC – 0.3
IOH = –4 mA
1.65 V
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
2.2
2
IOL = 100 μA
1.65 V to
3.6 V
0.1
0.2
0.3
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
IOH = –12 mA
VOL
TA = 25°C
UNIT
V
V
II
VI = 5.5 V or GND
3.6 V
±1
±5
±20
μA
IOZ
VO = VCC or GND
3.6 V
±1
±10
±20
μA
ICC
VI = VCC or GND, IO = 0
3.6 V
1
10
40
μA
500
500
5000
μA
ΔICC
Ci
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V to
3.6 V
VI = VCC or GND
3.3 V
5
pF
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A
Y
OE
Y
OE
Y
tsk(o)
VCC
TA = 25°C
–40°C to 85°C
–40°C to 125°C
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1.8 V ± 0.15 V
1
4.5
11.8
1
12.3
1
13.8
2.5 V ± 0.2 V
1
2.7
5.8
1
6.3
1
8.4
2.7 V
1
3
5.3
1
5.5
1
7
3.3 V ± 0.3 V
1
2.5
4.6
1
4.8
1
6
1.8 V ± 0.15 V
1
4.3
13.8
1
14.3
1
15.8
2.5 V ± 0.2 V
1
2.7
6.9
1
7.4
1
9.5
2.7 V
1
3.3
6.4
1
6.6
1
8.5
3.3 V ± 0.3 V
1
2.4
5.2
1
5.4
1
7
1.8 V ± 0.15 V
1
4.3
10.6
1
11.1
1
12.6
2.5 V ± 0.2 V
1
2.2
5.1
1
5.6
1
7.7
2.7 V
1
2.5
4.8
1
5
1
6.5
3.3 V ± 0.3 V
1
2.4
4.4
1
4.6
1
3.3 V ± 0.3 V
1
UNIT
ns
ns
ns
6
1.5
ns
7.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance per gate
TEST
CONDITIONS
f = 10 MHz
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VCC
TYP
1.8 V
7.4
2.5 V
11.3
3.3 V
15
UNIT
pF
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7.8 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
10
8
6
4
One Output Switching
Four Outputs Switching
8
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN74LVC125A device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or
power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined
by the current-sourcing capability of the driver.
9.2 Functional Block Diagram
3OE
1OE
1A
1Y
3A
3Y
4OE
2OE
2A
2Y
4A
4Y
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 5.5 V
Allows down voltage translation
Inputs accept voltages to 5.5 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74LVC125A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.
10.2 Typical Application
3V
5V
1OE
VCC
1Y
C/System
Logic/LEDs
4OE
C or System
Logic
4Y
1A
4A
GND
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
10
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Typical Application (continued)
– Outputs should not be pulled above VCC.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
10.2.3 Application Curves
100
80
60
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–100
–1
–0.5 0.0
VOL – V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 5. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
Figure 6. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
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Product Folder Links: SN74LVC125A
11
SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
www.ti.com
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
12
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Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC125A
SN74LVC125A
www.ti.com
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC125A
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC125AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125ADBRG4
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125ADE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADRG3
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ADTG4
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC125A
SN74LVC125APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWE4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWRG3
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-1-260C-UNLIM
SN74LVC125APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
Addendum-Page 1
LC125A
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC125APWTE4
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125APWTG4
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC125A
SN74LVC125ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC125A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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