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SN74LVC1G06
SCES295Z – JUNE 2000 – REVISED NOVEMBER 2017
SN74LVC1G06 Single Inverter Buffer/Driver With Open-Drain Output
1 Features
3 Description
•
This single inverter buffer and driver is designed for
1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Input and Open-Drain Output Accept
Voltages up to 5.5 V
Maximum tpd of 4.5 ns at 3.3 V at 125°C
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V for open-drain
devices
Ioff Supports Partial-Power-Down Mode and BackDrive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Can Be Used For Up or Down Translation
Schmitt Trigger Action on All Ports
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
The output of the SN74LVC1G06 device is opendrain and can be connected to other open-drain
outputs to implement active-low wired-OR or activehigh wired-AND functions. The maximum sink current
is 32 mA.
This device is fully specified for partial-power-down
applications using Ioff.The Ioff circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G06DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G06DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1G06DRL
SOT-5X3 (5)
1.60 mm × 1.20 mm
SN74LVC1G06DRY
SON (6)
1.45 mm × 1.00 mm
2 Applications
SN74LVC1G06DSF
SON (6)
1.00 mm x 1.00 mm
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SN74LVC1G06YZP
DSBGA (5)
1.40 mm × 0.90 mm
SN74LVC1G06YZV
DSBGA (4)
0.90 mm × 0.90 mm
SN74LVC1G06DPW X2SON (5)
0.80 mm x 0.80 mm
•
•
AV Receivers
Blu-ray Players and Home Theaters
DVD Recorders and Players
Desktop or Notebook PCs
Digital Radio or Internet Radio Players
Digital Video Cameras (DVC)
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices
Network Projector Front-Ends
Portable Media Players
Pro Audio Mixers
Smoke Detectors
Solid State Drive (SSD): Enterprise
High-Definition (HDTV)
Tablets: Enterprise
Audio Docks: Portable
DLP Front Projection Systems
DVR and DVS
Digital Picture Frame (DPF)
Digital Still Cameras
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G06
SCES295Z – JUNE 2000 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristifcs..........................................
Switching Characteristics: –40°C to +85°C...............
Switching Characteristics: –40°C to +125°C.............
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Y (February 2017) to Revision Z
Page
•
Changed values in the Thermal Information table to align with JEDEC standards ............................................................... 5
•
Updated Feature Description to include more detailed information about specific device features. ..................................... 9
•
Added DPW layout example ................................................................................................................................................ 13
Changes from Revision X (August 2015) to Revision Y
Page
•
Changed Logic Diagram (Positive Logic) labels from: A-1, Y-3 to: A-2, Y-4.......................................................................... 1
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 14
Changes from Revision W (December 2013) to Revision X
•
Page
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information
table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Revision V (November 2012) to Revision W
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated Ioff in Features. ......................................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 5
2
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SCES295Z – JUNE 2000 – REVISED NOVEMBER 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
NC
1
A
2
GND
3
DRL Package
5-Pin SOT-5X3
Top View
VCC
5
A
2
GND
3
GND
A
2
GND
3
DRY Package
6-Pin SON
Top View
NC
1
6
A
2
5
NC
GND
3
4
Y
A
B1
GND
C1
A2
C2
4
Y
NC
VCC
Y
A
DSF Package
6-Pin SON
Top View
VCC
NC
A
GND
YZP Package
5-Pin DSBGA
Top View
A1
VCC
Y
4
NC
5
DPW Package
5-Pin X2SON
Top View
VCC
5
1
1
Y
4
DCK Package
5-Pin SC70
Top View
NC
NC
1
6
VCC
2
5
3
4
NC
Y
YZV Package
4-Pin DSBGA
Top View
VCC
A
A1
A2
VCC
GND
B1
B2
Y
Y
Pin Functions (1) (2)
PIN
NAME
DBV, DCK,
DRL, DPW
DRY,
DSF
YZP
YZV
I/O
DESCRIPTION
A
2
2
B1
A1
I
DNU
—
—
A1
—
—
Do not use
GND
3
3
C1
B1
—
Ground
—
—
—
Not connected
1
Input
NC
1
VCC
5
6
A2
A2
—
Power pin
Y
4
4
C2
B2
O
Output
(1)
(2)
5
NC – No internal connection
See mechanical drawings for dimensions.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
6.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Tj
Continuous current through VCC or GND
Junction temperature
–65
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
UNIT
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
Machine Model (MM), per A115-A
200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
MIN
MAX
Operating
1.65
5.5
Data retention only
1.5
VCC = 1.65 V to 1.95 V
VIH
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
5.5
V
IOL
Low-level output current
TA
(1)
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
Δt/Δv
VCC = 1.65 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
5
Operating free-air temperature
–40
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs application report.
6.4 Thermal Information
SN74LVC1G06
THERMAL METRIC (1)
DBV
(SOT-23)
DCK
(SC70)
DRL
(SOT-5X3)
DRY
(SON)
DPW
(X2SON)
YZV
(DSBGA)
YZP
(DSBGA)
UNIT
5 PINS
5 PINS
5 PINS
5 PINS
5 PINS
4 PINS
5 PINS
RθJA
Junction-to-ambient
thermal resistance
231.5
276.1
296.2
369.6
511
168.2
144.4
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
139.4
178.9
137.3
257.6
241.9
2.1
1.3
°C/W
RθJB
Junction-to-board
thermal resistance
71.1
70.9
145.3
230.8
374.2
55.9
39.9
°C/W
ψJT
Junction-to-top
characterization
parameter
45.2
47
14.7
77.2
45
1.1
0.5
°C/W
ψJB
Junction-to-board
characterization
parameter
70.7
69.3
145.9
231
373.3
56.3
39.7
°C/W
RθJC(bot)
Junction-to-case
(bottom) thermal
resistance
N/A
N/A
N/A
N/A
168
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metricsapplication
report.
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6.5 Electrical Characteristifcs
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOL = 100 μA
High-level
output
voltage
VOL
TYP (1)
MIN
MAX
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
IOL = 32 mA
0.55
4.5 V
II
InflectionV = 5.5 V or GND
point current I
Ioff
Off-state
current
A input
VI = 5.5 V or GND, IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.55
0 to 5.5 V
±1
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
VI or VO = 5.5 V
ICC
V
0.4
3V
IOL = 24 mA
UNIT
CI
Input
capacitance
VI = VCC or GND
3.3 V
4
pF
CO
Off-state
capacitance
VO = VCC or GND
3.3 V
5
pF
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics: –40°C to +85°C
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
PARAMETER
tpd
Propagation
delay
A
TO (OUTPUT)
Y
VCC
MIN
MAX
1.8 V ± 0.15 V
2.2
6.5
2.5 V ± 0.2 V
1.1
4
3.3 V ± 0.3 V
1.2
4
5 V ± 0.5 V
1
3
UNIT
ns
6.7 Switching Characteristics: –40°C to +125°C
over recommended operating free-air temperature range, TA = –40°C to +125°C (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM (INPUT)
Propagation
delay
A
TO (OUTPUT)
Y
VCC
MIN
MAX
1.8 V ± 0.15 V
2.2
7
2.5 V ± 0.2 V
1.1
4.5
3.3 V ± 0.3 V
1.2
4.5
5 V ± 0.5 V
1
3.5
UNIT
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
1.8 V
3
2.5 V
3
3.3 V
4
5V
6
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UNIT
pF
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6.9 Typical Characteristics
2.5
6
TPD
TPD
5
2
TPD - ns
TPD - ns
4
1.5
1
3
2
0.5
0
-100
1
0
-50
0
50
Temperature - °C
100
150
0
1
D001
Figure 1. TPD Across Temperature at 3.3-V VCC
2
3
Vcc - V
4
5
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D002
Figure 2. TPD Across VCC at 25°C
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7
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
RL
CL
(see Note A)
S1
tPZL (see Notes E and F)
VLOAD
tPLZ (see Notes E and G)
VLOAD
tPHZ/tPZH
VLOAD
LOAD CIRCUIT
INPUT
VCC
VI
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VM
tr/tf
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
VCC
VCC
3V
VCC
VLOAD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
CL
RL
V∆
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
th
VI
VM
Input
VM
VM
VM
Data Input
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VM
VM
VOL
tPHL
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
tPZL
VOH
Output
VI
Output
Control
tPHL
tPLH
VI
Output
Waveform 2
S1 at VLOAD
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VLOAD/2 − V∆
VLOAD/2
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms (Open Drain)
8
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8 Detailed Description
8.1 Overview
The SN74LVC1G06 device contains one open-drain inverter with a maximum sink current of 32 mA. This device
is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the
device is powered down. This inhibits current backflow into the device which prevents damage to the device.
8.2 Functional Block Diagram
A
2
4
Y
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 CMOS Open-Drain Outputs
The open-drain output allows the device to sink current to GND but not to source current from VCC. When the
output is not actively pulling the line low, it will go into a high impedance state (tri-state). This allows the device to
be used for a wide variety of applications, including up-translation and down-translation, as the output voltage
can be determined by an external pullup.
The drive capability of this device creates fast edges into light loads so routing and load conditions should be
considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than
the device can sustain without being damaged. It is important for the power output of the device to be limited to
avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
8.3.2 Standard CMOS Inputs
The impendence for standard CMOS inputs is high. Typically, a CMOS input is modeled as a resistor in parallel
with the input capacitance as shown in the Electrical Characteristics. The worst case resistance is calculated with
the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current,
given in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal before the standard CMOS input.
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Feature Description (continued)
8.3.3 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 5.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and the output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
Logic
Input
Output
-IIK
-IOK
GND
Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
Each input and output enter a high impedance state when the supply voltage is 0 V. The maximum leakage into
or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage as long as the input signals remain below the
maximum input voltage value specified in the Recommended Operating Conditions.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G06.
Table 1. Function Table
10
INPUT
A
OUTPUT
Y
L
Hi-Z
H
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G06 is a high-drive CMOS device that can be used to implement a high output drive buffer, such
as an LED application. It can sink 32 mA of current at 4.5 V making it ideal for high-drive applications. It is good
for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant allowing it to translate up or down to
VCC. Below shows a simple LED driver application for a single channel of the device.
9.2 Typical Application
VPU
VCC
From
MCU
Figure 6. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above 5.5 V.
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Typical Application (continued)
9.2.3 Application Curve
1600
Icc
Icc
Icc
Icc
1400
1200
1.8V
2.5V
3.3V
5V
Icc - µA
1000
800
600
400
200
0
0
20
40
Frequency - MHz
60
80
D001
Figure 7. ICC vs Frequency
12
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SN74LVC1G06
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SCES295Z – JUNE 2000 – REVISED NOVEMBER 2017
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin
as possible for best results.
11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 8 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
An example layout is given in Figure 9 for the DPW (X2SON-5) package. This example layout includes a 0402
(metric) capacitor and uses the measurements found in the example board layout appended to this end of this
datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or it can be left out of the layout
11.2 Layout Example
WORST
BETTER
BEST
Figure 8. Trace Example
4 mil
0402
0.1 …F
Bypass
Capacitor
8 mil
8 mil
8 mil
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK,
TYP
Figure 9. Example Layout With DPW (X2SON-5) Package
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G06DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C065, C06F, C06J,
C06R, C06T)
(C06H, C06P, C06S)
SN74LVC1G06DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C06F
Samples
SN74LVC1G06DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C06F
Samples
SN74LVC1G06DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C065, C06F, C06J,
C06R)
(C06H, C06P, C06S)
SN74LVC1G06DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C06F
SN74LVC1G06DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CT5, CTF, CTJ, CT
K, CTR, CTT)
(CTH, CTS)
SN74LVC1G06DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CT5, CTF, CTJ, CT
K, CTR, CTT)
(CTH, CTS)
SN74LVC1G06DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CT5, CTF, CTJ, CT
K, CTR, CTT)
(CTH, CTS)
SN74LVC1G06DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CT5, CTF, CTJ, CT
K, CTR)
(CTH, CTS)
SN74LVC1G06DCKTE4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CT5, CTF, CTJ, CT
K, CTR)
(CTH, CTS)
SN74LVC1G06DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CT5, CTF, CTJ, CT
K, CTR)
(CTH, CTS)
SN74LVC1G06DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CO
Samples
SN74LVC1G06DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(CT7, CTR)
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Aug-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G06DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CT
Samples
SN74LVC1G06DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CT
Samples
SN74LVC1G06YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CTN
Samples
SN74LVC1G06YZVR
ACTIVE
DSBGA
YZV
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CT
N
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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