SN74LVC1G126DCKR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 SN74LVC1G126 Single Bus Buffer Gate With 3-State Output 1 Features 2 Applications • • • • • • • • 1 • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Provides Down Translation to VCC Max tpd of 3.7 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model – 200-V Machine Model – 1000-V Charged-Device Model • • Cable Modem Termination Systems High-Speed Data Acquisition and Generation Military: Radars and Sonars Motor Controls: High-Voltage Power Line Communication Modems SSDs: Internal or External Video Broadcasting and Infrastructure: Scalable Platforms Video Broadcasting: IP-Based Multi-Format Transcoders Video Communication Systems 3 Description This single buffer is designed for 1.65-V to 3.6-V VCC operation. The LVC1G126 device is a single line driver with 3-state output. The output is disabled when the output-enable input is low. Device Information(1) PART NUMBER SN74LVC1G126 PACKAGE (PIN) BODY SIZE SOT-23 (5) 2.90 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm SOT (5) 1.60 mm × 1.20 mm SON (6) 1.00 mm × 1.00 mm XBGA (5) 1.40 mm × 0.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic 1 OE 2 A 4 Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 4 4 5 5 6 6 6 7 7 7 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, CL = 15 pF ...................... Switching Characteristics, –40°C to 85°C................. Switching Characteristics, –40°C to 125°C............... Operating Characteristics ........................................ Typical Characteristics ............................................ Parameter Measurement Information .................. 8 9 Detailed Description ............................................ 10 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 10 Application and Implementation........................ 11 10.1 Application Information.......................................... 11 10.2 Typical Application ............................................... 11 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 13 13.1 Trademarks ........................................................... 13 13.2 Electrostatic Discharge Caution ............................ 13 13.3 Glossary ................................................................ 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 5 Revision History Changes from Revision Q (December 2013) to Revision R • Page Added Applications, Device Information table, Handling Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1 Changes from Revision P (November 2012) to Revision Q Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5 • Added ESD warning. ............................................................................................................................................................ 13 Changes from Revision O (March 2011) to Revision P • Removed Ordering Information table. .................................................................................................................................... 1 Changes from Revision N (February 2007) to Revision O • 2 Page Page Added DSF package option to the data sheet. ...................................................................................................................... 3 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 SN74LVC1G126 www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015 6 Pin Configuration and Functions DBV PACKAGE (TOP VIEW) OE 1 A 2 GND 3 VCC 5 OE 1 A 2 GND 3 1 A 2 GND 3 6 5 4 VCC 5 OE 1 A 2 GND 3 5 VCC 4 Y Y 4 Y 4 DRY PACKAGE (TOP VIEW) OE DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) DSF PACKAGE (TOP VIEW) OE A GND VCC N.C. 1 6 2 5 3 4 VCC N.C. Y Y YZP PACKAGE (BOTTOM VIEW) GND C1 3 4 C2 A B1 2 OE A1 1 5 A2 Y VCC See mechanical drawings for dimensions. Pin Functions PIN SN74LVC1G126 NAME TYPE DESCRIPTION DBV, DCK, DRL, YZP DRY, DSF A 2 2 I GND 3 3 — Ground Pin NC — 5 — Do not connect OE 1 1 I OE Enable/Input VCC 5 6 — Power Pin Y 4 4 O Y Output A Input Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 3 SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) VI Input voltage range –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) (3) Storage temperature range –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 7.2 ESD Ratings PARAMETER V(ESD) (1) (2) 4 Electrostatic discharge DEFINITION VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 SN74LVC1G126 www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Operating Supply voltage MAX 1.65 5.5 Data retention only 1.7 VCC = 3 V to 3.6 V 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 2 VCC = 4.5 V to 5.5 V VIL V 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage UNIT 1.5 VCC = 1.65 V to 1.95 V VIH MIN 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current VCC = 1.65 V –4 VCC = 2.3 V –8 –16 VCC = 3 V VCC = 4.5 V –32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current 8 16 VCC = 3 V Δt/Δv Input transition rise or fall rate TA Operating free-air temperature mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V (1) mA –24 ns/V 5 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7.4 Thermal Information SN74LVC1G126 THERMAL METRIC RθJA (1) (1) Junction-to-ambient thermal resistance DBV DCK DRL DRY YZP 5 PINS 5 PINS 5 PINS 6 PINS 5 PINS 206 252 142 234 132 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 5 SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VOH MAX VCC – 0.1 VCC – 0.1 1.65 V 1.2 1.2 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3V TYP (1) MIN IOH = –8 mA UNIT V 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.55 0.55 0.55 0 to 5.5 V ±5 ±5 μA IOL = 16 mA 3.8 MAX IOH = –32 mA 3.8 3V IOL = 24 mA IOL = 32 mA II –40°C to 125°C TYP (1) IOH = –4 mA IOH = –24 mA A or OE inputs MIN 1.65 V to 5.5 V IOH = –16 mA VOL –40°C to 85°C VCC 4.5 V VI = 5.5 V or GND V Ioff VI or VO = 5.5 V 0 ±10 ±10 μA IOZ VO = 0 to 5.5 V 3.6 V 10 10 μA ICC VI = 5.5 V or GND 1.65 V to 5.5 V 10 10 μA ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 500 μA Ci VI = VCC or GND (1) IO = 0 3.3 V 4 4 pF All typical values are at VCC = 3.3 V, TA = 25°C. 7.6 Switching Characteristics, CL = 15 pF over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3) –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.7 6.9 0.6 4.6 0.6 3.7 0.5 3.4 ns 7.7 Switching Characteristics, –40°C to 85°C over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4) –40°C to 85°C 6 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 2.6 8 1.1 5.5 1 4.5 1 4 ns ten OE Y 2.8 9.4 1.3 6.6 1.2 5.3 1 5 ns tdis OE Y 1.6 9.8 1 5.5 1 5.5 1 4.2 ns Submit Documentation Feedback VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 SN74LVC1G126 www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015 7.8 Switching Characteristics, –40°C to 125°C over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4) –40°C to 125°C PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 2.6 9 1.1 5.7 1 4.7 1 4.2 ns ten OE Y 2.8 9.6 1.3 6.8 1.2 5.5 1 5.2 ns tdis OE Y 1.6 10 1 5.7 1 5.7 1 4.4 ns 7.9 VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd Outputs enabled Power dissipation capacitance VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 19 19 19 21 2 2 3 4 f = 10 MHz Outputs disabled UNIT pF 7.10 Typical Characteristics 10 14 12 VCC = 3 V, TA = 25°C tpd – Propagation Delay Time – ns tpd – Propagation Delay Time – ns VCC = 3 V, TA = 25°C One Output Switching 10 8 6 4 One Output Switching 8 6 4 2 2 0 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 1. Propagation Delay (Low to High Transition) vs Load Capacitance 0 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 2. Propagation Delay (High to Low Transition) vs Load Capacitance Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 7 SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com 8 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 SN74LVC1G126 www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015 Parameter Measurement Information (continued) VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 9 SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com 9 Detailed Description 9.1 Overview The SN74LVC1G126 device contains a dual buffer gate with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. 9.2 Functional Block Diagram 1 OE 2 4 A Y 9.3 Feature Description • • • • 1.65 V to 5.5 V operating voltage range Allows down voltage translation – 5 V to 3.3 V – 5 V or 3.3 V to 1.8 V Inputs accept voltages to 5.5 V – 5.5-V tolerance on input pin when VCC = 0 V Ioff feature – Allows voltage on the inputs and outputs when VCC is 0 V – Able to reduce leakage when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table INPUTS 10 OE A OUTPUT Y H H H H L L L X Z Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 SN74LVC1G126 www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN74LVC1G126 device is a high-drive CMOS device that can be used as an output enabled buffer with a high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant allowing it to translate down to VCC. 10.2 Typical Application 1.65 V to 5 V SN74LVC1G126 0.1 PF OE Input signal 1 from system VCC A GND Y Output 1 to long PCB trace or high-Z logic input Figure 5. Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions: – For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table. – For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommend Output Conditions: – Load currents should not exceed 50 mA per output and 100 mA total for the part. Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 11 SN74LVC1G126 SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com Typical Application (continued) 10.2.3 Application Curves 10 VCC VCC VCC VCC 9 8 1.8 V 2.5 V 3.3 V 5V ICC (mA) 7 6 5 4 3 2 1 0 0 20 40 Frequency (MHz) 60 80 D003 Figure 6. ICC vs Frequency 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals, then 0.01-μF or 0.022-μF capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 7. Layout Diagram 12 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 SN74LVC1G126 www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015 13 Device and Documentation Support 13.1 Trademarks NanoFree is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G126 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74LVC1G126DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C26F Samples 74LVC1G126DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C26F Samples 74LVC1G126DBVTE4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C26F Samples 74LVC1G126DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C26F Samples 74LVC1G126DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CN5 Samples 74LVC1G126DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CN5 Samples 74LVC1G126DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CN5 Samples SN74LVC1G126DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J, C26K, C26R, C 26T) SN74LVC1G126DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J, C26K, C26R) Samples SN74LVC1G126DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN K, CNR, CNT) Samples SN74LVC1G126DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN K, CNR) Samples SN74LVC1G126DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CN7, CNR) Samples SN74LVC1G126DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CN Samples SN74LVC1G126DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CN Samples SN74LVC1G126YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CN7, CNN) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of