SN74LVC1G17
SCES351W – JULY 2001 – REVISED SN74LVC1G17
SEPTEMBER 2020
SCES351W – JULY 2001 – REVISED SEPTEMBER 2020
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SN74LVC1G17 Single Schmitt-Trigger Buffer
1 Features
•
•
•
•
•
•
•
•
•
3 Description
Available in Ultra Small 0.64-mm2
Package (DPW) With 0.5-mm Pitch
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.6 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD
78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
•
•
•
•
•
The SN74LVC1G17 device contains one buffer and
performs the Boolean function Y = A.
The CMOS device has high output drive while
maintaining low static power dissipation over a broad
Vcc operating range.
The SN74LVC1G17 is available in a variety of
packages, including the ultra-small DPW package
with a body size of 0.8 mm × 0.8mm.
Device Information
DEVICE NAME
SN74LVC1G17
2 Applications
•
•
•
•
•
•
This single Schmitt-trigger buffer is designed for
1.65-V to 5.5-V VCC operation.
AV Receiver
Audio Dock: Portable
Blu-ray Player and Home Theater
MP3 Player/Recorder
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
(1)
PACKAGE(1)
BODY SIZE
SOT-23 (5)
2.9mm × 1.6mm
SC70 (5)
2.0mm × 1.25mm
X2SON (4)
0.8mm × 0.8mm
SON (6)
1.45mm × 1.0mm
SON (6)
1.0mm × 1.0mm
For all available packages, see the orderable addendum at
the end of the datasheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
intellectual
property
matters
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SCES351W – JULY 2001 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 Handling Ratings.........................................................4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics—DC Limit Changes............6
6.6 Switching Characteristics, CL = 15 pF........................ 7
6.7 Switching Characteristics AC Limit, –40°C TO
85°C.............................................................................. 7
6.8 Switching Characteristics AC Limit, –40°C TO
125°C............................................................................ 7
6.9 Operating Characteristics........................................... 7
6.10 Typical Characteristics.............................................. 7
7 Parameter Measurement Information............................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................10
9 Applications and Implementation................................ 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Trademarks............................................................. 14
12.2 Electrostatic Discharge Caution..............................14
12.3 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision V (April 2014) to Revision W (September 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Corrected part number from SN74LVC1G14 to SN74LVC1G17 in the Application Informationsection............11
• Corrected typical application schematic in Typical Application section.............................................................11
Changes from Revision U (February 2014) to Revision V (April 2014)
Page
• Added Pin Functions table. ................................................................................................................................3
• Added Handling Ratings table. .......................................................................................................................... 4
• Added Thermal Information table. ..................................................................................................................... 5
• Added Typical Characteristics. .......................................................................................................................... 7
• Added Application and Implementation section. .............................................................................................. 11
• Added Power Supply Recommendations section. ...........................................................................................12
• Added Layout section. ..................................................................................................................................... 13
Changes from Revision T (November 2012) to Revision U (February 2014)
Page
• Added Applications............................................................................................................................................. 1
• Moved Tstg to Handling Ratings table................................................................................................................. 4
• Changed MAX operating free-air temperature from 85°C to 125°C................................................................... 5
• Added –40°C to 125°C to Electrical Characteristics table.................................................................................. 6
• Added Switching Characteristics table for –40°C to 125°C temperature range..................................................7
Changes from Revision S (June 2011) to Revision T (November 2012)
Page
• Removed Ordering Information table..................................................................................................................3
2
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5 Pin Configuration and Functions
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
N.C.
1
5
N.C.
VCC
1
A
A
2
GND
3
3
N.C.
1
A
2
GND
3
DRY PACKAGE
(TOP VIEW)
5
VCC
N.C.
A
2
5
N.C.
4
Y
GND
3
4
Y
Y
4
1
6
VCC
Y
YZP PACKAGE
(TOP VIEW)
DPW PACKAGE
(TOP VIEW)
GND
VCC
5
2
GND
4
DRL PACKAGE
(TOP VIEW)
N.C.
1
A
2
5
3
4
VCC
Y
DNU
A1
A
B1
B2
GND
C1
C2
A2
YZV PACKAGE
(TOP VIEW)
A
A1
GND
B1
VCC
A2
B2
VCC
Y
DSF PACKAGE
(TOP VIEW)
N.C.
A
GND
1
6
2
5
3
4
VCC
N.C.
Y
Y
N.C. – No internal connection
See mechanical drawings for dimensions.
DNU – Do not use
Pin Functions
PIN
NAME
DBV, DCK,
DRL, DPW
DRY, DSF
YZP
YZV
NC
1
1, 5
A1, B2
–
DESCRIPTION
Not connected
A
2
2
B1
A1
Input
GND
3
3
C1
B1
Ground
Y
4
4
C2
B2
Output
VCC
5
6
A2
A2
Power terminal
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
V
range(1)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Voltage range applied to any output in the high-impedance or power-off state(1)
state(1) (2)
UNIT
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
(1)
(2)
V
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
VESD (1)
(1)
(2)
(3)
4
Human-Body Model
(HBM)(2)
Charged-Device Model (CDM)(3)
MAX
UNIT
–65
150
°C
0
2
kV
0
1
kV
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
VCC
Supply voltage
Operating
Data retention only
MIN
MAX
1.65
5.5
1.5
UNIT
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
–24
VCC = 4.5 V
IOL
Low-level output current
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
TA
mA
32
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
SN74LVC1G17
THERMAL METRIC(1)
RθJA
DCK
DRL
DRY
YZP
DPW
YZV
5 PINS
5 PINS
5 PINS
6 PINS
5 PINS
4 PINS
4 PINS
181
229
280
350
608
130
340
RθJC(top) Junction-to-case (top) thermal resistance
164
66
121
432
54
215
1
RθJB
Junction-to-board thermal resistance
62
67
171
446
51
294
39
ψJT
Junction-to-top characterization parameter
44
2
11
191
1
41
8
ψJB
Junction-to-board characterization parameter
62
66
169
442
50
294
38
RθJC(bot) Junction-to-case (bottom) thermal resistance
–
–
–
198
–
250
–
(1)
Junction-to-ambient thermal resistance
DBV
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics—DC Limit Changes
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
(Positive-going
input threshold
voltage)
VT–
(Negative-going
input threshold
voltage)
ΔVT
Hysteresis
(VT+ – VT–)
MIN
TYP
MAX
1.65 V
0.76
1.13
0.76
1.13
2.3 V
1.08
1.56
1.08
1.56
3V
1.48
1.92
1.48
1.92
4.5 V
2.19
2.74
2.19
2.74
5.5 V
2.65
3.33
2.65
3.33
1.65 V
0.35
0.59
0.35
0.59
2.3 V
0.56
0.88
0.56
0.88
3V
0.89
1.2
0.89
1.2
4.5 V
1.51
1.97
1.51
1.97
5.5 V
1.88
2.4
1.88
2.4
1.65 V
0.36
0.64
0.36
0.64
2.3 V
0.45
0.78
0.45
0.78
3V
0.51
0.83
0.51
0.83
4.5 V
0.58
0.93
0.58
0.93
5.5 V
0.69
1.04
0.69
1.04
VCC – 0.1
VCC – 0.1
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3.8
3.8
3V
4.5 V
IOL = 100 μA
1.65 V to
5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
3V
UNIT
V
V
V
V
IOH = –32 mA
V
0.55
0.55
IOL = 32 mA
4.5 V
0.55
0.55
VI = 5.5 V or GND
0 to
5.5 V
±5
±5
μA
0
±10
±10
μA
1.65 V to
5.5 V
10
10
VI or VO = 5.5 V
VI = 5.5 V or GND,
6
–40°C TO 125°C
MAX
IOH = –8 mA
ICC
IO = 0
VI = 3.6 V or GND,
3 V to
3.6 V
ΔICC
One input at VCC – 0.6 V,
Other inputs at VC C or GND
3 V to
5.5 V
CI
VI = VCC or GND
3.3 V
(1)
TYP(1)
1.2
IOL = 24 mA
Ioff
MIN
1.2
IOL = 16 mA
A input
–40°C TO 85°C
MAX
1.65 V
IOH = –24 mA
II
TYP(1)
IOH = –4 mA
IOH = –16 mA
VOL
25°C
MIN
1.65 V to
5.5 V
IOH = –100 μA
VOH
VCC
μA
0.5
1.5
500
4.5
500
μA
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 7-1 )
–40°C TO 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
9.9
1.6
5.5
1.5
4.6
0.9
4.4
ns
6.7 Switching Characteristics AC Limit, –40°C TO 85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see
Figure 7-2)
–40°C TO 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.8
11
2
6.5
1.8
5.5
1.2
5
ns
6.8 Switching Characteristics AC Limit, –40°C TO 125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see
Figure 7-2)
–40°C TO 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.8
13
2
8
1.8
6.5
1.2
6
ns
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
20
21
22
26
UNIT
pF
6.10 Typical Characteristics
3.8
8
TPD
TPD
7
3.7
6
5
TPD - ns
TPD - ns
3.6
3.5
3.4
4
3
3.3
2
3.2
3.1
-100
1
-50
0
50
Temperature - °C
100
150
0
0
1
D001
Figure 6-1. Across Temperature at 3.3V Vcc
2
3
Vcc - V
4
5
6
D002
Figure 6-2. Across Vcc at 25°C
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC1G17 device contains one Schmitt trigger buffer and performs the Boolean function Y = A. The
device functions as an independent buffer, but because of Schmitt action, it will have different input threshold
levels for a positive-going (VT+) and negative-going signals.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
8.3 Feature Description
•
•
•
•
Wide operating voltage range.
– Operates From 1.65 V to 5.5 V.
Allows Down voltage translation.
Inputs accept voltages to 5.5 V.
Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
8.4 Device Functional Modes
Table 8-1. Function Table
10
INPUT
A
OUTPUT
Y
H
H
L
L
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G17 is a high drive CMOS device that can be used for a multitude of buffer type functions where
the input is slow or noisy. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multiple
outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translate
down to VCC.
9.2 Typical Application
RF
~2.2 M
RS
~1 k
C1
~32 pF
CL
16 pF
C
50 pF
C2
~32 pF
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
• Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
• Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC .
2. Recommend Output Conditions
• Load currents should not exceed (IO max) per output and should not exceed (continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Max Ratings table.
• Outputs should not be pulled above VCC.
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9.2.3 Application Curves
10
Icc
Icc
Icc
Icc
9
8
1.8V
2.5V
3.3V
5V
Icc - mA
7
6
5
4
3
2
1
0
0
20
40
Frequency - MHz
60
80
D003
Figure 9-1. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
12
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SCES351W – JULY 2001 – REVISED SEPTEMBER 2020
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that
must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high
or low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or
is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
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12 Device and Documentation Support
12.1 Trademarks
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.3 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G17DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C175, C17F, C17J,
C17K, C17R)
(C17H, C17P, C17S)
SN74LVC1G17DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C17F
Samples
SN74LVC1G17DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C17F
Samples
SN74LVC1G17DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C175, C17F, C17J,
C17K, C17R)
(C17H, C17P, C17S)
SN74LVC1G17DBVTE4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C17F
Samples
SN74LVC1G17DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C17F
Samples
SN74LVC1G17DCK3
ACTIVE
SC70
DCK
5
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 85
(C7F, C7Z)
Samples
SN74LVC1G17DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C75, C7F, C7J, C7
K, C7R, C7T)
(C7H, C7P, C7S)
SN74LVC1G17DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
C7S
Samples
SN74LVC1G17DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
C7S
Samples
SN74LVC1G17DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C75, C7F, C7J, C7
K, C7R, C7T)
(C7H, C7P, C7S)
SN74LVC1G17DCKTE4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
C7S
Samples
SN74LVC1G17DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
C7S
Samples
SN74LVC1G17DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
S4
Samples
SN74LVC1G17DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(C77, C7R)
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
8-Jun-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G17DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(C77, C7R)
Samples
SN74LVC1G17DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C7
Samples
SN74LVC1G17DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
C7
Samples
SN74LVC1G17YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C7N
Samples
SN74LVC1G17YZVR
ACTIVE
DSBGA
YZV
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C7
(7, N)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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