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SN74LVC1T45YZTR

SN74LVC1T45YZTR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    DSBGA6_1.42X0.92MM

  • 描述:

    IC BUS TRANSCVR TRI-ST 6DSBGA

  • 数据手册
  • 价格&库存
SN74LVC1T45YZTR 数据手册
SN74LVC1T45 SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 SN74LVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs 1 Features 3 Description • This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5V, 3.3-V, and 5-V voltage nodes. ESD protection exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Available in the Texas Instruments NanoFree™ package Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V powersupply range VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state DIR input circuit referenced to VCCA Low power consumption, 4-µA maximum ICC ±24-mA output drive at 3.3 V Ioff supports partial-power-down mode operation Maximum data rates – 420 Mbps (3.3-V to 5-V translation) – 210 Mbps (translate to 3.3 V) – 140 Mbps (translate to 2.5 V) – 75 Mbps (translate to 1.8 V) Latch-up performance exceeds 100 mA per JESD 78, Class II • • • • • • • • • The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state. 2 Applications • • • • Personal electronic Industrial Enterprise Telecom NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. Functional Block Diagram Package Information PART NUMBER DIR A 5 SN74LVC1T45 3 4 VCCA B (1) PACKAGE(1) BODY SIZE (NOM) DRL (SOT, 6) 1.60 mm × 1.20 mm DBV (SOT-23, 6) 2.90 mm × 1.60 mm DCK (SC70, 6) 2.00 mm × 1.25 mm DPK (USON, 6) 1.60 mm × 1.60 mm YZP (DSBGA, 6) 1.39 mm × 0.90 mm For all available packages, see the orderable addendum at the end of the data sheet. VCCB An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................7 6.6 Switching Characteristics (VCCA = 1.8 V ± 0.15 V)..... 8 6.7 Switching Characteristics (VCCA = 2.5 V ± 0.2 V)....... 8 6.8 Switching Characteristics (VCCA = 3.3 V ± 0.3 V)....... 9 6.9 Switching Characteristics (VCCA = 5 V ±0.5 V)........... 9 6.10 Operating Characteristics....................................... 10 6.11 Typical Characteristics.............................................11 7 Parameter Measurement Information.......................... 13 8 Detailed Description......................................................14 8.1 Overview................................................................... 14 8.2 Functional Block Diagram......................................... 14 8.3 Feature Description...................................................14 8.4 Device Functional Modes..........................................15 9 Applications and Implementation................................ 16 9.1 Application Information............................................. 16 9.2 Typical Application.................................................... 16 10 Power Supply Recommendations..............................19 11 Layout........................................................................... 19 11.1 Layout Guidelines................................................... 19 11.2 Layout Example...................................................... 19 12 Device and Documentation Support..........................20 12.1 Documentation Support.......................................... 20 12.2 Receiving Notification of Documentation Updates..20 12.3 Support Resources................................................. 20 12.4 Trademarks............................................................. 20 12.5 Electrostatic Discharge Caution..............................20 12.6 Glossary..................................................................20 13 Mechanical, Packaging, and Orderable Information.................................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (February 2017) to Revision M (November 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated the thermals in the Thermal Information section.................................................................................. 6 • Updated the Switching Characterisitcs sections: extended some minimum specifications for lower delays .....8 • Updated the Ioff Supports Partial Power-Down Mode Operation section..........................................................14 • Added the Balanced High-Drive CMOS Push-Pull Outputs and VCC Isolation sections...................................14 • Updated the Power Supply Recommendations section....................................................................................19 Changes from Revision K (December 2014) to Revision L (February 2017) Page • Added DPK (USON) package information..........................................................................................................1 • Added Documentation Support section, Receiving Notification of Documentation Updates section, and Community Resources section........................................................................................................................... 1 • Added Junction temperature, TJ in Absolute Maximum Ratings ....................................................................... 5 Changes from Revision J (December 2013) to Revision K (December 2014) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................................................................................................................... 1 Changes from Revision I (December 2011) to Revision J (December 2013) Page • Updated document to new TI data sheet format - no specification changes...................................................... 1 • Removed ordering information........................................................................................................................... 1 • Added ESD warning........................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 5 Pin Configuration and Functions Figure 5-2. DCK Package, 6-Pin SC70 (Top View) Figure 5-1. DBV Package, 6-Pin SOT-23 (Top View) Figure 5-3. DRL Package, 6-Pin SOT (Top View) Figure 5-4. DPK Package, 6-Pin USON (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME DBV, DCK, DRL, DPK VCCA 1 P SYSTEM-1 supply voltage (1.65 V to 5.5 V) GND 2 G Device GND A 3 I/O Output level depends on VCC1 voltage. B 4 I/O Input threshold value depends on VCC2 voltage. DIR 5 I GND (low level) determines B-port to A-port direction. VCCB 6 P SYSTEM-2 supply voltage (1.65 V to 5.5 V) (1) P = power, G = ground, I/O = input and output, I = input Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 3 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 1 2 C A B B GND DIR A V CCA V CCB Not to scale Figure 5-5. YZP Package, 6-Pin DSBGA (Bottom View) Legend Power Input Input or Output Ground Table 5-2. Pin Functions PIN (1) 4 TYPE(1) DESCRIPTION NO. NAME A1 VCCA P SYSTEM-1 supply voltage (1.65 V to 5.5 V) A2 VCCB P SYSTEM-2 supply voltage (1.65 V to 5.5 V) B1 GND G Device GND B2 DIR I GND (low level) determines B-port to A-port direction. C1 A I/O Output level depends on VCC1 voltage. C2 B I/O Input threshold value depends on VCC2 voltage. P = power, G = ground, I/O = input and output, I = input Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage –0.5 6.5 V VI Input voltage(2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state(2) (3) A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA 150 °C 150 °C VCCA VCCB TJ Junction temperature Tstg Storage temperature (1) (2) (3) –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 Machine Model ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See (1) (2) (3) VCCI VCCA VCCB VCCO Supply voltage 1.65 o 1.95 V VIH High-level input voltage 2.3 to 2.7 V Data inputs(4) 3 to 3.6 V 4.5 to 5.5 V MIN MAX 1.65 5.5 1.65 5.5 Low-level input voltage Data inputs(4) 1.7 VCCI × 0.7 VCCI × 0.35 0.7 3 to 3.6 V 0.8 4.5 to 5.5 V VIH High-level input voltage DIR (referenced to VCCA)(5) V 2 2.3 to 2.7 V 1.65 to 1.95 V 2.3 to 2.7 V 3 to 3.6 V 4.5 to 5.5 V V VCCI × 0.65 1.65 o 1.95 V VIL UNIT V VCCI × 0.3 VCCA × 0.65 1.7 2 V VCCA × 0.7 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 5 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6.3 Recommended Operating Conditions (continued) See (1) (2) (3) VCCI VCCO MIN 1.65 to 1.95 V VIL Low-level input voltage VI Input voltage VO Output voltage DIR (referenced to VCCA)(5) MAX 2.3 to 2.7 V 0.7 3 to 3.6 V 0.8 4.5 to 5.5 V VCCA × 0.3 High-level output current 5.5 V 0 VCCO V –4 2.3 to 2.7 V –8 3 to 3.6 V –24 4.5 to 5.5 V –32 1.65 to 1.95 V IOL Low-level output current Input transition rise or fall rate Δt/Δv Data inputs Control inputs TA (1) (2) (3) (4) (5) V 0 1.65 to 1.95 V IOH UNIT VCCA × 0.35 mA 4 2.3 to 2.7 V 8 3 to 3.6 V 24 4.5 to 5.5 V 32 1.65 to 1.95 V 20 2.3 to 2.7 V 20 3 to 3.6 V 10 4.5 to 5.5 V 5 1.65 to 5.5 V 5 Operating free-air temperature –40 85 mA ns/V °C VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. 6.4 Thermal Information SN74LVC1T45 DBV (SOT-23) THERMAL METRIC(1) DCK (SC70) DPK (USON) DRL (SOT) YZP (DSBGA) UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 215.1 210.9 278.3 223.7 131.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 136.5 139.2 133.4 88.7 1.3 °C/W RθJB Junction-to-board thermal resistance 96.6 72 174.1 58.4 22.6 °C/W ψJT Junction-to-top characterization parameter 71.5 54.9 23.4 5.9 5.2 °C/W ψJB Junction-to-board characterization parameter 96.3 71.7 173.5 58.1 22.6 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6.5 Electrical Characteristics over recommended operating free-air temperature range, TA = –40 to +85°C (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS IOH = –100 μA IOH = –4 mA VOH IOH = –8 mA VCCA VCCB 1.65 to 4.5 V 1.65 to 4.5 V 1.65 V 1.65 V 1.2 2.3 V 2.3 V 1.9 3V 3V 2.4 3.8 VI = VIH IOH = –24 mA DIR ICCA 4.5 V 0.1 1.65 V 1.65 V 0.45 2.3 V 2.3 V 0.3 0.55 VI = VIL IOL = 24 mA 3V 3V IOL = 32 mA 4.5 V 4.5 V VI = VCCA or GND VO = VCCO or GND ICCA + ICCB V = VCCI or GND, IO = 0 (see Table 8-1) I A port A port at VCCA – 0.6 V, DIR at VCCA, B port = open DIR DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND ΔICCA ±1 1.65 to 5.5 V TA = –40 to +85°C ±2 TA = 25 °C ±1 0V 0 to 5.5 V TA = –40 to +85°C ±2 TA = 25 °C ±1 0 to 5.5 V 0V TA = –40 to +85°C ±2 TA = 25 °C ±1 1.65 to 5.5 V 1.65 to 5.5 V TA = –40 to +85°C ±2 1.65 to 5.5 V 1.65 to 5.5 V 3 5.5 V 0V 2 0V 5.5 V –2 1.65 to 5.5 V 1.65 to 5.5 V 3 5.5 V 0V –2 0V 5.5 V 2 1.65 to 5.5 V 1.65 to 5.5 V 4 VI = VCCI or GND, IO = 0 V 0.55 TA = 25 °C 1.65 to 5.5 V VI = VCCI or GND, IO = 0 ICCB V 1.65 to 4.5 V B port A or B port VCCO – 0.1 4.5 V VI or VO = 0 to 5.5 V IOZ UNIT 1.65 to 4.5 V A port Ioff MAX IOL = 100 μA IOL = 8 mA II TYP IOH = –32 mA IOL = 4 mA VOL MIN μA μA μA μA μA μA 50 3 to 5.5 V 3 to 5.5 V μA 50 ΔICCB B port B port at VCCB – 0.6 V, DIR at GND, A port = open Ci DIR VI = VCCA or GND 3.3 V 3.3 V TA = 25 °C 2.5 pF Cio A or B port VO = VCCA/B or GND 3.3 V 3.3 V TA = 25 °C 6 pF (1) (2) 3 to 5.5 V 3 to 5.5 V 50 μA VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 7 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6.6 Switching Characteristics (VCCA = 1.8 V ± 0.15 V) over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3 17.7 2.2 10.3 1.7 8.3 1.4 7.2 2.8 14.3 2.2 8.5 1.8 7.1 1.7 7 3 17.7 2.3 16 2.1 15.5 1.9 15.1 2.8 14.3 2.1 12.9 2 12.6 1.8 12.2 5.2 19.4 4.8 18.5 4.7 18.4 5.1 17.1 2.3 10.5 2.1 10.5 2.4 10.7 3.1 10.9 5.2 21.9 4.9 11.5 4.6 10.3 2.8 8.2 4.2 16 3.7 9.2 3.3 8.4 2.4 6.4 33.7 25.2 23.9 21.5 36.2 24.4 22.9 20.4 28.2 20.8 19 18.1 33.7 27 25.5 24.1 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Section 9.2.2.2.1 section. 6.7 Switching Characteristics (VCCA = 2.5 V ± 0.2 V) over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) 8 (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.3 16 1.5 8.5 1.3 6.4 1.1 5.1 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 2.2 10.3 1.5 8.5 1.4 8 1 7.5 2.2 8.5 1.4 7.5 1.3 7 0.9 6.2 3 8.1 3.1 8.1 2.8 8.1 3.2 8.1 1.3 5.9 1.3 5.9 1.3 5.9 1 5.8 5.2 23.7 4.1 11.4 3.9 10.2 2.4 7.1 3.9 18.9 3.2 9.6 2.8 8.4 1.8 5.3 29.2 18.1 16.4 12.8 32.2 18.9 17.2 13.3 21.9 14.4 12.3 10.9 21 15.6 13.5 12.7 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Section 9.2.2.2.1 section. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6.8 Switching Characteristics (VCCA = 3.3 V ± 0.3 V) over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.1 15.5 1.4 8 0.7 5.8 0.7 4.4 2 12.6 1.3 7 0.8 5 0.7 4 1.7 8.3 1.3 6.4 0.7 5.8 0.6 5.4 1.8 7.1 1.3 5.4 0.8 5 0.7 4.5 2.9 7.3 3 7.3 2.8 7.3 3.4 7.3 1.8 5.6 1.6 5.6 2.2 5.7 2.2 5.7 5.4 20.5 3.9 10.1 2.9 8.8 2.4 6.8 3.3 14.5 2.9 7.8 2.4 7.1 1.7 4.9 22.8 14.2 12.9 10.3 27.6 15.5 13.8 11.3 21.1 13.6 11.5 10.1 19.9 14.3 12.3 11.3 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Section 9.2.2.2.1 section. 6.9 Switching Characteristics (VCCA = 5 V ±0.5 V) over recommended operating free-air temperature range, VCCA = 5 V ±0.5 V (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.9 15.1 1 7.5 0.6 5.4 0.5 3.9 1.8 12.2 0.9 6.2 0.7 4.5 0.5 3.5 1.4 7.2 1 5.1 0.7 4.4 0.5 3.9 1.7 7 0.9 4.6 0.7 4 0.5 3.5 2.1 5.4 2.2 5.4 2.2 5.5 2.2 5.4 0.9 3.8 1 3.8 0.7 3.7 0.7 3.7 4.8 20.2 2.5 9.8 1 8.5 2.5 6.5 3.2 14.8 2.5 7.4 2.5 7 1.6 4.5 22 12.5 11.4 8.4 27.2 14.4 12.5 10 18.9 11.3 9.1 7.6 17.6 11.6 10 8.6 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Section 9.2.2.2.1 section. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 9 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6.10 Operating Characteristics TA = 25°C PARAMETER CpdA (1) CpdB (1) (1) 10 A-port input, B-port output B-port input, A-port output A-port input, B-port output B-port input, A-port output TEST CONDITIONS CL = 0 pF, f = 10 MHz, tr = tf = 1 ns CL = 0 pF, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V VCCA = VCCB = 5 V TYP TYP TYP TYP 3 4 4 4 18 19 20 21 18 19 20 21 3 4 4 4 UNIT pF pF Power dissipation capacitance per transceiver Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 6.11 Typical Characteristics 9 9 8 8 7 7 6 6 t PLH − ns 10 t PHL − ns 10 5 5 4 4 3 3 2 2 1 1 0 0 0 5 10 20 15 25 30 35 0 5 10 15 20 25 30 35 CL − pF CL − pF TA = 25°C, VCCA = 1.8 V TA = 25°C, VCCA = 1.8 V Figure 6-1. Typical Propagation Delay (A to B) vs Load Capacitance Figure 6-2. Typical Propagation Delay (B to A) vs Load Capacitance 9 8 8 7 7 6 6 t PLH − ns 10 9 t PHL − ns 10 5 5 4 4 3 3 2 2 1 1 0 0 5 10 15 20 25 30 0 35 0 5 10 CL − pF 15 20 CL − pF 25 30 35 TA = 25°C, VCCA = 2.5 V TA = 25°C, VCCA = 2.5 V Figure 6-3. Typical Propagation Delay (A to B) vs Load Capacitance Figure 6-4. Typical Propagation Delay (B to A) vs Load Capacitance 9 8 8 7 7 6 6 t PLH − ns 10 9 t PHL − ns 10 5 5 4 4 3 3 2 2 1 1 0 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 CL − pF CL − pF TA = 25°C, VCCA = 3.3 V TA = 25°C, VCCA = 3.3 V Figure 6-5. Typical Propagation Delay (A to B) vs Load Capacitance Figure 6-6. Typical Propagation Delay (B to A) vs Load Capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 11 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 10 10 9 9 8 8 7 7 6 5 6 5 4 4 3 3 2 2 1 1 0 12 t PLH − ns t PHL − ns 6.11 Typical Characteristics (continued) 0 5 10 15 20 CL − pF 25 30 35 0 0 5 10 15 20 25 30 35 CL − pF TA = 25°C, VCCA = 5 V TA = 25°C, VCCA = 5 V Figure 6-7. Typical Propagation Delay (A to B) vs Load Capacitance Figure 6-8. Typical Propagation Delay (B to A) vs Load Capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 7 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 13 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 8 Detailed Description 8.1 Overview The SN74LVC1T45 is a single-bit, dual-supply, noninverting voltage level transceiver. Pin A and the direction control pin (DIR) are supported by VCCA and pin B is supported by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on the DIR allows data transmissions from A to B and a low on the DIR allows data transmissions from B to A. 8.2 Functional Block Diagram DIR A 5 3 4 VCCA B VCCB Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V, making the device suitable for translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V, and 5-V). 8.3.2 Support High Speed Translation The SN74LVC1T45 device supports high data rate applications. The translated signal data rate can be up to 420 Mbps when the signal is translated from 3.3 V to 5 V. 8.3.3 Ioff Supports Partial Power-Down Mode Operation The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting current backflow into the device. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Charateristics. 8.3.4 Balanced High-Drive CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so impedance matching and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. Two outputs can be connected together for a stronger output drive strength. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. 8.3.5 Vcc Isolation The I/O's of both ports will enter a high-impedance state when either of the supplies are at GND, while the other supply is still connected to the device. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 8.4 Device Functional Modes Table 8-1. Function Table(1) (1) INPUT DIR OPERATION L B data to A bus H A data to B bus Input circuits of the data I/Os always are active. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 15 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 9 Applications and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC1T45 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum data rate can be up to 420 Mbps when device translates signals from 3.3 V to 5 V. 9.2 Typical Application 9.2.1 Unidirectional Logic Level-Shifting Application Figure 9-1 shows an example of the SN74LVC1T45 being used in a unidirectional logic level-shifting application. VCC1 VCC1 VCC2 1 6 2 5 3 4 SYSTEM-1 VCC2 SYSTEM-2 Figure 9-1. Unidirectional Logic Level-Shifting Application 9.2.1.1 Design Requirements For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.65 V to 5.5 V Output voltage range 1.65 V to 5.5 V 9.2.1.2 Detailed Design Procedure To begin the design process, determine the following: • Input voltage range - Use the supply voltage of the device that is driving the SN74LVC1T45 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port. • Output voltage range - Use the supply voltage of the device that the SN74LVC1T45 device is driving to determine the output voltage range.   16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 9.2.1.3 Application Curve Figure 9-2. Translation Up (1.8 V to 5 V) at 2.5 MHz 9.2.2 Bidirectional Logic Level-Shifting Application Figure 9-3 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Because the SN74LVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 VCC1 VCC2 VCC2 Pullup/Down or Bus Hold(1) I/O-1 Pullup/Down or Bus Hold(1) 1 6 2 5 3 4 I/O-2 DIR CTRL SYSTEM-1 SYSTEM-2 Figure 9-3. Bidirectional Logic Level-Shifting Application 9.2.2.1 Design Requirements See Section 9.2.1.1. 9.2.2.2 Detailed Design Procedure Table 9-2 shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. Table 9-2. SYSTEM-1 and SYSTEM-2 Data Transmission STATE DIR CTRL I/O-1 I/O-2 1 H Out In 2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown.(1) 3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown.(1) 4 L In Out SYSTEM-2 data to SYSTEM-1 (1) DESCRIPTION SYSTEM-1 data to SYSTEM-2 SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 17 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 9.2.2.2.1 Enable Times Calculate the enable times for the SN74LVC1T45 using the following formulas: • • • • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 9.2.2.3 Application Curve Figure 9-4. Translation Down (5V to 1.8 V) at 2.5 MHz 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 10 Power Supply Recommendations The SN74LVC1T45 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port and B port are designed to track VCCA and VCCB, respectively allowing for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V and 5-V voltage nodes. The recommendation is to first power-up the input supply rail to help avoid internal floating while the output supply rail ramps up. However, both power-supply rails can be ramped up simultaneously. 11 Layout 11.1 Layout Guidelines To ensure reliability of the device, the following common printed-circuit board layout guidelines are recommended: • Bypass capacitors should be used on power supplies. • Short trace lengths should be used to avoid excessive loading. • Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depends on the system requirements 11.2 Layout Example Figure 11-1. Layout Example Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 19 SN74LVC1T45 www.ti.com SCES515M – DECEMBER 2003 – REVISED NOVEMBER 2022 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Implications of Slow or Floating CMOS Inputs 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks NanoFree™ is a trademark of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC1T45DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CT15, CT1F, CT1R) Samples SN74LVC1T45DBVRE4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CT15, CT1F, CT1R) Samples SN74LVC1T45DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CT15, CT1F, CT1R) Samples SN74LVC1T45DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CT15, CT1F, CT1R) Samples SN74LVC1T45DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CT15, CT1F, CT1R) Samples SN74LVC1T45DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (TA5, TAF, TAR) Samples SN74LVC1T45DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (TA5, TAF, TAR) Samples SN74LVC1T45DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (TA5, TAF, TAR) Samples SN74LVC1T45DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (TA5, TAF, TAR) Samples SN74LVC1T45DCKTE4 ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (TA5, TAF, TAR) Samples SN74LVC1T45DCKTG4 ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (TA5, TAF, TAR) Samples SN74LVC1T45DPKR ACTIVE USON DPK 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TA7 Samples SN74LVC1T45DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (1JX, TA7, TAR) Samples SN74LVC1T45DRLRG4 ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (1JX, TA7, TAR) Samples SN74LVC1T45YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (TA2, TA7, TAN) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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