SN74LVC244ARGYR

SN74LVC244A SN74LVC244A SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 www.ti.com SN74LVC244A Octal Buffer or Driver With 3-State Outputs 1 Features 3 Description • • • These octal bus buffers are designed for 1.65-V to 3.6-V VCC operation. The SN74LVC244A devices are designed for asynchronous communication between data buses. • • • • • • • • • Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Specified From –40°C to +85°C and –40°C to +125°C Maximum tpd of 5.9 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input or Output Voltage With 3.3-V VCC) Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level Available in Ultra Small Logic QFN Package (0.5 mm Maximum Height) Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model – 1000-V Charged-Device Model 2 Applications • • • • • • Servers LED Displays Network Switches Telecom Infrastructure Motor Drivers I/O Expanders Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) SN74LVC244AN PDIP (20) 25.40 mm × 6.35 mm SN74LVC244ANS SO (20) 12.60 mm × 5.30 mm SN74LVC244ADB SSOP (20) 7.50 mm × 5.30 mm SN74LVC244ADGV TVSOP (20) 5.00 mm × 4.40 mm SN74LVC244ADW SOIC (20) 12.80 mm × 7.50 mm SN74LVC244ARGY VQFN (20) 4.50 mm × 3.50 mm SN74LVC244AZQN BGA (20) 3.00 mm × 4.00 mm SN74LVC244APW TSSOP (20) 6.50 mm × 4.40 mm SN74LVC244ARWP X1QFN (20) 2.50 mm × 3.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages. Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: SN74LVC244A 1 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................7 6.6 Switching Characteristics............................................8 6.7 Operating Characteristics........................................... 8 6.8 Typical Characteristics................................................ 9 7 Parameter Measurement Information.......................... 10 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 11 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 9.2 Typical Application.................................................... 12 10 Power Supply Recommendations..............................13 11 Layout........................................................................... 14 11.1 Layout Guidelines................................................... 14 11.2 Layout Example...................................................... 14 12 Device and Documentation Support..........................15 12.1 Receiving Notification of Documentation Updates..15 12.2 Support Resources................................................. 15 12.3 Trademarks............................................................. 15 12.4 Electrostatic Discharge Caution..............................15 12.5 Glossary..................................................................15 13 Mechanical, Packaging, and Orderable Information.................................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision AB (November 2016) to Revision AC (October 2020) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 Changes from Revision AA (June 2016) to Revision AB (November 2016) Page • Changed A2 to A4 for 2 OE in Pin Functions table.............................................................................................3 • Added ambient temperature, TA for BGA package and all other packages in Recommended Operating Conditions ..........................................................................................................................................................6 Changes from Revision Z (January 2015) to Revision AA (May 2016) Page • Updated Device Information table to show all available packages.....................................................................1 • Added RWP Package ........................................................................................................................................ 3 • Deleted GQN package from Pin Functions table................................................................................................3 • Added RWP thermal information to Thermal Information table and updated all thermal information for existing packages............................................................................................................................................................ 6 • Updated all values for ZQN column in Thermal Information table...................................................................... 6 • Added package type in Thermal Information table............................................................................................. 6 Changes from Revision Y (September 2010) to Revision Z (January 2015) Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the datasheet............................................................................................................................................................ 1 • Updated Features............................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 5 Pin Configuration and Functions VCC 2OE 1A2 C 2A4 1A3 D 2Y3 1A4 E 2A2 GND 2Y1 2Y4 2A3 2Y2 2A1 1Y1 1Y2 1Y3 1Y4 1A2 VCC 2Y4 20 2 1OE 1A1 1 Not to scale Figure 5-1. ZQN Package 20-Pin BGA Top View 1OE 1 20 VCC 1A1 2 19 2OE 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 GND 10 11 2A1 Not to scale Figure 5-2. DB, DGV, DW, N, NS, and PW Packages 20-Pin SSOP, TVSOP, SOIC, PDIP, SO, and TSSOP Front View 19 2OE 1A1 1 3 18 1Y1 2Y4 2 4 17 2A4 3 4 1Y1 1OE 17 1A1 VCC 2OE 4 19 18 3 1OE B 2 20 A 1 Thermal Pad 16 2A4 15 1Y2 14 13 2A3 1Y3 5 12 2A2 2Y2 7 14 1Y3 2Y2 6 11 1Y4 1A4 8 13 2A2 2Y1 9 12 1Y4 11 Not to scale Figure 5-4. RWP Package 20-Pin X1QFN Top View 2A1 10 GND 10 1A3 2A1 2A3 8 9 1Y2 15 2Y1 GND 16 6 7 5 1A3 Thermal Pad 1A4 2Y3 1A2 2Y3 Not to scale Figure 5-3. RGY Package 20-Pin VQFN Top View Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 3 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 Table 5-1. Pin Functions PIN DB, DGV, DW, N, NS, PW, and RGY ZQN RWP 1A1 2 A1 1 I Port 1 A1 input 1A2 4 B1 3 I Port 1 A2 input 1A3 6 C1 5 I Port 1 A3 input 1A4 8 D1 7 I Port 1 A4 input 1 OE 1 A2 20 I Output enable 1Y1 18 B4 17 O Port 1 Y1 output 1Y2 16 C4 15 O Port 1 Y2 output 1Y3 14 D4 13 O Port 1 Y3 output 1Y4 12 E4 11 O Port 1 Y4 output 2A1 11 E3 10 I Port 2 A1 input 2A2 13 D2 12 I Port 2 A2 input 2A3 15 C3 14 I Port 2 A3 input 2A4 17 B2 16 I Port 2 A4 input 2 OE 19 A4 18 I Output enable 2Y1 9 E2 8 O Port 2 Y1 output 2Y2 7 D3 6 O Port 2 Y2 output 2Y3 5 C2 4 O Port 2 Y3 output 2Y4 3 B3 2 O Port 2 Y4 output GND 10 E1 9 — Ground VCC 20 A3 19 — Power pin NAME 4 TYPE DESCRIPTION Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC MIN MAX Supply voltage –0.5 6.5 V voltage(2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 VI Input VO Voltage range applied to any output in the high-impedance or power-off state(2) state(2) (3) UNIT VO Voltage range applied to any output in the high or low IIK Input clamp current VI < 0 –50 mA VO < 0 –50 mA ±50 mA IOK Output clamp current IO Continuous output current Ptot Power dissipation TJ Junction temperature Tstg Storage temperature Continuous current through VCC or GND (1) (2) (3) (4) (5) V ±100 mA 500 mW 150 °C 150 °C TA = –40°C to +125°C(4) (5) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Section 6.3 table. For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K. For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 5 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 6.3 Recommended Operating Conditions over recommended operating free-air temperature range (unless otherwise noted)(1) TA = 25°C VCC Supply voltage VIH VIL Operating Data retention only VCC = 1.65 V to 1.95 V High-level input voltage –40 TO +125°C MAX MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.65 3.6 1.5 1.5 1.5 0.65 × VCC 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V Low-level input voltage –40 TO +85°C MIN 2 0.35 × VCC UNIT V V 2 0.35 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 V VI Input voltage 0 5.5 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH IOL TA (1) High-level output current Low-level output current Ambient temperature VCC = 1.65 V –4 –4 –4 VCC = 2.3 V –8 –8 –8 VCC = 2.7 V –12 –12 –12 VCC = 3 V –24 –24 –24 VCC = 1.65 V 4 4 4 VCC = 2.3 V 8 8 8 VCC = 2.7 V 12 12 12 VCC = 3 V 24 24 24 BGA package –40 85 All other packages –40 125 mA mA °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs , SCBA004. 6.4 Thermal Information SN74LVC244A THERMAL METRIC(1) DB(2) (SSOP) DGV(2) (TVSOP) DW (2) (SOIC) ZQN(2) (BGA) N(2) (PDIP) NS(2) (SO) PW(2) (TSSOP) RGY(3) (VQFN) RWP(3) (X1QFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 108.1 128.7 90.9 198.7 61.6 90.1 114.7 50.3 79.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 70.2 43.7 55.3 106.8 46.5 56.4 48.4 58.4 63.2 °C/W RθJB Junction-to-board thermal resistance 63.3 70.2 58.8 143.1 42.5 57.7 65.6 28.3 46.4 °C/W ψJT Junction-to-top characterization parameter 30.6 3.1 29.1 24.1 34.6 28.4 6.8 4.9 2.6 °C/W ψJB Junction-to-board characterization parameter 62.9 69.5 58.3 119.6 42.4 57.2 65.1 28.4 46.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — — n/a — — — 22.7 27.3 °C/W (1) (2) (3) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS TA = 25°C MIN TYP –40 TO +85°C MAX MIN –40 TO +125°C MAX MIN IOH = –100 µA 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 VCC – 0.3 IOH = –4 mA 1.65 V 1.29 1.2 1.05 IOH = –8 mA 2.3 V 1.9 1.7 1.55 2.7 V 2.2 2.2 2.05 IOH = –12 mA VOL VCC MAX UNIT V 3V 2.4 2.4 2.25 IOH = –24 mA 3V 2.3 2.2 2 IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 IOL = 4 mA 1.65 V 0.24 0.45 0.6 IOL = 8 mA 2.3 V 0.3 0.7 0.75 IOL = 12 mA 2.7 V 0.4 0.4 0.6 IOL = 24 mA 3V 0.55 0.55 0.8 0.3 V II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µA Ioff VI or VO = 5.5 V 0 ±1 ±10 ±20 µA IOZ VO = 0 to 5.5 V 3.6 V ±1 ±10 ±20 µA 1 10 40 1 10 40 500 500 5000 ICC VI = VCC or GND IO = 0 3.6 V ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5.5 pF (1) 3.6 V ≤ VI ≤ 5.5 V(1) µA µA This applies in the disabled state only. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 7 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 6.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A TA = 25°C VCC Y MIN OE Y OE Y MAX MIN MAX 1 7 14.4 1 14.9 1 16.4 1 5.9 10.4 1 10.9 1 12.4 2.5 V ± 0.2 V 1 4.2 7.4 1 7.9 1 10 2.7 V 1 4.2 6.7 1 6.9 1 8.2 1.5 3.9 5.7 1.5 5.9 1.5 7.2 1.5 V 1 8.3 17.8 1 18.3 1 19.8 1.8 V ± 0.15 V 1 6.4 12.1 1 12.6 1 14.1 2.5 V ± 0.2 V 1 4.6 9.1 1 9.6 1 11.7 2.7 V 1 5 8.4 1 8.6 1 10.3 1.5 4.5 7.4 1.5 7.6 1.5 9.4 1.5 V 1 7.2 15.6 1 16.1 1 17.6 1.8 V ± 0.15 V 1 5.8 11.6 1 12.1 1 13.6 2.5 V ± 0.2 V 1 3.7 7.3 1 7.8 1 9.9 2.7 V 1 3.8 6.6 1 6.8 1 8.6 1.5 3.8 6.3 1.5 6.5 1.5 3.3 V ± 0.3 V tsk(o) MIN 1.5 V 3.3 V ± 0.3 V tdis –40 TO +125°C MAX 1.8 V ± 0.15 V 3.3 V ± 0.3 V ten –40 TO +85°C TYP 3.3 V ± 0.3 V 1 UNIT ns ns ns 8 1.5 ns 6.7 Operating Characteristics TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Cpd Power dissipation capacitance per buffer/driver Outputs disabled 8 f = 10 MHz Submit Document Feedback f = 10 MHz VCC TYP 1.8 V 43 2.5 V 43 3.3 V 44 1.8 V 1 2.5 V 1 3.3 V 2 UNIT pF Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 6.8 Typical Characteristics 14 10 12 VCC = 3 V, TA = 25°C tpd – Propagation Delay Time – ns tpd – Propagation Delay Time – ns VCC = 3 V, TA = 25°C One Output Switching Four Outputs Switching Eight Outputs Switching 10 8 6 4 2 One Output Switching Four Outputs Switching Eight Outputs Switching 8 6 4 2 0 50 100 150 200 250 300 0 CL – Load Capacitance – pF Figure 6-1. Propagation Delay (Low to High Transition) vs Load Capacitance 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 6-2. Propagation Delay (High to Low Transition) vs Load Capacitance Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 9 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.5 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 2 × VCC 6V 6V 15 pF 30 pF 30 pF 50 pF 50 pF 2 kΩ 1 kΩ 500 Ω 500 Ω 500 Ω 0.1 V 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 8 Detailed Description 8.1 Overview The SN74LVC244A device is organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. The device passes data from the A inputs to the Y outputs when OE is low. The outputs are in the highimpedance state when OE is high. OE should be tied to VCC through a pullup resistor to ensure the highimpedance state during power up or power down; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 Functional Block Diagram 1OE 1A1 1A2 1A3 1A4 1 19 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages. Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description • • • Allows down voltage translation – 5 V to 3.3 V – 5 V or 3.3 V to 1.8 V Inputs accept voltage levels up to 5.5 V It is available in ultra small logic 20 pin QFN package at 0.5 mm max height with 0.4 mm pitch. 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SN74LVC244A. Table 8-1. Function Table INPUTS OE A OUTPUT Y L H H L L L H X Hi-Z Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 11 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information SN74LVC244A is a high drive CMOS device that can be used for a multitude of bus interface type applications where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC making it ideal for down translation. 9.2 Typical Application Regulated 3 V SN74LVC244A 1OE A1 uC or System Logic VCC Y1 uC System Logic LEDs A4 Y4 GND Figure 9-1. Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive currents in excess of maximum limits. The high drive will also create fast edges into light loads, so consider routing and load conditions to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions: • For rise time and fall time specification, see (Δt/ΔV) in the Section 6.3 table. • For specified high and low levels, see (VIH and VIL) in the Section 6.3 table. • Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Section 6.3 table at any valid VCC. 2. Recommended maximum Output Conditions: • Load currents should not exceed (IO max) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in the Section 6.1 table. • Outputs should not be pulled above VCC. 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 9.2.3 Application Curves 60 100 TA = 25°C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 80 TA = 25°C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 40 20 I OH – mA I OL – mA 60 40 0 –20 –40 20 –60 0 –80 –20 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –100 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOH – V VOL – V Figure 9-2. Output Drive Current (IOL) vs LOW-level Output Voltage (VOL) Figure 9-3. Output Drive Current (IOH) vs HIGH-level Output Voltage (VOH) 10 Power Supply Recommendations The power supply may be any voltage between the MIN and MAX supply voltage rating located in the Section 6.3 table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1 μF capacitor is recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01 μF or 0.022 μF capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 13 SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 11 Layout 11.1 Layout Guidelines Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally, they will be tied to GND or VCC, whichever makes more sense or is more convenient. 11.2 Layout Example VCC Unused Input Input Output Unused Input Output Input Figure 11-1. Layout Diagram 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A SN74LVC244A www.ti.com SCAS414AC – NOVEMBER 1992 – REVISED OCTOBER 2020 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74LVC244A 15 PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC244ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244ADBRE4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244ADBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A SN74LVC244ADWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A SN74LVC244ADWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A SN74LVC244ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LVC244A SN74LVC244ADWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A SN74LVC244AN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 125 SN74LVC244AN SN74LVC244ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC244A SN74LVC244APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWRG3 ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244APWTE4 ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 20-Feb-2021 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC244APWTG4 ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A SN74LVC244ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC244A SN74LVC244ARGYRG4 ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC244A SN74LVC244ARWPR ACTIVE X1QFN RWP 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC244A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of