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SN74LVC2G157
SCES207N – APRIL 1999 – REVISED MARCH 2019
SN74LVC2G157 Single 2-Line to 1-Line data selector multiplexer
1 Features
3 Description
•
This single 2-line to 1-line data selector multiplexer is
designed for 1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ package
Supports 5-V VCC operation
Inputs accept voltages to 5.5 V
Max tpd of 6 ns at 3.3 V
Low power consumption, 10-µA Maximum ICC
±24-mA Output drive at 3.3 V
Typical VOLP (Output ground bounce)
2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports live insertion, partial-power-down
mode, and back-drive protection
Can be used as a down translator to translate
inputs from a maximum of 5.5 V down
to the VCC Level
Latch-up performance exceeds 100 mA per
JESD 78, Class II
ESD Protection exceeds JESD 22
– 2000-V Human body model (A114-A)
– 1000-V Charged-device model (C101)
The SN74LVC2G157 device features a common
strobe (G) input. When the strobe is high, Y is low
and Y is high. When the strobe is low, a single bit is
selected from one of two sources and is routed to the
outputs. The device provides true and complementary
data.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC2G157DCT
Barcode scanner
Cable solutions
E-books
Embedded PC
Field transmitter: temperature or pressure sensors
Fingerprint biometrics
HVAC: Heating, ventilating, and air conditioning
Network-attached storage (NAS)
Server motherboard and PSU
Software defined radio (SDR)
TV: High definition (HDTV), LCD, and digital
Video communications systems
Wireless data access cards, headsets, keyboards,
mice, and LAN cards
BODY SIZE (NOM)
2.95 mm × 2.80 mm
SN74LVC2G157DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G157YZP
1.91 mm × 0.91 mm
DSBGA (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
PACKAGE
SSOP (8)
A
1
5
B
G
A/B
2
3
Y
Y
7
6
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G157
SCES207N – APRIL 1999 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics .........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (June 2015) to Revision N
Page
•
Changed YZP package pinout drawing to match mechanical data drawing; and, pin functions description for clarity ........ 3
•
Added additional thermal metrics for all packages................................................................................................................. 5
•
Added detailed feature description sections for Standard CMOS Inputs, Balanced High-Drive CMOS Push-Pull
Outputs, and Negative Clamping Diodes. .............................................................................................................................. 8
•
Added improved Design Requirements and Detailed Design Procedure............................................................................. 10
•
Changed verbiage to better reflect recommendations for this specific device rather than logic devices in general............ 12
•
Added layout example for the YZP package. ....................................................................................................................... 12
Changes from Revision L (January 2014) to Revision M
Page
•
Added ESD Ratings table....................................................................................................................................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics ................................................................................................................................................ 6
•
Added Mechanical, Packaging, and Orderable Information section..................................................................................... 14
Changes from Revision K (January 2007) to Revision L
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table ..................................................................................................................................... 1
•
Updated Features ................................................................................................................................................................... 1
•
Added Device Information table ............................................................................................................................................. 1
2
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SCES207N – APRIL 1999 – REVISED MARCH 2019
5 Pin Configuration and Functions
DCT Package
8-Pin SSOP
Top View
DCU Package
8-Pin VSSOP
Top View
A
1
8
VCC
B
2
7
G
Y
3
6
A/B
GND
4
5
Y
A
B
Y
GND
1
2
3
8
7
6
4
5
VCC
G
A/B
Y
YZP Package
8-Pin DSBGA
Bottom View
GND
D1
D2
Y
Y
C1
C2
A/B
B
B1
B2
G
A
A1
A2
VCC
Drawing are not to scale. See mechanical drawings for dimensions
Pin Functions
PIN
I/O
DESCRIPTION
SSOP,
VSSOP
DSBGA
A
1
A1
Input
Data Input A
A/B
6
C2
Input
Input Selector
B
2
B1
Input
Data Input B
G
7
B2
Input
Common Strobe Input
GND
4
D1
—
Ground
VCC
8
A2
—
Positive Supply
Y
5
D2
Output
Output
Y
3
C1
Output
Inverted Output
NAME
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
Tstg
Storage temperature
TJ
Junction temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
VCC
(1)
.
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
1.5
Low-level input voltage
VI
Input voltage
VO
Output voltage
1.7
High-level output current
0.7 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
4
0.3 × VCC
5.5
V
0
VCC
V
–4
VCC = 2.3 V
–8
VCC = 3 V
V
0
VCC = 1.65 V
VCC = 4.5 V
(1)
V
2
VCC = 4.5 V to 5.5 V
IOH
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
–16
mA
–24
–32
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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Recommended Operating Conditions (continued)
See (1).
MIN
MAX
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
UNIT
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
ns/V
5
–40
85
°C
6.4 Thermal Information
SN74LVC2G157
THERMAL METRIC (1)
DCT (SSOP)
DCU (VSSOP) YZP (DSBGA)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
192.0
289.9
99.9
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
70.2
86.9
1.0
°C/W
RθJB
Junction-to-board thermal resistance
105.2
208.5
27.8
°C/W
ψJT
Junction-to-top characterization parameter
7.7
23.1
0.4
°C/W
ψJB
Junction-to-board characterization parameter
103.6
206.5
27.8
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOH = –24 mA
IOH = –32 mA
4.5 V
IOL = 100 µA
0.1
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
0.4
3V
IOL = 32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
V
0.55
4.5 V
Ioff
(1)
3.8
1.65 V to 5.5 V
IOL = 24 mA
II
2.3
IOL = 4 mA
IOL = 16 mA
A, B, or
control inputs
V
2.4
3V
UNIT
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN TYP (1) MAX
VCC
0.55
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
tpd
A/B
Y or Y
G
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
4.4
14
2.1
4.9
16
2.5
4.2
14
2
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
8
2
6
1.4
4
9
2.1
6
1.6
4
8
1.6
6
1.3
4
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
VCC = 1.8 V
f = 10 MHz
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
35
35
37
40
UNIT
pF
6.8 Typical Characteristics
41
Power Dissipation Capacitance (CPD)
40
39
38
37
36
35
Typ. Char.
34
0
1
2
3
4
5
6
Supply Voltage [VCC] (V)
C001
Figure 1. Voltage vs Capacitance
6
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
This single 2-line to 1-line data selector multiplexer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G157 device features a common strobe (G) input. When the strobe is high, Y is low and Y is
high. When the strobe is low, a single bit is selected from one of two sources and is routed to the outputs. The
device provides true and complementary data.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
A
1
5
B
G
A/B
2
3
Y
Y
7
6
8.3 Feature Description
The SN74LVC2G157 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows it to be used in a
broad range of systems. The 5.5 V I/Os allow down translation and also allow voltages at the inputs when VCC =
0.
8.3.1 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics . The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics , using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be
followed at all times.
8.3.3 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 3.
8
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Feature Description (continued)
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 3. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1 lists the functional modes for SN74LVC2G157.
Table 1. Function Table
INPUTS
OUTPUTS
G
A/B
A
B
Y
Y
H
X
X
X
L
H
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2G157 allows a single controller input to receive data from two different digital signal sources. In
this application, a digital temperature sensor's output and a digital photo sensor's output are multiplexed. Both of
these sensors have a relatively slow read rate, typically less than one read per second.
9.2 Typical Application
VCC = 5 V
_
A/B
VCC
A
MCU
(MSP43x)
Temp.
Sensor
Y
B
GND
Photo
Sensor
Figure 4. Multiplexer Controlled by Processor
9.2.1 Design Requirements
• 5-V Operation
• Selectable input from two digital signal sources
– Select LOW: Temperature Sensor, 1 kbps 5-V signal
– Select HIGH: Photo Sensor, 1 kbps 5-V signal
• 15 pF, low leakage CMOS load
9.2.1.1 Power
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions . The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics .
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74LVC2G157 plus the maximum supply current, ICC, listed in Electrical Characteristics . The logic device can
only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to
exceed the maximum total current through GND or VCC listed in Absolute Maximum Ratings.
The SN74LVC2G157 can drive a load with a total capacitance less than or equal to 50 pF connected to a highimpedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
10
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Typical Application (continued)
CAUTION
The maximum junction temperature, TJ(max) listed in
Absolute Maximum Ratings, is an additional limitation to prevent damage to the device.
Do not violate any values listed in the Absolute Maximum Ratings
. These limits are provided to prevent damage to the device.
9.2.1.2 Inputs
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74LVC2G157, as specified in Electrical Characteristics , and the desired input transition rate. A 10 kΩ resistor
value is often used due to these factors.
The SN74LVC2G157 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions .
Refer to Feature Descriptionfor additional information regarding the inputs for this device.
9.2.1.3 Outputs
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics . Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics .
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor, typically 0.1 µF, from VCC to GND. The capacitor needs to be placed physically
close to the device and electrically close to both the VCC and GND pins. An example layout is shown in
Figure 7.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LVC2G157 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
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Typical Application (continued)
9.2.3 Application Curve
20.00
Max tpd (ns)
15.00
10.00
5.00
0.00
0.00
1.00
2.00
3.00
4.00
5.00
Voltage (V)
6.00
7.00
C001
Figure 5. Max propagation delay vs voltage for the LVC logic family
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions . Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 7.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
12
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SN74LVC2G157
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SCES207N – APRIL 1999 – REVISED MARCH 2019
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 6. Trace Example
VCC
GND
Avoid 90°
corners for
signal lines
Unused output
left floating
Bypass capacitor placed
close to the device
0.1 F
A
A1
A2
VCC
B
B1
B2
G
Y
C1
C2
A/B
GND
D1
D2
Y
Unused
input tied
to GND
Figure 7. Example layout for SN74LVC2G157
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74LVC2G157DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C57
(R, Z)
74LVC2G157DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C57R
74LVC2G157DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C57R
SN74LVC2G157DCT3
ACTIVE
SM8
DCT
8
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 85
C57
Z
SN74LVC2G157DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C57
(R, Z)
SN74LVC2G157DCTRG4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C57
(R, Z)
SN74LVC2G157DCU3
ACTIVE
VSSOP
DCU
8
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 85
57
CZ
SN74LVC2G157DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C57J, C57Q, C57R)
SN74LVC2G157DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C57J, C57Q, C57R)
SN74LVC2G157YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(C37, C3N)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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