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SN74LVC2G17
SCES381N – JANUARY 2002 – REVISED JANUARY 2015
SN74LVC2G17 Dual Schmitt-Trigger Buffer
1 Features
3 Description
•
•
This dual Schmitt-Trigger buffer is designed for 1.65V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
•
Schmitt-Trigger inputs provide hysteresis
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.4 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode Operation and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
The SN74LVC2G17 device contains two buffers and
performs the Boolean function Y = A. The device
functions as two independent buffers, but because of
Schmitt action, it may have different input threshold
levels for positive-going (VT+) and negative-going
(VT–) signals.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC2G17
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AV Receivers
Audio Docks: Portable
Blu-ray Players and Home Theater
MP3 Players/Recorders
Personal Digital Assistants (PDAs)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drives (SSDs): Client and Enterprise
TVs: LCD/Digital and High-Definition (HDTVs)
Tablets: Enterprise
Video Analytics: Server
Wireless Headsets, Keyboards, and Mice
PACKAGE (PIN)
BODY SIZE
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (6)
2.00 mm × 1.25 mm
SON (6)
1.45 mm × 1.00 mm
SON (6)
1.00 mm × 1.00 mm
DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1
6
1A
1Y
3
2A2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G17
SCES381N – JANUARY 2002 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
5
5
6
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics, –40°C to 85°C ................
Switching Characteristics, –40°C to 125°C ..............
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
9
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
10 Application and Implementation.......................... 9
10.1 Application Information .......................................... 9
10.2 Typical Power Button Circuit .................................. 9
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision M (November 2013) to Revision N
•
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision L (September 2013) to Revision M
Page
•
Updated document formatting. ............................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4
Changes from Revision K (July 2012) to Revision L
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Added ESD warning. ............................................................................................................................................................ 12
Changes from Revision J (June 2012) to Revision K
•
2
Page
Updated pin out graphic. ........................................................................................................................................................ 3
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SCES381N – JANUARY 2002 – REVISED JANUARY 2015
6 Pin Configuration and Functions
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
6
1
1A
1Y
1
1A
GND
GND
5
2
2
3
4
5
2A
3 4
2Y
GND
2 5
VCC
1A
1 6
1Y
1Y
VCC
VCC
2A
2A
6
YZP PACKAGE
(BOTTOM VIEW)
3
4
DRY PACKAGE
(TOP VIEW)
1A
1
6
1Y
GND
2
5
VCC
2A
3
4
2Y
DSF PACKAGE
(TOP VIEW)
1A
1
6
1Y
GND
2
5
VCC
2A
3
4
2Y
2Y
2Y
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
1A
1
I
Input 1
1Y
6
O
Output 1
2A
3
I
Input 2
2Y
4
O
Output 2
GND
2
—
Ground
VCC
5
—
Power Pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature under bias
Tstg
Storage temperature range
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
VESD
(1)
(2)
(3)
(1)
(2)
Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all
pins (3)
VALUE
UNIT
2000
V
1000
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
Operating
High-level output current
MIN
MAX
1.65
5.5
V
0
5.5
V
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
Low-level output current
8
16
VCC = 3 V
(1)
4
Operating free-air temperature
mA
24
VCC = 4.5 V
TA
mA
–24
VCC = 4.5 V
IOL
UNIT
32
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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7.4 Thermal Information
SN74LVC2G17
THERMAL METRIC (1)
DBV
DCK
YZP
DRY
DSF
UNIT
234
300
°C/W
6 PINS
Junction-to-ambient thermal resistance (2)
RθJA
(1)
(2)
165
259
123
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
ΔVT
Hysteresis
(VT+ – VT–)
VOH
MAX
1.4
0.7
1.4
1.0
1.7
1.0
1.7
3V
1.3
2.0
1.3
2.0
4.5 V
1.9
3.1
1.9
3.1
5.5 V
2.2
3.7
2.2
3.7
1.65 V
0.3
0.7
0.3
0.7
2.3 V
0.4
1
0.4
1.0
3V
0.8
1.3
0.8
1.3
4.5 V
1.1
2
1.1
2.0
5.5 V
1.4
2.5
1.4
2.5
1.65 V
0.3
0.8
0.3
0.8
2.3 V
0.4
0.9
0.35
0.9
3V
0.4
1.1
0.4
1.1
4.5 V
0.6
1.3
0.6
1.3
0.7
1.4
0.7
1.4
VCC – 0.1
VCC – 0.1
1.65 V
1.2
1.2
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
3.8
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
0.55
0.55
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
IO = 0
V
V
V
3.8
3V
IOL = 32 mA
UNIT
V
IOH = –32 mA
IOL = 24 mA
(1)
TYP (1)
0.7
IOH = –8 mA
IOL = 16 mA
A input
MIN
IOH = –4 mA
IOH = –24 mA
II
–40°C to 125°C
MAX
2.3 V
1.65 V to 5.5 V
IOH = –16 mA
VOL
TYP (1)
1.65 V
5.5 V
IOH = –100 μA
–40°C to 85°C
MIN
V
0 to 5.5 V
±5
±5
μA
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
4
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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7.6 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.9
9.3
1.9
5.7
2.2
5.4
1.5
4.3
ns
7.7 Switching Characteristics, –40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.9
9.8
1.9
6.2
2.2
5.9
1.5
4.8
ns
7.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
17
18
19
21
UNIT
pF
7.9 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
10
8
6
4
One Output Switching
8
6
4
2
2
0
50
100
150
200
250
300
0
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
6
50
100
150
200
250
300
CL – Load Capacitance – pF
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram
1
6
1A
1Y
3
4
2A2
Y
9.3 Feature Description
•
•
•
•
•
1.65 V to 5.5 V operating voltage range
Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
Inputs accept voltages to 5.5 V
– 5-V tolerance on input pin
Ioff feature
– Allows voltage on the inputs and outputs when VCC is 0 V
– Able to reduce leakage when VCC is 0 V
Schmitt-Trigger Input can improve the noise immunity capability
9.4 Device Functional Modes
8
INPUT
A
OUTPUT
Y
H
H
L
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LVC2G17 device contains two buffers and performs the Boolean function Y = A. The device functions
as two independent buffers, but because of Schmitt action, it may have different input threshold levels for
positive-going (VT+) and negative-going (VT–) signals.
10.2 Typical Power Button Circuit
3V
3V
SN74LVC2G17
1A
GND
2A
1Y
VCC
2Y
CLK
D
Q
GND
VCC
PRE
CLR
Q
MCU
SN74LVC1G74
3V
Figure 4. Device Power Button Circuit
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions
should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
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Typical Power Button Circuit (continued)
10.2.3 Application Curves
60
40
100
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
80
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OL – mA
I OH – mA
60
0
–20
–40
40
20
–60
0
–80
–100
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–20
–0.2
0.0
VOH – V
Figure 5. Output Current Drive
vs HIGH-level Output Voltage
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL – V
Figure 6. Output Current Drive
vs LOW-level Output Voltage
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
10
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12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
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13 Device and Documentation Support
13.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
12
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC2G17DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C175, C17F, C17K,
C17R)
SN74LVC2G17DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C175, C17F, C17K,
C17R)
SN74LVC2G17DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C17F, C17R)
SN74LVC2G17DCK3
ACTIVE
SC70
DCK
6
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 85
(C7F, C7Z)
SN74LVC2G17DCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C75, C7F, C7J, C7
K, C7R)
SN74LVC2G17DCKRE4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
SN74LVC2G17DCKRG4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
SN74LVC2G17DCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C75, C7F, C7J, C7
K, C7R)
SN74LVC2G17DCKTE4
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
SN74LVC2G17DCKTG4
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C75
SN74LVC2G17DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C7
SN74LVC2G17DSF2
ACTIVE
SON
DSF
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C7
SN74LVC2G17DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C7
SN74LVC2G17YZPR
ACTIVE
DSBGA
YZP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(C77, C7N)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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