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SN74LVC2G66
SCES325N – JULY 2001 – REVISED AUGUST 2018
SN74LVC2G66 Dual Bilateral Analog Switch
1 Features
3 Description
•
This dual bilateral analog switch is designed for
1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
Rail-to-Rail Input/Output
Low ON-State Resistance, Typically ≉6 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
The SN74LVC2G66 device can handle both analog
and digital signals. The SN74LVC2G66 device
permits signals with amplitudes of up to 5.5 V (peak)
to be transmitted in either direction.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
Each switch section has its own enable-input control
(C). A high-level voltage applied to C turns on the
associated switch section.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-analog
conversion systems.
2 Applications
•
•
•
•
•
•
Wireless Devices
Audio and Video Signal Routing
Portable Computing
Wearable Devices
Signal Gating, Chopping, Modulation or
Demodulation (Modem)
Signal Multiplexing for Analog-to-Digital and
Digital-to-Analog Conversion Systems
Device Information(1)
PART NUMBER
SN74LVC2G66DCT
PACKAGE
SSOP (8)
BODY SIZE (NOM)
2.95 mm × 2.80 mm
SN74LVC2G66DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G66YZP
1.91 mm × 0.91 mm
DSBGA (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Switch (Positive Logic)
1A
1C
1
2
1B
7
One of Two Switches
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G66
SCES325N – JULY 2001 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
6
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics .........................................
Analog Switch Characteristics ..................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (May 2018) to Revision N
•
Page
Changed the YZP pin configuration ...................................................................................................................................... 3
Changes from Revision L (September 2015) to Revision M
Page
•
Updated pinout image and the Pin Function table ................................................................................................................ 3
•
Changed pin 3 Name From: 1C To: 2C ................................................................................................................................ 3
•
Changed the Thermal Information table for the DCT package .............................................................................................. 5
Changes from Revision K (January 2014) to Revision L
Page
•
Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Typical Characteristics section, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
•
Added Thermal Information table ........................................................................................................................................... 5
Changes from Revision J (December 2011) to Revision K
Page
•
Updated document to new TI data sheet format--no specification changes. ......................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
2
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SCES325N – JULY 2001 – REVISED AUGUST 2018
5 Pin Configuration and Functions
DCT Package
8-Pin SSOP
Top View
DCU Package
8-Pin VSSOP
Top View
1A
1
8
VCC
1A
1
8
VCC
1B
2
7
1C
1B
2
7
1C
2C
3
6
2B
2C
3
6
2B
GND
4
5
2A
GND
4
5
2A
Not to scale
Not to scale
YZP Package
8-Pin DSBGA
Bottom View
1
2
D
GND
2A
C
2C
2B
B
1B
1C
A
1A
VCC
Not to scale
See mecahnical drawings for dimensions.
Pin Functions
PIN
I/O
DESCRIPTION
DCT
DCU
YZP
1A
1
A1
I/O
Bidirectional signal to be switched
1B
2
B1
I/O
Bidirectional signal to be switched
2C
3
C1
I
2A
5
D2
I/O
Bidirectional signal to be switched
2B
6
C2
I/O
Bidirectional signal to be switched
1C
7
B2
I
GND
4
D1
—
Ground pin
VCC
8
A2
—
Power pin
NAME
Controls the switch (L = OFF, H = ON)
Controls the switch (L = OFF, H = ON)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage (2)
–0.5
6.5
V
(2) (3)
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Switch I/O voltage (2) (3) (4)
IIK
Control input clamp current
VI < 0
–50
mA
II/OK
I/O port diode current
VI/O < 0 or VI/O > VCC
–50
mA
IT
On-state switch current
VI/O = 0 to VCC
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
(4)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
(1)
.
VCC
Supply voltage
VI/O
I/O port voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage, control input
MIN
MAX
1.65
5.5
V
0
VCC
V
VCC × 0.65
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage, control input
VI
Control input voltage
TA
(1)
4
Input transition rise or fall time
V
VCC × 0.35
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
Δt/Δv
V
VCC × 0.3
0
5.5
VCC = 1.65 V to 1.95 V
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
VCC = 4.5 V to 5.5 V
10
Operating free-air temperature
UNIT
–40
85
V
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC2G66
THERMAL METRIC (1)
DCT (SSOP)
DCU (VSSOP) YZP (DSBGA)
UNIT
8 PINS
8 PINS
8 PINS
204.4
102
°C/W
RθJA
Junction-to-ambient thermal resistance
186.1
RθJC(top)
Junction-to-case (top) thermal resistance
116.5
77
—
°C/W
RθJB
Junction-to-board thermal resistance
98.6
83.2
—
°C/W
ψJT
Junction-to-top characterization parameter
42.2
7.1
—
°C/W
ψJB
Junction-to-board characterization parameter
97.6
82.7
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
ON-state switch resistance
ron(p)
Peak ON-state resistance
TEST CONDITIONS
VI = VCC or GND,
VC = VIH
(see Figure 3 and Figure 1)
VI = VCC to GND,
VC = VIH
(see Figure 3 and Figure 1)
VCC
IS = 4 mA
1.65 V
IS = 8 mA
2.3 V
IS = 24 mA
3V
IS = 32 mA
MIN TYP (1)
MAX
12.5
30
9
20
7.5
15
4.5 V
6
10
IS = 4 mA
1.65 V
85
120 (1)
IS = 8 mA
2.3 V
22
30 (1)
IS = 24 mA
3V
12
20
IS = 32 mA
4.5 V
7.5
15
IS = 4 mA
1.65 V
7
IS = 8 mA
2.3 V
5
IS = 24 mA
3V
3
IS = 32 mA
4.5 V
UNIT
Ω
Ω
Difference of ON-state resistance
between switches
VI = VCC to GND,
VC = VIH
(see Figure 3 and Figure 1)
IS(off)
OFF-state switch leakage current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
VC = VIL (see Figure 4)
5.5 V
IS(on)
ON-state switch leakage current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 5)
5.5 V
II
Control input current
VC = VCC or GND
5.5 V
ICC
Supply current
VC = VCC or GND
5.5 V
ΔICC
Supply-current change
VC = VCC – 0.6 V
5.5 V
Cic
Control input capacitance
5V
3.5
pF
Cio(off)
Switch input / output capacitance
5V
6
pF
Cio(on)
Switch input / output capacitance
5V
14
pF
Δron
(1)
Ω
2
±1
±0.1 (1)
±1
±0.1 (1)
±1
±0.1 (1)
10
1 (1)
500
μA
μA
μA
μA
μA
TA = 25°C
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
ten (2)
C
(3)
C
PARAMETER
tdis
(1)
(2)
(3)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MIN
MAX
0.6
ns
A or B
2.3
10
1.6
5.6
1.5
4.4
1.3
3.9
ns
A or B
2.5
10.5
1.2
6.9
2
7.2
1.1
6.3
ns
1.2
MAX
MIN
UNIT
MIN
2
MAX
VCC = 5 V
± 0.5 V
0.8
MAX
tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
6.7 Analog Switch Characteristics
TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response
(switch on)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
(1)
Crosstalk
(between switches)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
Crosstalk
(control input to signal output)
C
A or B
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 8)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
Feedthrough attenuation
(switch off)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
(1)
6
VCC
TYP
1.65 V
35
2.3 V
120
3V
175
4.5 V
195
1.65 V
>300
2.3 V
>300
3V
>300
4.5 V
>300
1.65 V
–58
2.3 V
–58
3V
–58
4.5 V
–58
1.65 V
–42
2.3 V
–42
3V
–42
4.5 V
–42
1.65 V
35
2.3 V
50
3V
70
4.5 V
100
1.65 V
–58
2.3 V
–58
3V
–58
4.5 V
–58
1.65 V
–42
2.3 V
–42
3V
–42
4.5 V
–42
UNIT
MHz
dB
mV
dB
Adjust fin voltage to obtain 0 dBm at input.
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Analog Switch Characteristics (continued)
TA = 25°C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 10)
Sine-wave distortion
A or B
B or A
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 10)
VCC
TYP
1.65 V
0.1%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
1.65 V
0.15%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
UNIT
6.8 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
8
9
9.5
11
f = 10 MHz
UNIT
pF
6.9 Typical Characteristics
100
VCC = 1.65 V
ron - Ω
VCC = 2.3 V
VCC = 3.0 V
10
1
0.0
VCC = 4.5 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - V
Figure 1. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VCC
VCC
B or A
A or B
VI = VCC or GND
VIH
VO
C
VC
(On)
GND
IS
r on +
V
VI * VO
W
IS
VI - VO
Figure 3. ON-State Resistance Test Circuit
VCC
VCC
VI
A
VIL
B or A
A or B
VO
C
VC
(Off)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 4. OFF-State Switch Leakage-Current Test Circuit
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Parameter Measurement Information (continued)
VCC
VCC
B or A
A or B
A
VI = VCC or GND
VO
VO = Open
C
VC
VIH
(On)
GND
Figure 5. ON-State Leakage-Current Test Circuit
VCC
VCC
0.1 µF
fin
50 Ω
B or A
A or B
C
VC
VIH
VO
RL
(On)
GND
CL
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch On)
10
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Parameter Measurement Information (continued)
VCC
VCC
0.1 µF
Rin
600 Ω
VO1
CL
50 pF
RL
600 Ω
C
VC
VIH
50 Ω
fin
1B or 1A
1A or 1B
(On)
VCC/2
2B or 2A
2A or 2B
Rin
600 Ω
VO2
CL
50 pF
RL
600 Ω
C
VC
VIL
(Off)
GND
VCC/2
20log10(VO2/VI1) or
20log10(VO1/VI2)
Figure 7. Crosstalk (Between Switches)
VCC
VCC
A or B
VCC/2
B or A
Rin
600 Ω
RL
600 Ω
C
VC
50 Ω
VO
GND
CL
50 pF
VCC/2
Figure 8. Crosstalk (Control Input, Switch Output)
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Parameter Measurement Information (continued)
VCC
VCC
0.1 µF
50 Ω
fin
B or A
A or B
RL
VO
C
VC
VIL
CL
RL
(Off)
GND
VCC/2
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 9. Feedthrough (Switch Off)
VCC
VCC
10 µF
fin
600 Ω
VIH
10 µF
B or A
A or B
VO
RL
10 kΩ
C
VC
(On)
GND
CL
50 pF
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
VCC = 3 V, VI = 2.5 VP-P
VCC = 4.5 V, VI = 4 VP-P
Figure 10. Sine-Wave Distortion
12
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8 Detailed Description
8.1 Overview
This dual bilateral analog switch is designed for 1.65-V to 5.5-V VCC operation. Robust LVC family technology
allows this device to accept input voltages without connecting power to VCC.
The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either
direction. A high-level voltage applied to the control pin C enables the respective switch to begin propagating
signals across the device. A low-level voltage disables this transmission. Each device incorporates two switches
with independent control and operation.
8.2 Functional Block Diagram
1A
1C
1
2
1B
7
One of Two Switches
8.3 Feature Description
Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the
associated switch section. When C is this Signals can pass through A to B or B to A. Low ON-resistance of 6 Ω
at 4.5-V VCC is ideal for analog signal conditioning systems. The control signals can accept voltages up to 5.5 V
without VCC connected in the system. Combination of lower tpd of 0.8 ns at 3.3 V and low enable and disable time
make this part suitable for high-speed signal switching applications.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC2G66.
Table 1. Function Table
CONTROL
INPUT
(C)
SWITCH
L
Off
H
On
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2G66 can be used in any situation where an Dual SPST switch would be used and a solid-state,
voltage controlled version is preferred.
9.2 Typical Application
Vcc= 1.65V to 5.5V
0.1 PF
1C
1B
Microcontroller
Or
System Logic
Microcontroller
Or
System Logic
1A
2A
2B
2C
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Typical Application Schematic
9.2.1 Design Requirements
The SN74LVC2G66 allows on/off control of analog and digital signals with a digital control signal. All input
signals should remain between 0 V and VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed ±50 mA.
3. Frequency Selection Criterion:
– Maximum frequency tested is 150 MHz.
– Added trace resistance or capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout.
14
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Typical Application (continued)
9.2.3 Application Curve
20.0
18.0
16.0
Ron (Ω)
14.0
12.0
–40°C
10.0
25°C
8.0
85°C
6.0
4.0
2.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VIN (V)
Pin: A–B, VCC = 3 V, IS = 24 mA
Figure 12. ron vs VI
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
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11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection.
NOTE
Not all PCB traces can be straight, and so they will have to turn corners. Figure 13 shows
progressively better techniques of rounding corners. Only the last example maintains
constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 13. Trace Example
16
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC2G66DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C66
(R, Z)
SN74LVC2G66DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C66
(R, Z)
SN74LVC2G66DCTRG4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C66
(R, Z)
SN74LVC2G66DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(66, C66Q, C66R)
CZ
SN74LVC2G66DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C66R
SN74LVC2G66DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C66Q, C66R)
SN74LVC2G66DCUTE4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C66R
SN74LVC2G66DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C66R
SN74LVC2G66YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(C67, C6N)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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