SN74LVC2T45YEPR

SN74LVC2T45 SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation 1 Features 3 Description • This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5V, 3.3-V, and 5-V voltage nodes. Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V powersupply range VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state DIR input circuit referenced to VCCA Low power consumption, 4-μA maximum ICC Available in the Texas Instruments NanoFree™ package ±24-mA output drive at 3.3 V Ioff supports Partial-Power-Down mode operation Maximum data rates: – 420 Mbps (3.3-V to 5-V translation) – 210 Mbps (translate to 3.3 V) – 140 Mbps (translate to 2.5 V) – 75 Mbps (translate to 1.8 V) Latch-up performance exceeds 100 mA per JESD 78, Class II ESD protection exceeds JESD 22 – 4000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • • • • • • • • • 2 Applications • • • • Personal electronic Industrial Enterprise Telecom The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. Package Information(1) PART NUMBER DIR 5 SN74LVC2T45 A1 2 (1) 7 A2 PACKAGE BODY SIZE (NOM) DCT (SM8, 8) 2.95 mm × 2.80 mm DCU (VSSOP, 8) 2.30 mm × 2.00 mm YZP (DSBGA, 8) 1.89 mm × 0.89 mm For all available packages, see the orderable addendum at the end of the data sheet. B1 3 6 VCCA B2 VCCB Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics: VCCA = 1.8 V ± 0.15 V.......7 6.7 Switching Characteristics: VCCA = 2.5 V ± 0.2 V.........7 6.8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V.........8 6.9 Switching Characteristics: VCCA = 5 V ± 0.5 V............8 6.10 Operating Characteristics......................................... 9 6.11 Typical Characteristics............................................ 10 7 Parameter Measurement Information.......................... 13 8 Detailed Description......................................................14 8.1 Overview................................................................... 14 8.2 Functional Block Diagram......................................... 14 8.3 Feature Description...................................................14 8.4 Device Functional Modes..........................................15 9 Application and Implementation.................................. 16 9.1 Application Information............................................. 16 9.2 Typical Applications.................................................. 16 10 Power Supply Recommendations..............................20 10.1 Power-Up Considerations....................................... 20 11 Layout........................................................................... 21 11.1 Layout Guidelines................................................... 21 11.2 Layout Example...................................................... 21 12 Device and Documentation Support..........................22 12.1 Documentation Support.......................................... 22 12.2 Receiving Notification of Documentation Updates..22 12.3 Support Resources................................................. 22 12.4 Trademarks............................................................. 22 12.5 Electrostatic Discharge Caution..............................22 12.6 Glossary..................................................................22 13 Mechanical, Packaging, and Orderable Information.................................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (October 2022) to Revision M (October 2022) Page • Changed the TA operating free-air temperature back to 85°C ...........................................................................4 Changes from Revision K (June 2017) to Revision L (October 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated the thermals in the Thermal Information section.................................................................................. 5 • Extended the minimum specifications for lower delays in the Switching Characteristics sections..................... 7 Changes from Revision J (October 2014) to Revision K (June 2017) Page • Changed data sheet title.....................................................................................................................................1 • Added Junction temperature, TJ in Absolute Maximum Ratings ....................................................................... 4 Changes from Revision I (March 2007) to Revision J (October 2014) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 5 Pin Configuration and Functions VCCA A1 A2 GND 1 8 2 7 3 6 4 5 VCCB B1 B2 DIR Figure 5-1. DCT or DCU Package, 8-Pin SM8 or VSSOP (Top View) Table 5-1. Pin Functions: DCT, DCU PIN NAME TYPE(1) NO. DESCRIPTION VCCA 1 P A1 2 I/O Input/output A1. Referenced to VCCA A2 3 I/O Input/output A2. Referenced to VCCA GND 4 G Ground DIR 5 I Direction control signal B2 6 I/O Input/output B2. Referenced to VCCB B1 7 I/O Input/output B1. Referenced to VCCB VCCB 8 P (1) A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V I = input, O = output, P = power, G =ground 1 2 D GND DIR C A2 B2 B A1 B1 A VCCA VCCB Not to scale Figure 5-2. YZP Package, 8-Pin DSGBA (Bottom View) Table 5-2. Pin Functions: YZP PIN NO. NAME A1 VCCA A2 B1 TYPE(1) DESCRIPTION P A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V VCCB P B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V A1 I/O Input/output A1. Referenced to VCCA B2 B1 I/O Input/output B1. Referenced to VCCB C1 A2 I/O Input/output A2. Referenced to VCCA C2 B2 I/O Input/output B2. Referenced to VCCB D1 GND G Ground D2 DIR I Direction control signal (1) I = input, O = output, P = power, G = ground Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 3 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCCA Supply voltage VCCB Input voltage(2) VI state(2) MIN MAX UNIT –0.5 6.5 V –0.5 6.5 V V VO Voltage range applied to any output in the high-impedance or power-off –0.5 6.5 VO Voltage range applied to any output in the high or low A port state(2) (3) B port –0.5 VCCA + 0.5 –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 IOK Output clamp current VO < 0 –50 IO Continuous output current –50 50 mA Continuous current through VCC or GND –100 100 mA 150 °C 150 °C TJ Junction temperature Tstg Storage temperature (1) (2) (3) –65 V mA mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) (2) (3) VCCI VCCA VCCB VIH VCCO Supply voltage High-level input voltage Data inputs(4) MIN MAX 1.65 5.5 1.65 5.5 1.65 V to 1.95 V VCCI × 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V 2 4.5 V to 5.5 V VCCI × 0.7 1.65 V to 1.95 V VIL Low-level input voltage Data inputs(4) 4 High-level input voltage DIR (referenced to VCCA)(5) VCCI × 0.35 0.7 3 V to 3.6 V 0.8 V VCCI × 0.3 1.65 V to 1.95 V VCCA × 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V 2 4.5 V to 5.5 V VCCA × 0.7 Submit Document Feedback V V 2.3 V to 2.7 V 4.5 V to 5.5 V VIH UNIT V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.3 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted)(1) (2) (3) VCCI VIL Low-level input voltage VI Input voltage VO Output voltage DIR (referenced to VCCA)(5) VCCO MIN VCCA × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V to 5.5 V High-level output current IOL Low-level output current Δt/Δv Data inputs Input transition rise or fall rate Control input TA (1) (2) (3) (4) (5) UNIT V VCCA × 0.3 0 5.5 V 0 VCCO V 1.65 V to 1.95 V IOH MAX 1.65 V to 1.95 V –4 2.3 V to 2.7 V –8 3 V to 3.6 V –24 4.5 V to 5.5 V –32 1.65 V to 1.95 V 4 2.3 V to 2.7 V 8 3 V to 3.6 V 24 4.5 V to 5.5 V 32 1.65 V to 1.95 V 20 2.3 V to 2.7 V 20 3 V to 3.6 V 10 4.5 V to 5.5 V 5 1.65 V to 5.5 V 5 Operating free-air temperature –40 mA mA ns/V 85 °C VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs, SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. 6.4 Thermal Information SN74LVC2T45 THERMAL METRIC(1) DCU DCT YZP UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 246.4 195.3 105.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 95.4 106 1.6 °C/W RθJB Junction-to-board thermal resistance 157.8 110.8 10.8 °C/W ψJT Junction-to-top characterization parameter 37 38.3 3.1 °C/W ψJB Junction-to-board characterization parameter 156.9 109.3 10.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 5 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS IOH = –100 μA IOH = –8 mA 1.65 V to 4.5 V 1.65 V to 4.5 V 1.65 V 1.65 V 1.2 2.3 V 2.3 V 1.9 VI = VIH DIR A port Ioff B port A or B port IOZ ICCA 6 MAX V 3V 2.4 3.8 IOL = 100 μA 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 1.65 V 1.65 V 0.45 VI = VIL 2.3 V 2.3 V 0.3 IOL = 24 mA 3V 3V 0.55 IOL = 32 mA 4.5 V 4.5 V 0.55 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 0V 0 to 5.5 V ±1 ±2 0 to 5.5 V 0V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V 3 5V 0V 2 0V 5V –2 1.65 V to 5.5 V 1.65 V to 5.5 V 3 5V 0V –2 0V 5V 2 1.65 V to 5.5 V 1.65 V to 5.5 V 4 VI = VCCA or GND VI or VO = 0 to 5.5 V VO = VCCO or GND A port One A port at VCCA – 0.6 V, DIR at VCCA, B port = open DIR DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND ΔICCB B port One B port at VCCB – 0.6 V, DIR at GND, A port = open CI DIR Cio A or B port UNIT VCCO – 0.1 4.5 V ICCA + ICCB V = VCCI or GND, IO = 0 (see Table 10-1) I (1) (2) MIN 3V VI = VCCI or GND, IO = 0 ΔICCA MAX 4.5 V VI = VCCI or GND, IO = 0 ICCB TYP IOH = –32 mA IOL = 8 mA II MIN IOH = –24 mA IOL = 4 mA VOL –40°C to +85°C VCCB IOH = –4 mA VOH TA = 25°C VCCA V µA µA µA µA µA µA 50 3 V to 5.5 V 3 V to 5.5 V µA 50 3 V to 5.5 V 3 V to 5.5 V 50 µA VI = VCCA or GND 3.3 V 3.3 V 2.5 pF VO = VCCA/B or GND 3.3 V 3.3 V 6 pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.6 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3 17.7 2.2 10.3 1.7 8.3 1.4 7.2 2.8 14.3 2.2 8.5 1.8 7.1 1.7 7 3 17.7 2.3 16 2.1 15.5 1.9 15.1 2.8 14.3 2.1 12.9 2 12.6 1.8 12.2 5.5 30.9 5.5 30.5 5.5 30.5 5.5 29.3 4.3 19.7 4.2 19.6 4.1 19.5 4 19.4 6 27.9 5 14.9 5 11.3 4.1 8.6 5 19.5 3.9 12.6 4.3 9.7 2.1 7.1 37.2 28.6 25.2 22.2 42.2 27.8 23.9 20.8 37.4 29.9 27.8 26.6 45.2 39 37.6 36.3 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. 6.7 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V MIN VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MAX MIN MAX MIN MAX MIN MAX 2.3 16 1.5 8.5 1.3 6.4 1.1 5.1 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 2.2 10.3 1.5 8.5 1.4 8 1 7.5 2.2 8.5 1.4 7.5 1.3 7 0.9 6.2 4.2 17.1 4.2 16.8 4.1 16.8 4.1 16.5 3.2 12.6 3.2 12.5 3.2 12.3 3 12.3 6 27.9 4.7 13.9 4.7 10.5 3.5 7.6 4.2 18.9 3.6 11.2 3.6 8.9 1.4 6.2 29.2 19.7 16.9 13.7 36.4 21.4 17.5 13.8 28.6 21 18.7 17.4 30 24.3 22.2 21.1 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 7 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.1 15.5 1.4 8 0.7 5.6 0.7 4.4 2 12.6 1.3 7 0.8 5 0.7 4 1.7 8.3 1.3 6.4 0.7 5.8 0.6 5.4 1.8 7.1 1.3 5.4 0.8 5 0.7 4.5 4.5 10.9 4.5 10.8 4.4 10.8 4.4 10.4 3.4 8.4 3.7 8.4 3.9 8.1 3.3 7.8 5.7 27.3 4.7 13.7 4.7 10.4 2.9 7.4 4.5 17.7 3.5 11.3 4.3 8.3 1 5.6 26 17.7 14.1 11 34.4 19.1 15.4 11.9 23.9 16.4 13.9 12.2 23.5 17.8 15.8 14.4 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. 6.9 Switching Characteristics: VCCA = 5 V ± 0.5 V over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) 8 (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.9 15.1 1 7.5 0.6 5.4 0.5 3.9 1.8 12.2 0.9 6.2 0.7 4.5 0.5 3.5 1.4 7.2 1 5.1 0.7 4.4 0.5 3.9 1.7 7 0.9 4.6 0.7 4 0.5 3.5 2.9 8.2 2.9 7.9 2.8 7.9 2.2 7.8 1.4 6.9 1.3 6.7 0.7 6.7 0.7 6.6 5.8 26.1 4.4 13.9 4.4 10.1 1.3 7.3 4.7 16.9 3.3 11 4 7.7 1 5.6 24.1 16.1 12.1 9.5 33.1 18.5 14.1 10.8 22 14.2 12.1 10.5 20.4 14.1 12.4 11.3 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.10 Operating Characteristics TA = 25°C PARAMETER CpdA (1) CpdB (1) (1) A-port input, B-port output B-port input, A-port output A-port input, B-port output B-port input, A-port output TEST CONDITIONS CL = 0 pF, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V VCCA = VCCB = 5 V TYP TYP TYP TYP 3 4 4 4 18 19 20 21 18 19 20 21 3 4 4 4 UNIT pF CL = 0 pF, f = 10 MHz, tr = tf = 1 ns pF Power dissipation capacitance per transceiver. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 9 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.11 Typical Characteristics 10 10 9 9 8 8 VCCB = 1.8 V VCCB = 1.8 V 7 6 VCCB = 2.5 V 5 6 t PLH− ns t PHL − ns 7 VCCB = 2.5 V 5 VCCB = 3.3 V 4 4 VCCB = 5 V 3 VCCB = 3.3 V 3 VCCB = 5 V 2 2 1 1 0 0 0 5 10 15 20 25 30 0 35 5 10 15 20 25 30 35 CL − pF CL − pF Figure 6-1. Typical Propagation Delay of High-to-Low (A to B) vs Figure 6-2. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.8 V Load Capacitance TA = 25°C, VCCA = 1.8 V 10 10 9 9 8 8 VCCB = 1.8 V VCCB = 2.5 V 7 6 6 5 VCCB = 2.5 V VCCB = 3.3 V 4 VCCB = 5 V t PLH − ns t PHL − ns VCCB = 1.8 V 7 VCCB = 3.3 V VCCB = 5 V 5 4 3 3 2 2 1 1 0 0 0 5 10 15 20 25 30 35 0 5 10 CL − pF 15 20 CL − pF 25 30 35 Figure 6-3. Typical Propagation Delay of High-to-Low (B to A) vs Figure 6-4. Typical Propagation Delay of Low-to-High (B to A) vs Load Capacitance TA = 25°C, VCCA = 1.8 V Load Capacitance TA = 25°C, VCCA = 1.8 V 10 10 9 9 7 7 VCCB = 1.8 V 6 t PLH − ns t PHL − ns VCCB = 1.8 V 8 8 5 6 5 VCCB = 2.5 V 4 4 VCCB = 3.3 V 3 3 VCCB = 5 V VCCB = 2.5 V VCCB = 3.3 V 2 2 VCCB = 5 V 1 1 0 0 0 5 10 15 20 25 30 35 0 CL − pF 5 10 15 20 25 30 35 CL − pF Figure 6-5. Typical Propagation Delay of High-to-Low (A to B) vs Figure 6-6. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 2.5 V Load Capacitance TA = 25°C, VCCA = 2.5 V 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.11 Typical Characteristics (continued) 10 9 9 8 8 7 7 t PHL − ns 10 t PLH − ns 6 VCCB = 1.8 V 5 4 6 VCCB = 1.8 V 5 4 3 VCCB = 3.3 V VCCB = 5 V 2 VCCB = 2.5 V VCCB = 3.3 V 3 VCCB = 2.5 V VCCB = 5 V 2 1 1 0 0 5 10 15 20 CL − pF 25 30 0 35 0 5 10 15 20 25 30 35 CL − pF Figure 6-7. Typical Propagation Delay of High-to-Low (B to A) vs Figure 6-8. Typical Propagation Delay of Low-to-High (B to A) vs Load Capacitance TA = 25°C, VCCA = 2.5 V Load Capacitance TA = 25°C, VCCA = 2.5 V 10 10 9 9 8 8 7 7 VCCB = 1.8 V 6 6 t PLH − ns t PHL − ns VCCB = 1.8 V 5 VCCB = 2.5 V 4 3 VCCB = 2.5 V 5 4 VCCB = 3.3 V 3 VCCB = 5 V 2 2 VCCB = 3.3 V 1 1 VCCB = 5 V 0 0 0 5 10 15 20 25 30 35 0 5 10 Figure 6-9. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 3.3 V 20 25 30 35 Figure 6-10. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 3.3 V 10 10 9 9 8 8 7 7 6 6 t PLH − ns t PHL − ns 15 CL − pF CL − pF 5 VCCB = 1.8 V 4 3 VCCB = 1.8 V 5 4 3 2 VCCB = 2.5 V 1 VCCB = 2.5 V 2 VCCB = 3.3 V VCCB = 3.3 V 1 VCCB = 5 V 0 VCCB = 5 V 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 CL − pF CL − pF Figure 6-11. Typical Propagation Delay of High-to-Low (B to A) vs Load Capacitance TA = 25°C, VCCA = 3.3 V Figure 6-12. Typical Propagation Delay of Low-to-High (B to A) vs Load Capacitance TA = 25°C, VCCA = 3.3 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 11 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 6.11 Typical Characteristics (continued) 10 10 9 9 8 8 7 7 VCCB = 1.8 V VCCB = 1.8 V t PLH − ns t PHL − ns 6 5 4 6 5 VCCB = 2.5 V 4 VCCB = 2.5 V VCCB = 3.3 V 3 3 VCCB = 5 V 2 2 VCCB = 3.3 V 1 0 1 VCCB = 5 V 0 0 5 10 15 20 25 30 35 0 5 10 CL − pF 9 8 8 7 7 6 6 t PLH − ns 9 t PHL− ns 10 5 3 VCCB = 2.5 V 30 35 5 VCCB = 1.8 V 4 VCCB = 2.5 V 3 2 2 VCCB = 3.3 V VCCB = 3.3 V VCCB = 5 V 1 VCCB = 5 V 1 0 0 0 5 10 15 20 25 30 35 0 CL − pF 5 10 15 20 25 30 35 CL − pF Figure 6-15. Typical Propagation Delay of High-to-Low (B to A) vs Load Capacitance TA = 25°C, VCCA = 5 V 12 25 Figure 6-14. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 5 V 10 4 20 CL − pF Figure 6-13. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 5 V VCCB = 1.8 V 15 Figure 6-16. Typical Propagation Delay of Low-to-High (B to A) vs Load Capacitance TA = 25°C, VCCA = 5 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 7 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 13 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 8 Detailed Description 8.1 Overview The SN74LVC2T45 is a dual-bit, dual-supply noninverting voltage level translation device. VCCA supports pin Ax and the direction control pin, and VCCB supports pin Bx. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A. 8.2 Functional Block Diagram DIR A1 5 2 7 A2 B1 3 6 VCCA B2 VCCB Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V, and 5-V). 8.3.2 Support High-Speed Translation SN74LVC2T45 can support high data rate applications. The translated signal data rate can be up to 420 Mbps when signal is translated from 3.3 V to 5 V. 8.3.3 Ioff Supports Partial-Power-Down Mode Operation Ioff will prevent backflow current by disabling I/O output circuits when the device is in Partial-Power-Down mode. The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting current backflow into the device. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics. 8.3.4 Balanced High-Drive CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so impedance matching and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. Two outputs can be connected together for a stronger output drive strength. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 8.3.5 Vcc Isolation The I/O's of both ports will enter a high-impedance state when either of the supplies are at GND, while the other supply is still connected to the device. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics. 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SN74LVC2T45 device. Table 8-1. Function Table (Each Transceiver)(1) (1) INPUT DIR OPERATION L B data to A bus H A data to B bus Input circuits of the data I/Os always are active. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 15 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC2T45 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum data rate can be up to 420 Mbps when the device translates signal from 3.3 V to 5 V. It is recommended to tie all unused I/Os to GND. The device should not have any floating I/Os when changing translation direction. 9.2 Typical Applications 9.2.1 Unidirectional Logic Level-Shifting Application Figure 9-1 shows an example of the SN74LVC2T45 being used in a unidirectional logic level-shifting application. VCC2 VCC1 VCC1 VCC2 1 8 2 7 3 6 4 5 VCC2 VCC1 SYSTEM-1 SYSTEM-2 Figure 9-1. Unidirectional Logic Level-Shifting Application 9.2.1.1 Design Requirements Table 9-1 lists the pins and pin descriptions of the SN74LVC2T45 connections with SYSTEM-1 and SYSTEM-2. Table 9-1. SN74LVC2T45 Pin Connections With SYSTEM-1 and SYSTEM-2 PIN NAME FUNCTION 1 VCCA VCC1 SYSTEM-1 supply voltage (1.65 V to 5.5 V) DESCRIPTION 2 A1 OUT1 Output level depends on VCC1 voltage. 3 A2 OUT2 Output level depends on VCC1 voltage. 4 GND GND Device GND 5 DIR DIR GND (low level) determines B-port to A-port direction. 6 B2 IN2 Input threshold value depends on VCC2 voltage. 7 B1 IN1 Input threshold value depends on VCC2 voltage. 8 VCCB VCC2 SYSTEM-2 supply voltage (1.65 V to 5.5 V) For this design example, use the parameters listed in Table 9-2. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 Table 9-2. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.65 V to 5.5 V Output voltage range 1.65 V to 5.5 V 9.2.1.2 Detailed Design Procedure To begin the design process, determine the following: • • Input voltage range – Use the supply voltage of the device that is driving the SN74LVC2T45 device to determine the input voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the value must be less than the VIL of the input port. Output voltage range – Use the supply voltage of the device that the SN74LVC2T45 device is driving to determine the output voltage range.   9.2.1.3 Application Curve Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 17 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 9.2.2 Bidirectional Logic Level-Shifting Application Figure 9-2 shows the SN74LVC2T45 being used in a bidirectional logic level-shifting application. Because the SN74LVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 VCC1 VCC2 Pullup/Down or Bus Hold(1) Pullup/Down or Bus Hold(1) I/O-1 VCC2 1 8 2 7 3 6 4 5 I/O-2 DIR CTRL SYSTEM-1 SYSTEM-2 Figure 9-2. Bidirectional Logic Level-Shifting Application 9.2.2.1 Design Requirements Refer to Section 9.2.1. 9.2.2.2 Detailed Design Procedure Table 9-3 provides data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. Table 9-3. Data Transmission Sequence STATE DIR CTRL I/O-1 I/O-2 1 H Out In 2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown.(1) 3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown.(1) 4 L In Out SYSTEM-2 data to SYSTEM-1 (1) DESCRIPTION SYSTEM-1 data to SYSTEM-2 SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown. 9.2.2.2.1 Enable Times Calculate the enable times for the SN74LVC2T45 using the following formulas: • • • • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC2T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 www.ti.com SN74LVC2T45 SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 9.2.2.3 Application Curve Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC2T45 19 SN74LVC2T45 www.ti.com SCES516M – DECEMBER 2003 – REVISED OCTOBER 2022 10 Power Supply Recommendations 10.1 Power-Up Considerations A proper power-up sequence with inputs held at ground should be followed as listed: 1. Connect ground before any supply voltage is applied. 2. Power up VCCA. 3. VCCB can be ramped up along with or after VCCA. The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. The recommendation is to first power-up the input supply rail to help avoid internal floating while the output supply rail ramps up. However, both power-supply rails can be ramped up simultaneously. Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 µF is recommended. If there are multiple VCC pins, 0.01 µF or 0.022 µF is recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results. Table 10-1. Typical Total Static Power Consumption (ICCA + ICCB) VCCB 20 VCCA 0V 1.8 V 2.5 V 3.3 V 5V 0V 0