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SN54LVC32A, SN74LVC32A
SCAS286R – JANUARY 1993 – REVISED OCTOBER 2016
SNx4LVC32A Quadruple 2-Input Positive-OR Gates
1 Features
3 Description
•
•
The SN54LVC32A quadruple 2-input positive-OR
gate is designed for 2.7-V to 3.6-V VCC operation, and
the SN74LVC32A quadruple 2-input positive-OR gate
is designed for 1.65-V to 3.6-V VCC operation.
1
•
•
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Specified From –40°C to +85°C,
–40°C to +125°C, and –55°C to +125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 3.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA
Per JESD 17
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
The SNx4LVC32A devices perform the Boolean
function Y + A ) B or Y + A • B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices.
This feature allows the use of these devices as
translators in a mixed 3.3-V/5-V system environment.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC32AD
SOIC (14)
8.65 mm × 3.91 mm
SN74LVC32ADB
SSOP (14)
6.20 mm × 5.30 mm
SN74LVC32ANS
SO (14)
10.30 mm × 5.30 mm
SN74LVC32APW
TSSOP (14)
5.00 mm × 4.40 mm
SN74LVC32ARGY
VQFN (14)
3.50 mm × 3.50 mm
SN54LVC32AJ
CDIP (14)
19.56 mm × 6.67 mm
SN54LVC32AW
CFP (14)
9.21 mm × 5.97 mm
SN54LVC32AFK
LCCC (20)
8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AV Receivers
Audio Docks: Portable
Blu-ray Players and Home Theater
MP3 Players or Recorders
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drives (SSDs): Client and Enterprise
TVs: LCD, Digital, and High-Definition (HDTV)
Tablets: Enterprise
Video Analytics: Server
Wireless Headsets, Keyboards, and Mice
Simplified Schematic
A
Y
B
A
Y
B
A
Y
B
A
Y
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC32A, SN74LVC32A
SCAS286R – JANUARY 1993 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions, SN54LVC32A
................................................................................... 5
6.4 Recommended Operating Conditions, SN74LVC32A
................................................................................... 5
6.5 Thermal Information .................................................. 6
6.6 Electrical Characteristics, SN54LVC32A .................. 6
6.7 Electrical Characteristics, SN74LVC32A .................. 6
6.8 Switching Characteristics, SN54LVC32A ................. 7
6.9 Switching Characteristics, SN74LVC32A ................. 7
6.10 Operating Characteristics........................................ 7
6.11 Typical Characteristics ............................................ 7
7
8
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Q (December 2014) to Revision R
Page
•
Added CDIP (14), CFP (14), and LCCC (20) packages to Device Information table............................................................. 1
•
Added Junction temperature, TJ in Absolute Maximum Ratings ........................................................................................... 4
•
Deleted open-drain from Application Information ................................................................................................................. 10
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 12
Changes from Revision P (April 2005) to Revision Q
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Military Disclaimer to Features.................................................................................................................................... 1
2
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SCAS286R – JANUARY 1993 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
SN54LVC32A J or W Package
SN74LVC32A D, DB, NS, or PW Package
14-Pin CDIP, CFP, SOIC, SSOP, SO, TSSOP
Top View
2Y
10
6
GND
3B
9
7
3A
8
3Y
NC
VCC
4B
1
19
4
18
4A
5
17
NC
2A
6
16
4Y
NC
7
15
NC
2B
8
14
3B
9
Not to scale
1A
VCC
1
14
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
2Y
SN74LVC32A RGY Package
14-Pin VQFN With Thermal Pad
Top View
13
5
1Y
NC
3A
2B
20
4Y
12
11
11
4
3Y
4A
2A
NC
12
1A
3
1B
4B
1Y
2
VCC
13
3
14
2
10
1
1B
GND
1A
SN54LVC32A FK Package
20-Pin LCCC
Top View
Not to scale
NC – No internal connection
Thermal
8
Not to scale
3Y
GND
7
Pad
Pin Functions
PIN
NAME
SN74LVC32A
SN54LVC32A
TYPE
DESCRIPTION
D, DB, NS, PW
RGY
J, W
FK
1A
1
1
1
2
I
Gate 1 input
1B
2
2
2
3
I
Gate 1 input
1Y
3
3
3
4
O
Gate 1 output
2A
4
4
4
6
I
Gate 2 input
2B
5
5
5
8
I
Gate 2 input
2Y
6
6
6
9
O
Gate 2 output
GND
7
7
7
10
—
Ground Pin
3Y
8
8
8
12
O
Gate 3 output
3A
9
9
9
13
I
Gate 3 input
3B
10
10
10
14
I
Gate 3 input
4Y
11
11
11
16
O
Gate 4 output
4A
12
12
12
18
I
Gate 4 input
4B
13
13
13
19
I
Gate 4 input
VCC
14
14
14
20
—
Power Pin
NC
—
—
—
1, 5, 7, 11, 15, 17
—
No Connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage
–0.5
6.5
UNIT
V
(2)
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Output voltage (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
500
mW
150
°C
150
°C
Continuous current through VCC or GND
Ptot
Power dissipation
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
TA = –40°C to +125°C
(4) (5)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions tables.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, DGV, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCAS286R – JANUARY 1993 – REVISED OCTOBER 2016
6.3 Recommended Operating Conditions, SN54LVC32A
over operating free-air temperature range (unless otherwise noted) (1)
SN54LVC32A
–55 to +125°C
Operating
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
Data retention only
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise and fall rate
(1)
UNIT
MIN
MAX
2
3.6
V
1.5
2
V
0.8
V
0
5.5
V
0
VCC
V
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 2.7 V
12
VCC = 3 V
24
mA
mA
7
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Recommended Operating Conditions, SN74LVC32A
over operating free-air temperature range (unless otherwise noted) (1)
SN74LVC32A
TA = 25°C
VCC
Supply voltage
VIH
High-level input
voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
Low-level input
voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output
current
Low-level output
current
MAX
MIN
MAX
MIN
MAX
3.6
1.65
3.6
1.65
3.6
1.5
1.5
0.65 × VCC
1.5
0.65 × VCC
V
0.65 × VCC
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
V
0.35 × VCC
0.35 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
V
0
5.5
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
VCC = 1.65 V
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
4
4
4
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
7
7
7
Δt/Δv Input transition rise and fall rate
(1)
UNIT
MIN
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
IOL
–40 to +125°C
1.65
VCC = 1.65 V to 1.95 V
VIL
–40 to +85°C
mA
mA
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.5 Thermal Information
SNx4LVC32A
THERMAL METRIC (1)
RθJA
(1)
D
DB
NS
PW
RGY
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
86
96
76
113
47
Junction-to-ambient thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics, SN54LVC32A
over operating free-air temperature range (unless otherwise noted)
SN54LVC32A
PARAMETER
TEST CONDITIONS
VCC
–55 to +125°C
MIN
IOH = –100 µA
VOH
2.7 V to 3.6 V
VCC – 0.2
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
2.7 V to 3.6 V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
IOH = –12 mA
VOL
UNIT
MAX
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
V
0.2
V
3.6 V
±5
µA
3.6 V
10
µA
2.7 V to 3.6 V
500
µA
6.7 Electrical Characteristics, SN74LVC32A
over operating free-air temperature range (unless otherwise noted)
SN74LVC32A
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
1.65 V to
3.6 V
IOH = –100 µA
VOH
VCC – 0.2
–40 to +125°C
MIN
UNIT
MAX
VCC – 0.3
1.65 V
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
V
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
2.2
2
IOL = 100 µA
1.65 V to
3.6 V
0.1
0.2
0.3
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.85
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
3.6 V
±1
±5
±20
µA
3.6 V
1
10
40
µA
500
500
5000
µA
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
6
VCC – 0.2
MIN MAX
IOH = –4 mA
IOH = –12 mA
VOL
–40 to +85°C
TYP MAX
IO = 0
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2.7 V to
3.6 V
3.3 V
5
V
pF
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6.8 Switching Characteristics, SN54LVC32A
over operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN54LVC32A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
–55 to +125°C
MIN
tpd
A or B
2.7 V
Y
UNIT
MAX
4.4
3.3 V ± 0.3 V
1
ns
3.8
6.9 Switching Characteristics, SN74LVC32A
over operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN74LVC32A
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
tsk(o)
VCC
TA = 25°C
–40 to +85°C
–40 to +125°C
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1.8 V ± 0.15 V
1
4.2
8.2
1
8.7
1
10.2
2.5 V ± 0.2 V
1
2.6
4.9
1
5.4
1
6.9
2.7 V
1
3
4.2
1
4.4
1
5.5
3.3 V ± 0.3 V
1
2.5
3.6
1
3.8
1
5
3.3 V ± 0.3 V
1
1.5
UNIT
ns
ns
6.10 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance per gate
f = 10 MHz
VCC
TYP
1.8 V
7.5
2.5 V
10.6
3.3 V
12.5
UNIT
pF
6.11 Typical Characteristics
8
7
TPD (ns)
6
5
4
3
2
1
TPD
0
1.5
2.0
2.5
3.0
3.5
VCC Input (V)
4.0
C001
Figure 1. TPD vs VCC (TA = 25°C)
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr /t f
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VΔ
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VΔ
VOL
tPHZ
VM
VOH – VΔ
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t PLZ and t PHZ are the same as t dis .
F. t PZL and t PZH are the same as t en .
G. t PLH and t PHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2-V to 3.6-V VCC operation, and the
SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation.
The SNx4LVC32A devices perform the Boolean function Y + A ) B or Y + A • B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as downtranslators in a mixed 3.3-V/5-V system environment.
8.2 Functional Block Diagram
Logic Diagram, Each Gate (Positive Logic)
A
Y
B
8.3 Feature Description
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows up or down voltage translation
– Inputs accept voltages to 5.5 V
8.4 Device Functional Modes
Table 1 lists the functional modes of SNx4LVC32A.
Table 1. Function Table
(Each Gate)
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
SN74LVC32A device is a high-drive, CMOS device that can be used for a multitude of buffer-type functions. It
can produce 24 mA of drive current at 3 V. Therefore, this device is ideal for driving multiple inputs and for highspeed applications up to 100 MHz. The inputs and outputs are 5.5-V tolerant allowing the device to translate
down to VCC.
9.2 Typical Application
1.65-V to 3.6-V VCC
1A
1B
System Inputs / MCU
4A
4B
1Y
System Outputs / MCU
4Y
Figure 3. Typical OR Gate Application and Supply Voltage
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions, SN74LVC32A
table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions,
SN74LVC32A table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above 5.5 V.
10
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Copyright © 1993–2016, Texas Instruments Incorporated
Product Folder Links: SN54LVC32A SN74LVC32A
SN54LVC32A, SN74LVC32A
www.ti.com
SCAS286R – JANUARY 1993 – REVISED OCTOBER 2016
Typical Application (continued)
9.2.3 Application Curve
Figure 4. Supply Current vs Input Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions, SN74LVC32A table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Layout Example specifies the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver.
11.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 5. Layout Diagram
Copyright © 1993–2016, Texas Instruments Incorporated
Product Folder Links: SN54LVC32A SN74LVC32A
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11
SN54LVC32A, SN74LVC32A
SCAS286R – JANUARY 1993 – REVISED OCTOBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC32A
Click here
Click here
Click here
Click here
Click here
SN74LVC32A
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 1993–2016, Texas Instruments Incorporated
Product Folder Links: SN54LVC32A SN74LVC32A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9761801Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629761801Q2A
SNJ54LVC
32AFK
5962-9761801QCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761801QC
A
SNJ54LVC32AJ
5962-9761801QDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761801QD
A
SNJ54LVC32AW
SN74LVC32AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC32A
Samples
SN74LVC32ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32ADBRG4
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC32A
Samples
SN74LVC32ADRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC32A
Samples
SN74LVC32ADT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC32A
Samples
SN74LVC32ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC32A
Samples
SN74LVC32APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32APWE4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32APWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32APWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32APWRG3
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC32APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC32A
Samples
SN74LVC32ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC32A
Samples
SNJ54LVC32AFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629761801Q2A
SNJ54LVC
32AFK
SNJ54LVC32AJ
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761801QC
A
SNJ54LVC32AJ
SNJ54LVC32AW
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9761801QD
A
SNJ54LVC32AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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