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SN54LVC374A, SN74LVC374A
SCAS296O – JANUARY 1993 – REVISED JULY 2014
SNx4LVC374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.5 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage
With 3.3-V VCC)
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Electronic Points of Sale
TV Set-top Boxes
Infotainment
Servers
Appliances
3 Description
The SN54LVC374A octal edge-triggered D-type flipflop is designed for 2.7-V to 3.6-V VCC operation, and
the SN74LVC374A octal edge-triggered D-type flipflop is designed for 1.65-V to 3.6-V VCC operation.
Device Information(1)
PART NUMBER
SNx4LVC374A
PACKAGE
BODY SIZE (NOM)
PDIP (20)
25.40 mm x 6.35 mm
VQFN (20)
4.50 mm x 3.50 mm
SOIC (20)
12.80 mm x 7.50 mm
SSOP (20)
7.20 mm x 5.30 mm
TVSOP (20)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
OE
CLK
1
11
C1
1D
3
1D
2
1Q
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC374A, SN74LVC374A
SCAS296O – JANUARY 1993 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
1
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements, SN54LVC374A ..................... 7
Timing Requirements, SN74LVC374A .................... 7
Timing Requirements, SN74LVC374A ..................... 7
Switching Characteristics, SN54LVC374A ............... 7
Switching Characteristics, SN74LVC374A ............. 8
Switching Characteristics, SN74LVC374A ............. 8
Operating Characteristics........................................ 8
Typical Characteristics ............................................ 9
8
9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
10 Applications and Implementation...................... 12
10.1 Application Information.......................................... 12
10.2 Typical Application ................................................ 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision N (May 2005) to Revision O
Page
•
Updated data sheet temperature range.................................................................................................................................. 1
•
Updated Ioff bullet in Features list. .......................................................................................................................................... 1
•
Added Applications. ............................................................................................................................................................... 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature range from 85°C to 125°C in Recommended Operating Conditions table................ 5
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added –40°C TO 125°C for SN74LVC374A to Electrical Characteristics table. ................................................................... 6
•
Added Timing Requirements table for SN74LVC374A at –40°C TO 125°C. ......................................................................... 7
•
Added Switching Characteristics table for SN74LVC374A –40°C TO 125°C. ....................................................................... 8
•
Added Typical Characteristics. ............................................................................................................................................... 9
•
Added Detailed Description section...................................................................................................................................... 11
•
Added Applications and Implementation section.................................................................................................................. 12
•
Added Power Supply Recommendations and Layout sections............................................................................................ 13
2
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Product Folder Links: SN54LVC374A SN74LVC374A
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SCAS296O – JANUARY 1993 – REVISED JULY 2014
6 Pin Configuration and Functions
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
20
1Q
1D
2D
2Q
3Q
3D
4D
4Q
3
4
19 8Q
18 8D
17 7D
5
6
16 7Q
15 6Q
7
8
14 6D
13 5D
12 5Q
9
10
11
2D
2Q
3Q
3D
4D
8Q
1
2
SN54LVC374A . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
VCC
VCC
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
CLK
20
OE
1
GND
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
SN74LVC374A . . . RGY PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
6
17
16
7
8
15
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
SN54LVC374A . . . J OR W PACKAGE
SN74LVC374A . . . DB, DGV, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
OE
I
Enable pin
2
1Q
O
Output 1
3
1D
I
Input 1
4
2D
I
Input 2
5
2Q
O
Output 2
6
3Q
O
Output 3
7
3D
I
Input 3
8
4D
I
Input 4
9
4Q
O
Output 4
10
GND
—
Ground pin
11
CLK
I
Clock
12
5Q
O
Output 5
13
5D
I
Input 5
14
6D
I
Input 6
15
6Q
O
Output 6
16
7Q
O
Output 7
17
7D
I
Input 7
18
8D
I
Input 8
19
8Q
O
Output 8
20
VCC
—
Power pin
Copyright © 1993–2014, Texas Instruments Incorporated
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SCAS296O – JANUARY 1993 – REVISED JULY 2014
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
(2)
MIN
MAX
–0.5
6.5
UNIT
V
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage range
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2
kV
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
V
Storage temperature range
Electrostatic discharge
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V
may actually have higher performance.
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SCAS296O – JANUARY 1993 – REVISED JULY 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LVC374A
VCC
Operating
Supply voltage
Data retention only
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
High-level input voltage
1.7
2
Low-level input voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
V
2
VCC = 1.65 V to 1.95 V
VIL
High-level output current
0.8
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
mA
4
VCC = 2.3 V
Low-level output current
V
0.8
VCC = 1.65 V
IOL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
SN74LVC374A
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
10
–55
125
–40
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, (SCBA004).
7.4 Thermal Information
SN74LVC374A
THERMAL METRIC
(1)
PW
UNIT
20 PIN
RθJA
Junction-to-ambient thermal resistance
102.5
RθJCtop
Junction-to-case (top) thermal resistance
35.9
RθJB
Junction-to-board thermal resistance
53.5
ψJT
Junction-to-top characterization parameter
2.2
ψJB
Junction-to-board characterization parameter
52.9
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, (SPRA953).
Copyright © 1993–2014, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN74LVC374A
SN74LVC374A
–40°C TO 85°C
–40°C TO 125°C
SN54LVC374A
PARAMETER
TEST CONDITIONS
VCC
MIN
2.7 V to
3.6 V
(1)
(2)
6
MAX
MIN
VCC – 0.2
VCC – 0.2
TYP (1)
UNIT
MAX
VCC – 0.2
1.2
1.20
IOH = –8 mA
2.3 V
1.7
1.70
2.7 V
2.2
2.2
2.20
3V
2.4
2.4
2.40
3V
2.2
2.2
2.20
1.65 V to
3.6 V
IOL = 100 μA
2.7 V to
3.6 V
V
0.2
0.20
0.2
V
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.7
0.70
IOL = 12 mA
2.7 V
0.4
0.4
0.40
IOL = 24 mA
3V
0.55
0.55
0.55
±5
±5
±5
μA
±10
±20
μA
±15
±10
±15
μA
10
10
10
10
10
10
500
500
500
II
VI = 0 to 5.5 V
Ioff
VI or VO = 5.5 V
0
IOZ
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
ΔICC
TYP (1)
1.65 V
IOH = –24 mA
ICC
MIN
IOH = –4 mA
IOH = –12 mA
VOL
MAX
1.65 V to
3.6 V
IOH = –100 μA
VOH
TYP (1)
3.6 V
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3.6 V
2.7 V to
3.6 V
Ci
VI = VCC or GND
3.3 V
4
12
4
Co
VO = VCC or GND
3.3 V
5.5
12
5.5
75
μA
μA
4
pF
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
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7.6 Timing Requirements, SN54LVC374A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC374A
PARAMETER
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
UNIT
MAX
80
100
MHz
3.3
3.3
ns
2
2
ns
1.5
1.5
ns
7.7 Timing Requirements, SN74LVC374A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC374A
–40°C TO 85°C
PARAMETER
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
55
MIN
95
UNIT
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
MAX
fclock
Clock frequency
80
100
MHz
tw
Pulse duration, CLK high or low
9
4
3.3
3.3
ns
tsu
Setup time, data before CLK↑
6
4
2
2
ns
th
Hold time, data after CLK↑
4
2
1.5
1.5
ns
7.8 Timing Requirements, SN74LVC374A
SN74LVC374A
–40°C TO 85°C
PARAMETER
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
40
MIN
80
UNIT
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
MAX
fclock
Clock frequency
tw
Pulse duration, CLK high or low
9
4
3.3
80
3.3
100
MHz
ns
tsu
Setup time, data before CLK↑
6
4
2
2
ns
th
Hold time, data after CLK↑
4
2
1.5
1.5
ns
7.9 Switching Characteristics, SN54LVC374A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC374A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
fmax
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
80
MIN
UNIT
MAX
100
MHz
tpd
CLK
Q
9.5
1
8.5
ns
ten
OE
Q
9.5
1
8.5
ns
tdis
OE
Q
8
1
7
ns
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7.10 Switching Characteristics, SN74LVC374A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC374A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–40°C TO 85°C
VCC = 1.8 V
± 0.15 V
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
MIN
55
MAX
MIN
95
UNIT
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
80
MIN
MAX
100
MHz
tpd
CLK
Q
21.9
10.8
8.1
1.5
7
ns
ten
OE
Q
19.8
10.8
8.5
1.5
7.5
ns
tdis
OE
Q
19.1
18.1
7.1
1.5
6.5
ns
1
1
1
1
ns
tsk(o)
7.11 Switching Characteristics, SN74LVC374A
over operating free-air temperature range (unless otherwise noted)
SN74LVC374A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–40°C TO 125°C
VCC = 1.8 V
± 0.15 V
MIN
fmax
MAX
55
VCC = 2.5 V
± 0.2 V
MIN
MAX
95
VCC = 2.7 V
MIN
MAX
80
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
100
MHz
tpd
CLK
Q
21.9
10.8
8.1
1.5
7.6
ns
ten
OE
Q
19.8
10.8
8.9
1.5
8.0
ns
tdis
OE
Q
19.1
18.1
7.7
1.5
7.0
ns
1.5
1.5
1.5
1.5
ns
tsk(o)
7.12 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
8
Outputs enabled
Power dissipation capacitance
Outputs
per flip-flop
disabled
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f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
53
54
54.5
12
15
13.5
UNIT
pF
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7.13 Typical Characteristics
6
8
TPD
TPD in ns
7
5
4
5
TPD (ns)
TPD (ns)
6
4
3
3
2
2
1
1
0
0
0.5
1
1.5
2
VCC (Volts)
2.5
3
3.5
0
-100
-50
D001
Figure 1. SN74LVC374A Clock to Q TDP VCC vs TPD at 25°C
0
50
Temperature (°C)
100
150
D001
Figure 2. SN74LVC374A Clock to Q Across Temp 3.3-V VCC
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O)
ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q
outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are
in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of
these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for
partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current
backflow through the devices when they are powered down. To ensure the high-impedance state during power
up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
OE
CLK
1
11
C1
1D
3
2
1D
1Q
To Seven Other Channels
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Function Table (Each Flip-Flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC374A SN74LVC374A
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10 Applications and Implementation
10.1 Application Information
The SN74LVC374A is a high-drive CMOS device that can be used for a multitude of bus interface type
applications where the data needs to be retained or latched. It can produce 32 mA of drive current at 3.3 V;
therefore, making it ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The
inputs are 5.5-V tolerant allowing it to translate down to VCC.
10.2 Typical Application
Regulated 3.3 V
OE
VCC
CLK
1D
1Q
µC
System Logic
µC or
8D
LEDs
8Q
System Logic
GND
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Rise time and fall time specs: See (Δt/ΔV) in Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
12
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Product Folder Links: SN54LVC374A SN74LVC374A
SN54LVC374A, SN74LVC374A
www.ti.com
SCAS296O – JANUARY 1993 – REVISED JULY 2014
Typical Application (continued)
10.2.3 Application Curves
20
ICC 1.8V
ICC 2.5V
ICC 3.3V
18
16
ICC (mA)
14
12
10
8
6
4
2
0
0
20
40
60
80
Frequency (MHz)
100
120
D001
Figure 4. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC pins, then a 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. A 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Figure 5 shows the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever makes more sense or is more
convenient. It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an
output enable terminal it will disable the outputs section of the part when asserted. This will not disable the input
section of the IOs so they also cannot float when disabled.
12.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 5. Layout Diagram
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC374A SN74LVC374A
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SN54LVC374A, SN74LVC374A
SCAS296O – JANUARY 1993 – REVISED JULY 2014
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC374A
Click here
Click here
Click here
Click here
Click here
SN74LVC374A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC374A SN74LVC374A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9757401Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629757401Q2A
SNJ54LVC
374AFK
5962-9757401QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757401QR
A
SNJ54LVC374AJ
5962-9757401QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757401QS
A
SNJ54LVC374AW
SN74LVC374ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC374A
Samples
SN74LVC374ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC374A
Samples
SN74LVC374ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC374A
Samples
SN74LVC374ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC374A
Samples
SN74LVC374ADWRE4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC374A
Samples
SN74LVC374AN
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74LVC374AN
Samples
SN74LVC374ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC374A
Samples
SN74LVC374APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC374A
Samples
SN74LVC374APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
LC374A
Samples
SN74LVC374APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC374A
Samples
SN74LVC374APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC374A
Samples
SN74LVC374ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LC374A
Samples
SNJ54LVC374AFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629757401Q2A
SNJ54LVC
374AFK
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54LVC374AJ
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757401QR
A
SNJ54LVC374AJ
SNJ54LVC374AW
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757401QS
A
SNJ54LVC374AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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