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SN54LVC540A, SN74LVC540A
SCAS297N – JANUARY 1993 – REVISED JUNE 2014
SNx4LVC540A Octal Buffers/Drivers with 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC)
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Handset: Smartphone
Network Switch
Health and Fitness; Wearables
3 Description
The SN54LVC540A octal buffer/driver is designed for
2.7-V to 3.6-V VCC operation, and the SN74LVC540A
octal buffer/driver is designed for 1.65-V to 3.6-V VCC
operation.
Device Information(1)
PART NUMBER
SN74LVC540A
PACKAGE
BODY SIZE (NOM)
SIOC (20)
12.80 mm × 7.50 mm
SO (20)
12.60 mm × 5.30 mm
SSOP (20)
7.50 mm × 5.30 mm
TVSOP (20)
5.00 mm × 4.40 mm
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
OE1
OE2
A1
1
19
2
18
Y1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC540A, SN74LVC540A
SCAS297N – JANUARY 1993 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
5
5
6
6
6
7
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, SN54LVC540A ...............
Switching Characteristics, SN74LVC540A ...............
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (May 2005) to Revision N
Page
•
Updated document to new data sheet standards................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. .............................................................................................................................................. 4
•
Changed MAX ambient temperature to 125°C....................................................................................................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics. .............................................................................................................................................. 7
•
Added Device and Documentation Support. ........................................................................................................................ 12
•
Added ESD warning. ............................................................................................................................................................ 12
•
Added Mechanical, Packaging, and Orderable Information. ................................................................................................ 12
2
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SCAS297N – JANUARY 1993 – REVISED JUNE 2014
6 Pin Configuration and Functions
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A3
A4
A5
A6
A7
OE2
1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54LVC540A . . . FK PACKAGE
(TOP VIEW)
A2
A1
OE1
VCC
SN54LVC540A . . . J OR W PACKAGE
SN74LVC540A . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
OE1
1
I
Output enable
A1
2
I
A1 input
A2
3
I
A2 input
A3
4
I
A3 input
A4
5
I
A4 input
A5
6
I
A5 input
A6
7
I
A6 input
A7
8
I
A7 input
A8
9
I
A8 input
GND
10
–
Ground pin
Y8
11
O
Y8 output
Y7
12
O
Y7 output
Y6
13
O
Y6 output
Y5
14
O
Y5 output
Y4
15
O
Y4 output
Y3
16
O
Y3 output
Y2
17
O
Y2 output
Y1
18
O
Y1 output
OE2
19
I
Output enable
VCC
20
–
Power pin
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SCAS297N – JANUARY 1993 – REVISED JUNE 2014
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
4
Electrostatic discharge
MAX
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
UNIT
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCAS297N – JANUARY 1993 – REVISED JUNE 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LVC540A
VCC
Operating
Supply voltage
Data retention only
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
V
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
High-level output current
0.8
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
TA
(1)
V
V
mA
4
VCC = 2.3 V
Low-level output current
V
0.8
VCC = 1.65 V
IOL
V
0.65 × VCC
VCC = 2.7 V to 3.6 V
VIL
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
SN74LVC540A
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
Operating free-air temperature
–55
125
–40
125
mA
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC540A
THERMAL METRIC (1)
DB
DGV
94.5
114.7
RθJC(top) Junction-to-case (top) thermal resistance
56.2
29.8
RθJB
Junction-to-board thermal resistance
49.7
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
DW
NS
PW
88.3
74.7
102.5
51.1
40.5
35.9
56.2
50.9
42.3
53.5
18.1
0.8
20.0
14.3
2.2
49.2
55.5
50.5
41.9
52.9
–
–
–
–
–
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 1993–2014, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA
1.65 V
IOH = –8 mA
2.3 V
IOH = –24 mA
(1)
(2)
1.7
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
V
0.2
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
3.6 V
VI or VO = 5.5 V
0
IOZ
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
ΔICC
1.2
2.7 V to 3.6 V
VI = 0 to 5.5 V
UNIT
VCC – 0.2
2.7 V
Ioff
ICC
MIN TYP (1) MAX
MAX
1.65 V to 3.6 V
IOL = 100 μA
II
SN74LVC540A
VCC – 0.2
2.7 V to 3.6 V
IOH = –12 mA
VOL
MIN TYP
(1)
1.65 V to 3.6 V
IOH = –100 μA
VOH
SN54LVC540A
VCC
±5
μA
±10
μA
±15
±10
μA
10
10
10
10
500
500
±5
3.6 V
2.7 V to 3.6 V
V
μA
μA
Ci
VI = VCC or GND
3.3 V
4
4
pF
Co
VO = VCC or GND
3.3 V
5.5
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
7.6 Switching Characteristics, SN54LVC540A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC540A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
tdis
OE
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
UNIT
MAX
MIN
MAX
7.1
1
5.3
ns
Y
8
1
6.6
ns
Y
8.2
1
7.4
ns
7.7 Switching Characteristics, SN74LVC540A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC540A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
1
16.4
1
7.8
1
7.1
1.4
5.3
ns
ten
OE
Y
1
16.5
1
10.5
1
8
1.1
6.6
ns
tdis
OE
Y
1
15.9
1
9
1
8.2
1.8
7.4
ns
1
ns
tsk(o)
6
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VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
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Product Folder Links: SN54LVC540A SN74LVC540A
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SCAS297N – JANUARY 1993 – REVISED JUNE 2014
7.8 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Power dissipation capacitance per Outputs enabled
buffer/driver
Outputs disabled
Cpd
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
63
56
31
3
3
3
UNIT
pF
7.9 Typical Characteristics
4
6
TPD
TPD
3.5
5
3
TPD (ns)
TPD (ns)
4
3
2.5
2
1.5
2
1
1
0.5
0
0
0.5
1
1.5
2
VCC (V)
2.5
3
3.5
0
-100
-50
D001
Figure 1. TPD Across Temperature at 25°C
0
50
Temperature (°C)
100
150
D001
Figure 2. TPD Across Temperature at 3.3 V
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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SCAS297N – JANUARY 1993 – REVISED JUNE 2014
9 Detailed Description
9.1 Overview
These devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs
and outputs on opposite sides of the package that facilitate printed circuit board layout. The 3-state control gate
is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs
are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the
use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified
for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current
backflow through the devices when they are powered down. To ensure the high-impedance state during power
up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
OE1
OE2
A1
1
19
2
18
Y1
To Seven Other Channels
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff Feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
A
OUTPUT
Y
L
L
H
L
H
L
H
X
X
Z
X
H
X
Z
OE1
OE2
L
L
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10 Application and Implementation
10.1 Application Information
The SN74LVC540A is a high drive CMOS device that can be used for a multitude of bus interface type
applications where the data needs to be retained or latched . It can produce 24 mA of drive current at 3.3 V
making it ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are
5.5 V tolerant allowing it to translate down to VCC.
10.2 Typical Application
Regulated 3.6 V
OE1
VCC
OE2
A1
uC or
System Logic
A8
Y1
uC
System Logic
LEDs
Y8
GND
Figure 5. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
10.2.3 Application Curves
300
250
ICC - mA
200
150
100
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
50
0
0
10
20
30
40
Frequency - MHz
50
60
D003
Figure 6. ICC vs Frequency at 3.3 V
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the IO’s so they also cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC540A SN74LVC540A
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SN54LVC540A, SN74LVC540A
SCAS297N – JANUARY 1993 – REVISED JUNE 2014
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC540A
Click here
Click here
Click here
Click here
Click here
SN74LVC540A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC540A SN74LVC540A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC540ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
SN74LVC540ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
SN74LVC540ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC540A
Samples
SN74LVC540ADWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC540A
Samples
SN74LVC540ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC540A
Samples
SN74LVC540ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC540A
Samples
SN74LVC540APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
SN74LVC540APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
SN74LVC540APWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
SN74LVC540APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
SN74LVC540APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC540A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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