SN74LVCC4245A
SCAS584N – NOVEMBER 1996 – REVISED DECEMBER 2022
SN74LVCC4245A Octal Dual-Supply Bus Transceiver
With Configurable Output Voltage and 3-State Outputs
1 Features
3 Description
•
•
This 8-bit (octal) noninverting bus transceiver uses
two separate power-supply rails. The A port, VCCA,
is dedicated to accepting a 5-V supply level, and the
configurable B port, which is designed to track VCCB,
accepts voltages from 3 V to 5 V. This allows for
translation from a 3.3-V to a 5-V environment and vice
versa.
•
•
•
Bidirectional voltage translator
4.5 V to 5.5 V on A port and
2.7 V to 5.5 V on B port
Control inputs VIH and VIL levels are referenced to
VCCA voltage
Latch-up performance exceeds 250 mA
per JESD 17
ESD protection exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
Level translation
Personal electronics
Industrial
Enterprise
Telecom
The SN74LVCC4245A device is designed for
asynchronous communication between data buses.
The SN74LVCC4245A device transmits data from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be
used to disable the device so the buses effectively are
isolated. The control circuitry (DIR, OE) is powered by
VCCA.
Package Information(1)
PART NUMBER
SN74LVCC4245A
(1)
PACKAGE
BODY SIZE (NOM)
DB (SSOP, 24)
8.20 mm × 5.30 mm
DW (SOIC, 24)
15.40 mm × 7.50 mm
NS (SOP, 24)
15.00 mm × 5.30 mm
PW (TSSOP, 24)
7.80 mm × 4.40 mm
For available packages, see the orderable addendum at the
end of the data sheet.
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCC4245A
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SCAS584N – NOVEMBER 1996 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Operating Characteristics........................................... 7
6.8 Typical Characteristics................................................ 7
7 Power-Up Consideration.................................................8
8 Parameter Measurement Information For A to B
VCCA = 4.5 V to 5.5 V and VCCB = 2.7 V to 3.6 V............ 9
9 Parameter Measurement Information For A to B
VCCA = 4.5 V to 5.5 V and VCCB = 3.6 V to 5.5 V.......... 10
10 Parameter Measurement Information For B to A
VCCA = 4.5 V to 5.5 V and VCCB = 2.7 V to 3.6 V...........11
11 Parameter Measurement Information For B to A
VCCA = 4.5 V to 5.5 V and VCCB = 3.6 V to 5.5 V.......... 12
12 Detailed Description....................................................13
12.1 Overview................................................................. 13
12.2 Functional Block Diagram....................................... 13
12.3 Feature Description.................................................13
12.4 Device Functional Modes........................................13
13 Application and Implementation................................ 14
13.1 Application Information........................................... 14
13.2 Typical Application.................................................. 14
14 Power Supply Recommendations..............................15
15 Layout...........................................................................16
15.1 Layout Guidelines................................................... 16
15.2 Layout Example...................................................... 16
16 Device and Documentation Support..........................17
16.1 Documentation Support.......................................... 17
16.2 Receiving Notification of Documentation Updates..17
16.3 Support Resources................................................. 17
16.4 Trademarks............................................................. 17
16.5 Electrostatic Discharge Caution..............................17
16.6 Glossary..................................................................17
17 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (March 2005) to Revision N (December 2022)
Page
• Removed ordering information........................................................................................................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added the Pin Configuration and Functions, Detailed Description, Application and Implementation, Layout
sections ..............................................................................................................................................................1
• Added thermal values for PW package.............................................................................................................. 5
2
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SCAS584N – NOVEMBER 1996 – REVISED DECEMBER 2022
5 Pin Configuration and Functions
VCCA
1
24
DIR
2
23
VCCB
NC
A1
3
22
OE
A2
4
21
B1
A3
5
20
B2
A4
6
19
B3
A5
7
18
B4
A6
8
17
B5
A7
9
16
B6
A8
10
15
B7
GND
11
14
B8
GND
12
13
GND
Not to scale
Figure 5-1. DB, DW, NS, or PW Package, SSOP, SOIC, SOP, or TSSOP (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
VCCA
1
—
DIR
2
I
Dir input
A1
3
I/O
A1 port
A2
4
I/O
A2 port
A3
5
I/O
A3 port
A4
6
I/O
A4 port
A5
7
I/O
A5 port
A6
8
I/O
A6 port
A7
9
I/O
A7 port
A8
10
I/O
A8 port
GND
11
—
GND
12
—
GND
13
—
B8
14
I/O
B8 port
B7
15
I/O
B7 port
B6
16
I/O
B6 port
B5
17
I/O
B5 port
B4
18
I/O
B4 port
B3
19
I/O
B3 port
B2
20
I/O
B2 port
B1
21
I/O
B1 port
OE
22
I
NC
23
—
Unconnected
VCCB
24
—
B port power
(1)
A port power
Ground
Output Enable active low
Signal Types: I = Input, O = Output, I/O = Input or Output.
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SCAS584N – NOVEMBER 1996 – REVISED DECEMBER 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
VCCB
Supply voltage range
VI
Input voltage range(2)
MIN
MAX
–0.5
6
I/O ports (A port)
–0.5
VCCA + 0.5
I/O ports (B port)
–0.5
VCCB + 0.5
Except I/O ports
–0.5
VCCA + 0.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
UNIT
V
V
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance(3)
Tstg
Storage temperature range
(1)
(2)
(3)
DW package
46
NS package
65
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
VALUE
UNIT
2000
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
(1)
VCCA
VCCB
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
4.5
5
5.5
V
VCCB
Supply voltage
2.7
3.3
5.5
V
VIHA
High-level input voltage
4.5 V
5.5 V
VIHB
4.5 V
High-level input voltage
5.5 V
VILA
4.5 V
Low-level input voltage
5.5 V
VILB
4.5 V
Low-level input voltage
5.5 V
VIH
High-level input voltage (control pins) (referenced to VCCA)
2.7 V
2
3.6 V
2
5.5 V
2
2.7 V
2
3.6 V
2
5.5 V
3.85
V
V
2.7 V
0.8
3.6 V
0.8
5.5 V
0.8
2.7 V
0.8
3.6 V
0.8
5.5 V
4.5 V
5.5 V
4.5 V
V
V
1.65
2.7 V
2
3.6 V
2
5.5 V
2
V
2.7 V
0.8
3.6 V
0.8
VIL
Low-level input voltage (control pins) (referenced to VCCA)
VIA
Input voltage
0
VCCA
V
VIB
Input voltage
0
VCCB
V
VOA
Output voltage
0
VCCA
V
VOB
Output voltage
0
VCCB
V
IOHA
High-level output current
4.5 V
3V
–24
mA
IOHB
High-level output current
4.5 V
2.7 V to 4.5 V
–24
mA
IOLA
Low-level output current
4.5 V
3V
24
mA
IOLB
Low-level output current
4.5 V
2.7 V to 4.5 V
24
mA
TA
Operating free-air temperature
85
°C
5.5 V
(1)
5.5 V
V
0.8
–40
All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVCC4245A
THERMAL METRIC(1)
PW (TSSOP)
DB (SSOP)
24 PINS
24 PINS
R θJA
Junction-to-ambient thermal resistance
100.6
90.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.7
51.9
°C/W
R θJB
Junction-to-board thermal resistance
55.8
49.7
°C/W
ψ JT
Junction-to-top characterization parameter
6.8
18.8
°C/W
ψ JB
Junction-to-board characterization parameter
55.4
49.3
°C/W
(1)
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCAS584N – NOVEMBER 1996 – REVISED DECEMBER 2022
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOHA
TEST CONDITIONS
VCCA
VCCB
IOH = –100 µA
4.5 V
IOH = –24 mA
4.5 V
IOH = –100 µA
4.5 V
IOH = –12 mA
4.5 V
VOHB
IOH = –24 mA
VOLA
4.5 V
4.4
4.49
3V
3.76
4.25
3V
2.9
2.99
2.7 V
2.2
2.5
3V
2.46
2.85
2.7 V
2.1
2.3
3V
2.25
2.65
4.5 V
3.76
4.25
V
3V
4.5 V
3V
IOL = 100 µA
4.5 V
3V
IOL = 12 mA
4.5 V
2.7 V
0.11
0.44
2.7 V
0.22
0.5
4.5 V
II
Control inputs
VI = VCCA or GND
IOZ (1)
A or B ports
VO = VCCA/B or GND,
0.44
V
0.1
3V
0.21
0.44
4.5 V
0.18
0.44
3.6 V
±0.1
±1
5.5 V
±0.1
±1
5.5 V
3.6 V
±0.5
±5
5.5 V
Open
8
80
3.6 V
8
80
5.5 V
8
80
3.6 V
5
50
5.5 V
8
80
5.5 V
VI = VIL or VIH
0.1
0.21
UNIT
V
4.5 V
An = VCC or GND
V
µA
µA
µA
IO (A port) = 0,
Bn = VCCB or GND
5.5 V
A to B
An = VCCA or GND,
IO (B port) = 0
5.5 V
A port
VI = VCCA – 2.1 V, Other inputs at VCCA or GND,
OE at GND and DIR at VCCA
5.5 V
5.5 V
1.35
1.5
OE
VI = VCCA – 2.1 V, Other inputs at VCCA or GND,
DIR at VCCA or GND
5.5 V
5.5 V
1
1.5
DIR
VI = VCCA – 2.1 V, Other inputs at VCCA or GND,
OE at VCCA or GND
5.5 V
3.6 V
1
1.5
ΔICCB (2)
B port
VI = VCCB – 0.6 V, Other inputs at VCCB or GND,
OE at GND and DIR at GND
5.5 V
3.6 V
0.35
0.5
Ci
Control inputs
VI = VCCA or GND
Open
Open
5
pF
Cio
A or B ports
VO = VCCA/B or GND
5V
3.3 V
11
pF
ICCB
ΔICCA (2)
(1)
(2)
6
3V
MAX
IOL = 24 mA
IOL = 24 mA
B to A
TYP
IOL = 100 µA
VOLB
ICCA
MIN
µA
mA
mA
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.
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6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 8-1 through
Figure 11-1)
PARAMETER
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCA = 5 V ± 0.5 V,
VCCB = 5 V ± 0.5 V
VCCA = 5 V ± 0.5 V,
VCCB = 2.7 V to 3.6 V
UNIT
MIN
MAX
MIN
MAX
1
7.1
1
7
1
6
1
7
1
6.8
1
6.2
1
6.1
1
5.3
1
9
1
9
1
8.3
1
8
1
8.2
1
10
1
8.1
1
10.2
1
4.7
1
5.2
1
4.9
1
5.2
1
5.4
1
5.9
1
6.3
1
7.4
ns
ns
ns
ns
ns
ns
6.7 Operating Characteristics
VCCA = 5 V, VCCB = 3.3 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per transceiver
CL = 0,
Outputs disabled
TYP
f = 10 MHz
20
6.5
UNIT
pF
6.8 Typical Characteristics
14
10
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
2
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
6
4
2
0
50
100
150
200
250
300
0
50
CL – Load Capacitance – pF
Figure 6-1. Propagation Delay (Low to High
Transition)
vs Load Capacitance
100
150
200
250
300
CL – Load Capacitance – pF
Figure 6-2. Propagation Delay (High to Low
Transition)
vs Load Capacitance
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SCAS584N – NOVEMBER 1996 – REVISED DECEMBER 2022
7 Power-Up Consideration
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up
problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pull up resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
then ramp it with VCCA. Otherwise, keep DIR low.
For more information, refer to the Voltage-Level-Translation Devices application note.
8
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8 Parameter Measurement Information For A to B
VCCA = 4.5 V to 5.5 V and VCCB = 2.7 V to 3.6 V
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 8-1. Load Circuit and Voltage Waveforms
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9 Parameter Measurement Information For A to B
VCCA = 4.5 V to 5.5 V and VCCB = 3.6 V to 5.5 V
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
3.5 V
1.5 V
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 9-1. Load Circuit and Voltage Waveforms
10
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10 Parameter Measurement Information For B to A
VCCA = 4.5 V to 5.5 V and VCCB = 2.7 V to 3.6 V
2 × VCCA
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCA
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
S1 at 2 × VCCA
(see Note B)
tPLZ
VCCA
1.5 V
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 10-1. Load Circuit and Voltage Waveforms
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11 Parameter Measurement Information For B to A
VCCA = 4.5 V to 5.5 V and VCCB = 3.6 V to 5.5 V
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
3V
1.5 V
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 11-1. Load Circuit and Voltage Waveforms
12
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12 Detailed Description
12.1 Overview
SN74LVCC4245A is an 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has
VCCB, which is set at 3.3 V, and A port has VCCA, which is set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa, designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
12.2 Functional Block Diagram
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
12.3 Feature Description
•
•
24 mA drive at 3-V supply
– Good for heavier loads and longer traces
Low VIH
– Allows 3.3-V to 5-V translation
12.4 Device Functional Modes
Table 12-1. Function Table
(Each Transceiver)
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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13 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
13.1 Application Information
The SN74LVCC4245A device pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin
'245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the
SN74LVC4245A to align with the conventional SN74LVC4245A device's pinout. SN74LVCC4245A is a high
drive CMOS device that can be used for a multitude of bus interface type applications where output drive or PCB
trace length is a concern.
13.2 Typical Application
3V
5V
VCCA
DIR
VCCB
B1
C/System
Logic/LEDs
OE
C or System
Logic
B8
A1
A8
GND
Figure 13-1. Typical Application Schematic
13.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create
fast edges into light loads so routing and load conditions should be considered to prevent ringing.
14
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13.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
• For rise time and fall time specifcations, see (Δt/ΔV) in the Section 6.3 table.
• For specified high and low levels, see (VIH and VIL) in the Section 6.3 table.
2. Recommend Output Conditions:
• Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Section 6.1 table.
• Outputs should not be pulled above VCC.
• Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
13.2.3 Application Curves
60
100
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
80
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–100
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
VOL – V
Figure 13-2. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
Figure 13-3. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
14 Power Supply Recommendations
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device terminals. Take these precautions to guard against such powerup problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
then ramp it with VCCA. Otherwise, keep DIR low.
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15 Layout
15.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 15-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
15.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 15-1. Layout Diagram
16
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16 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
16.1 Documentation Support
16.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, Voltage-Level-Translation Devices application note
16.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
16.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
16.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
16.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
16.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
17 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVCC4245ADBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
SN74LVCC4245ADW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC4245A
Samples
SN74LVCC4245ADWE4
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC4245A
Samples
SN74LVCC4245ADWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
LVCC4245A
Samples
SN74LVCC4245ADWRG4
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC4245A
Samples
SN74LVCC4245ANSR
ACTIVE
SO
NS
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC4245A
Samples
SN74LVCC4245APW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
SN74LVCC4245APWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
SN74LVCC4245APWRE4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
SN74LVCC4245APWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
SN74LVCC4245APWT
ACTIVE
TSSOP
PW
24
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
SN74LVCC4245APWTE4
ACTIVE
TSSOP
PW
24
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LG245A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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