SN74LVCE161284DLR

SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 FEATURES • • • • • • • Auto-Power-Up Feature Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at A9–A13 Pins 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Ioff and Power-Up 3-State Support Hot Insertion Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection – ±4 kV – Human-Body Model – ±8 kV – IEC 61000-4-2, Contact Discharge (Connector Pins) – ±15 kV – IEC 61000-4-2, Air-Gap Discharge (Connector Pins) – ±15 kV – Human-Body Model (Connector Pins) DGG OR DL PACKAGE (TOP VIEW) HD A9 A10 A11 A12 A13 VCC A1 A2 GND A3 A4 A5 A6 GND A7 A8 VCC PERI LOGIC IN A14 A15 A16 A17 HOST LOGIC OUT 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 DIR Y9 Y10 Y11 Y12 Y13 VCC CABLE B1 B2 GND B3 B4 B5 B6 GND B7 B8 VCC CABLE PERI LOGIC OUT C14 C15 C16 C17 HOST LOGIC IN DESCRIPTION/ORDERING INFORMATION The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line. ORDERING INFORMATION PACKAGE (1) TA 0°C to 70°C SSOP – DL TSSOP – DGG (1) ORDERABLE PART NUMBER Tube SN74LVCE161284DL Tape and reel SN74LVCE161284DLR Tape and reel SN74LVCE161284DGGR TOP-SIDE MARKING LVCE161284 LVCE161284 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low. The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant. The Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting the BUSY signal in the cable at power on. FUNCTION TABLE INPUTS 2 DIR HD L L L H H L H H OUTPUT MODE Open drain A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT Totem pole B1–B8 to A1–A8 and C14–C17 to A14–A17 Totem pole B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14–C17 to A14–A17 Open drain A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT Totem pole C14–C17 to A14–A17 Totem pole A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 LOGIC DIAGRAM VCC CABLE DIR HD 42 48 1 See Note A See Note A See Note B B1-B8 A1-A8 A9-A13 Y9-Y13 See Note C PERI LOGIC IN 19 30 A14-A17 HOST LOGIC OUT PERI LOGIC OUT C14-C17 24 25 HOST LOGIC IN NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. B. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. C. Active input detection circuit forces Y9-Y13 to the high state after power-on, until one of the A9-A13 goes high (see Figure 1). 3 SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 D A9 A10 A11 A12 A13 Timer Q OUT C R Auto-Power-Up Active Input Detection Circuit VCC = 3.3 V VCC CABLE = 5 V TA = 25°C TYP = 80 ns VCC and VCC CABLE 700 ns (TYP) An (one of A9−A13) 50% VCC Initial Activation Time Y9−Y13 Other Than Yn 50% VCC CABLE NOTE A: One of A9−A13 is switched as shown above, and the other four inputs are forced to low state. Figure 1. Error-Free Circuit Timing 4 SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com Absolute Maximum Ratings SCES541 – JANUARY 2004 – REVISED MARCH 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC CABLE Supply voltage range –0.5 7 V VCC –0.5 4.6 V –2 7 V –0.5 VCC + 0.5 Supply voltage range Cable side (2) (3) UNIT VI, VO Input and output voltage range IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA Except PERI LOGIC OUT ±50 mA ±100 mA IO Continuous output current Peripheral side (2) PERI LOGIC OUT ±200 mA VO = 5.5 V and VCC CABLE = 3 V 65 mA DGG package 70 DL package 63 Continuous current through each VCC or GND ISK Output high sink current θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) V –65 °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The ac input-voltage pulse duration is limited to 40 ns if the amplitude is greater than –0.5 V. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX VCC CABLE Supply voltage for the cable side, VCC CABLE ≥ VCC 3 5.5 V VCC 3 3.6 V Supply voltage A, B, DIR, and HD VIH High-level input voltage VIL Low-level input voltage 2 C14–C17 2.3 HOST LOGIC IN 2.6 PERI LOGIC IN Input voltage VO Open-drain output voltage 2 0.8 C14–C17 0.8 HOST LOGIC IN 1.6 High-level output current 0 VCC Cable side 0 5.5 HD low 0 A outputs and HOST LOGIC OUT –4 (1) Operating free-air temperature mA 14 A outputs and HOST LOGIC OUT 4 PERI LOGIC OUT TA V –0.5 B and Y outputs Low-level output current 5.5 V –14 PERI LOGIC OUT IOL V 0.8 Peripheral side HD high, B and Y outputs IOH V A, B, DIR, and HD PERI LOGIC IN VI UNIT mA 84 0 70 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5 SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ∆Vt Hysteresis (VT+ – VT–) VOH VCC VCC CABLE All inputs except the C inputs and HOST LOGIC IN 3.3 V 5V C inputs IOH = –14 mA HD high, A outputs, and HOST LOGIC OUT IOH = –4 mA PERI LOGIC OUT IOH = –0.5 mA B and Y outputs IOL = 14 mA IOH = –50 µA 3V 3V 2.23 3.3 V 4.7 V 2.4 3V 3V 3.15 V 3.15 V 3.1 3.3 V 4.7 V 4.5 2.4 V 2.8 0.77 IOL = 50 µA 3V IOL = 4 mA 0.2 3V 04 IOL = 84 mA C inputs VI = GND (pullup resistors) All inputs except B or C inputs VI = VCC or GND A1–A8 VO = VCC or GND B outputs Open-drain Y outputs IOZPU IOZPD Ioff B and Y outputs B and Y outputs 3.6 V VO = GND (pullup resistors) VO = 5.5 V VO = GND VO = 5.5 V VI or VO = 0 to 5.5 V 350 µA –5 mA 350 µA –5 mA µA 0 100 3.6 V 3.6 V IO = 0 45 5.5 V 70 3.6 V 0.8 3.3 V 3.3 V R pullup B1–B8, Y9–Y13, C14–C17 3.3 V 3.3 V Ci A9–A13, DIR, HD, PERI LOGIC IN VI = VCC or GND 3.3 V 5V HOST LOGIC IN 6 µA 100 0 VO = 0 V (in high-impedance state) Typical values are measured at TA = 25°C. Connect the VCC pin to the VCC CABLE pin. µA mA 0 to 1.5 V (2) 0 to 1.5 V (2) VO = GND IOH = –35 mA (1) (2) ±1 –3.5 0 to 1.5 V (2) 0 to 1.5 V (2) Power-down output leakage, B1–B8 and Y9–Y13 outputs B1–B8 mA –3.5 VI or VO = 0 to 3.6 V A1–A8 –3.5 3.6 V B1–B8, Y9–Y13 Cio µA 50 3.6 V VI = GND (12 × pullup) ZO 50 ±20 5.5 V VO = GND (pullup resistors) VI = VCC, 3.6 V 5.5 V Power-down input leakage, except A1–A8 or B1–B8 inputs ICC V 0.9 VO = VCC CABLE IOZ UNIT V 0.2 VI = VCC II MAX 0.8 HD high, B and Y outputs PERI LOGIC OUT MIN TYP (1) 0.4 HOST LOGIC IN A outputs and HOST LOGIC OUT VOL TEST CONDITIONS Ω 36 1.15 1.65 6.5 mA kΩ pF 4 VO = VCC or GND 3.3 V 5V 8 13 pF SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2 and Figure 3) FROM (INPUT) TO (OUTPUT) Totem pole A1–A8 B1–B8 Totem pole A9–A13 Y9–Y13 Totem pole B1–B8 A1–A8 Totem pole C14–C17 A14–A17 Totem pole PERI LOGIC IN PERI LOGIC OUT Totem pole HOST LOGIC IN HOST LOGIC OUT PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tslew Totem pole B1–B8 and Y9–Y13 outputs tPZH tPHZ ten–tdis tPHZ tr, tf (1) (2) 2 30 2 30 2 30 2 30 2 12 2 12 2 14 2 14 2 16 2 16 1 18 1 18 0.05 0.4 30 HD B1–B8, Y9–Y13, and PERI LOGIC OUT 2 25 DIR A1–A8 2 25 2 25 2 25 B1–B8 A1–A13 B1–B8 or Y9–Y13 A1–A8 or B1–B8 B1–B8 or A1–A8 Open drain tsk(o) (2) MAX 2 DIR tPLZ MIN TYP (1) 1 3 UNIT ns ns ns ns ns ns V/ns ns ns ns 120 ns 10 ns Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C. Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction. Table 1. ESD Protection PIN TEST CONDITIONS TYP B1–B8, Y9–Y13, PERI LOGIC OUT, C14–C17, HOST LOGIC IN DIR, HD, A1–A8, A9–A13, PERI LOGIC IN, A14–A17, HOST LOGIC OUT UNIT ±15 HBM Contact discharge, IEC 61000-4-2 ±8 Air-gap discharge, IEC 61000-4-2 ±15 ±4 HBM kV kV Operating Characteristics VCC and VCC CABLE = 3.3 V, CL = 0, f = 10 MHz, TA = 25°C PARAMETER Cpd Power dissipation capacitance FROM (INPUT) TO (OUTPUT) A B A Y 6 PERI LOGIC IN PERI LOGIC OUT 10 B A 33 C A 29 HOST LOGIC IN HOST LOGIC OUT 29 TYP UNIT 15 pF 7 SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP www.ti.com SCES541 – JANUARY 2004 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VCC CABLE CL = 50 pF (see Note A) 62 Ω TP1 2.7 V Input (see Note B) 0V tf1 Sink Load From B or Y Output Under Test 95% (VCC CABLE = 5.0 V
0.5 V) 50% (VCC CABLE = 5.0 V
0.5 V) Output (see Note B) tr1 Source Load CL = 50 pF (see Note A) 62 Ω Output (see Note B) 1.9 V (VCC CABLE = 5.0 V
0.5 V) 0.4 V VOLTAGE WAVEFORMS MEASURED AT TP1 SLEW RATE WAVEFORMS (B1−8 AND Y9−13) SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT VCC CABLE 2.7 V Input (see Note C) TP1 1.4 V 1.4 V 0V 500 Ω From B or Y Output CL = 50 pF (see Note A) 2V Output (see Note C) VOH 2V 0.8 V 0.8 V tr VOL tf VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN) OR PERI LOGIC IN TO PERI LOGIC OUT NOTES: A. CL includes probe and jig capacitance. B. When VCC CABLE is 3.3 V
0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and 1.9 V for the falling edge. When VCC CABLE is 5 V
0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge and between 95% VCC CABLE and 50% VCC CABLE for the falling edge.   tslew fall  V CC 95% – 50% tf1 C. D. E. F. G.   tslew rise  1.9 V – 0.4 V tr1 Input rise (tr) and fall (tf) times are 3 ns. Rise and fall times (open drain) are