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SN74LVCH16244A
SCES494B – OCTOBER 2003 – REVISED JUNE 2014
SN74LVCH16244A 16-Bit Buffer/Driver With 3-State Outputs
1 Features
2 Applications
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Member of the Texas Instruments
Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input or Output Voltage With
3.3-V VCC)
Bus Hold on Data Inputs Eliminates the Need for
External Pullup or Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Servers
PCs and Notebooks
Network Switches
Wireless and Telecom Infrastructures
TV Set-top Boxes
Electronic Points of Sale
3 Description
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation. The device can be used as four
4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
The SN74LVCH16244A device is designed
specifically to improve the performance and density of
3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
Device Information(1)
PART NUMBER
SN74LVCH16244A
PACKAGE
BODY SIZE (NOM)
TSSOP (48)
12.50 mm × 6.10 mm
TVSOP (48)
9.70 mm × 4.40 mm
SSOP (48)
15.88 mm × 7.49 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1
25
1OE
3OE
47
2
1A1
46
1A4
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
3
1A2
1A3
36
1Y1
44
5
43
6
3Y2
33
16
32
17
3Y3
3Y4
4OE
41
8
2A1
40
30
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
9
2A2
2A4
14
24
2OE
2A3
3Y1
35
48
13
38
11
37
12
19
4Y1
29
20
4Y2
27
22
26
23
4Y3
4Y4
Pin numbers shown are for the DGG, DGV, and DL packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCH16244A
SCES494B – OCTOBER 2003 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
6
6
7
7
8
8
8
9
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ............................................... 13
11 Power Supply Recommendations ..................... 14
12 Layout................................................................... 14
12.1 Layout Guidelines ................................................. 14
12.2 Layout Example .................................................... 14
13 Device and Documentation Support ................. 15
13.1 Trademarks ........................................................... 15
13.2 Electrostatic Discharge Caution ............................ 15
13.3 Glossary ................................................................ 15
14 Mechanical, Packaging, and Orderable
Information ........................................................... 15
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2005) to Revision B
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated Ioff Feature bullet. ..................................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. .............................................................................................................................................. 6
•
Changed MAX ambient temperature to 125°C. ..................................................................................................................... 7
•
Added Thermal Information table. .......................................................................................................................................... 7
•
Updated tsk(o) values in Switching Characteristics table. ........................................................................................................ 8
•
Added Typical Characteristics. .............................................................................................................................................. 9
2
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SCES494B – OCTOBER 2003 – REVISED JUNE 2014
6 Pin Configuration and Functions
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
Pin Functions
PIN
I/O
DESCRIPTION
1OE
I
Output enable 1
2
1Y1
O
1Y1 Output
3
1Y2
O
1Y2 Output
4
GND
—
Ground pin
5
1Y3
O
1Y3 Output
6
1Y4
O
1Y4 Output
7
VCC
—
Power pin
8
2Y1
O
2Y1 Output
9
2Y2
O
2Y2 Output
10
GND
—
Ground pin
11
2Y3
O
2Y3 Output
12
2Y4
O
2Y4 Output
13
3Y1
O
3Y1 Output
14
3Y2
O
3Y2 Output
15
GND
—
Ground pin
16
3Y3
O
3Y3 Output
17
3Y4
O
3Y4 Output
18
VCC
—
Power pin
NO.
NAME
1
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SCES494B – OCTOBER 2003 – REVISED JUNE 2014
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
4Y1
O
4Y1 Output
4Y2
O
4Y2 Output
21
GND
—
Ground pin
22
4Y3
O
4Y3 Output
23
4Y4
O
4Y4 Output
24
4OE
I
Output enable 4
25
3OE
I
Output enable 3
26
4A4
I
4A4 Input
27
4A3
I
4A3 Input
28
GND
—
29
4A2
I
4A2 Input
30
4A1
I
4A1 Input
31
VCC
—
Power pin
32
3A4
I
3A4 Input
33
3A3
I
3A3 Input
34
GND
—
35
3A2
I
3A2 Input
36
3A1
I
3A1 Input
37
2A4
I
2A4 Input
38
2A3
I
2A3 Input
39
GND
—
40
2A2
I
2A2 Input
41
2A1
I
2A1 Input
42
VCC
—
Power pin
43
1A4
I
1A4 Input
44
1A3
I
1A3 Input
45
GND
—
46
1A2
I
1A2 Input
47
1A1
I
1A1 Input
48
2OE
I
Output enable 2
NO.
NAME
19
20
4
Ground pin
Ground pin
Ground pin
Ground pin
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SCES494B – OCTOBER 2003 – REVISED JUNE 2014
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
Pin Assignments (1)
(56-Ball GQL or ZQL Package)
(1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
2OE
B
1Y2
1Y1
GND
GND
1A1
1A2
C
1Y4
1Y3
VCC
VCC
1A3
1A4
D
2Y2
2Y1
GND
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
VCC
VCC
4A2
4A1
J
4Y3
4Y4
GND
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
Pin Assignments (1)
(54-Ball GRD or ZRD Package)
1
(1)
2
3
4
5
6
A
1Y1
NC
1OE
2OE
NC
1A1
B
1Y3
1Y2
NC
NC
1A2
1A3
C
2Y1
1Y4
VCC
VCC
1A4
2A1
D
2Y3
2Y2
GND
GND
2A2
2A3
E
3Y1
2Y4
GND
GND
2A4
3A1
F
3Y3
3Y2
GND
GND
3A2
3A3
G
4Y1
3Y4
VCC
VCC
3A4
4A1
H
4Y3
4Y2
NC
NC
4A2
4A3
J
4Y4
NC
4OE
3OE
NC
4A4
NC – No internal connection
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
6
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCES494B – OCTOBER 2003 – REVISED JUNE 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating
VCC
Supply voltage
VIH
High-level input voltage
Data retention only
MIN
MAX
1.65
3.6
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
Output voltage
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
IOH
V
1.5
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
mA
10
ns/V
125
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
THERMAL METRIC (1)
DGG
DGV
DL
48 PINS
48 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
64.3
78.4
68.4
RθJC(top)
Junction-to-case (top) thermal resistance
17.6
30.7
34.7
RθJB
Junction-to-board thermal resistance
31.5
41.8
41.0
ψJT
Junction-to-top characterization parameter
1.1
3.8
12.3
ψJB
Junction-to-board characterization parameter
31.2
41.3
40.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 3.6 V
VOL
1.65 V
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
VI = 0 to 5.5 V
3.6 V
VI = 0.58 V
VI = 0.7 V
VI = 0.8 V
µA
–15
45
–45
µA
75
3V
VI = 2 V
–75
VI = 0 to 3.6 V (2)
3.6 V
±500
Ioff
VI or VO = 5.5 V
0
±10
µA
IOZ
VO = 0 to 5.5 V
3.6 V
±10
µA
ICC
ΔICC
(1)
(2)
(3)
±5
2.3 V
VI = 1.7 V
V
15
1.65 V
VI = 1.07 V
II(hold)
V
IOH = –24 mA
IOL = 24 mA
II
UNIT
VCC – 0.2
IOH = –4 mA
IOH = –12 mA
TYP (1) MAX
MIN
VI = VCC or GND
IO = 0
3.6 V ≤ VI ≤ 5.5 V (3)
One input at VCC – 0.6 V,
20
3.6 V
Other inputs at VCC or GND
µA
20
2.7 V to 3.6 V
500
µA
Ci
VI = VCC or GND
3.3 V
5.5
pF
Co
VO = VCC or GND
3.3 V
6
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
This applies in the disabled state only.
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
tdis
OE
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Y
1.5
6.6
1
3.9
1
4.7
1.1
4.1
ns
Y
1.5
7.5
1
4.7
1
5.8
1
4.6
ns
Y
1.5
10.3
1
5.3
1
6.2
1.8
5.8
ns
1
ns
tsk(o)
1
1
1
7.7 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
8
Power dissipation capacitance
per buffer/driver
Outputs enabled
Outputs disabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
33
32
35
2
2
3
f = 10 MHz
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UNIT
pF
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7.8 Typical Characteristics
4
4
TPD in ns
3.5
3.5
3
3
2.5
2.5
TPD - ns
TPD - ns
TPD in ns
2
2
1.5
1.5
1
1
0.5
0.5
0
0
1
2
3
VCC - V
4
0
-100
-50
D004
Figure 1. TDP Across VCC at 25°C
0
50
Temperature (qC)
100
150
D004
Figure 2. TPD Across Temperature at 3.3 V
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
The SN74LVCH16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It
provides true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
The SN74LVCH16244A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
9.2 Functional Block Diagram
1
25
1OE
3OE
47
2
1A1
46
1A4
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
3
1A2
1A3
36
1Y1
44
5
43
6
3Y2
33
16
32
17
3Y3
3Y4
4OE
41
8
2A1
40
30
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
9
2A2
2A4
14
24
2OE
2A3
3Y1
35
48
13
38
11
37
12
19
4Y1
29
20
4Y2
27
22
26
23
4Y3
4Y4
Pin numbers shown are for the DGG, DGV, and DL packages.
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9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
(Each 4-bit Buffer)
INPUTS
12
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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10 Application and Implementation
10.1 Application Information
The SN74LVCH16244A device is a 16-bit buffer driver. This device can be used as four 4-bit, two 8-bit, or one
16-bit buffer. It allows data transmission from the A bus to the Y bus with 4 separate enable pins that control 4
bits each. The output-enable (OE) input can be used to disable sections of the device so that the buses are
effectively isolated. The device has 5.5 V tolerant inputs at any valid VCC. This allows the device to be used in
multi-power systems, and it can be used for down translation. Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
10.2 Typical Application
Regulated 3.6 V
OE
Vcc
DIR
1A1
1Y1
uC
System Logic
uC or
System Logic
1A4
1Y4
LEDs
GND
Figure 4. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
10.2.3 Application Curves
300
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
250
ICC - mA
200
150
100
50
0
0
10
20
30
40
Frequency - MHz
50
60
D004
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
14
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SCES494B – OCTOBER 2003 – REVISED JUNE 2014
13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVCH16244ADGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16244A
SN74LVCH16244ADGVR
ACTIVE
TVSOP
DGV
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LDH244A
SN74LVCH16244ADL
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16244A
SN74LVCH16244ADLG4
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16244A
SN74LVCH16244ADLR
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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