SN74LVTH16543DLR

SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 D D D D D D D D D D D D Members of the Texas Instruments Widebus  Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54LVTH16543 . . . WD PACKAGE SN74LVTH16543 . . . DGG OR DL PACKAGE (TOP VIEW) 1OEAB 1LEAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2LEAB 2OEAB 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEBA 1LEBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2LEBA 2OEBA description The ’LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright  1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 description (continued) When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16543 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH16543 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† (each 8-bit section) INPUTS CEAB LEAB OEAB A OUTPUT B H X X X Z X X H X Z L H L X L L L L B0‡ L L L L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡ Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 logic symbol† 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 56 54 55 1 3 2 29 31 30 28 26 27 2LEAB 1A1 1EN3 G1 1C5 2EN4 G2 2C6 7EN9 G7 7C11 8EN10 G8 8C12 5 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 2A3 2A4 2A5 2A6 2A7 2A8 4 52 51 8 49 9 48 10 47 12 45 13 44 14 43 15 9 12D 2A2 5D 16 11D 10 42 41 17 40 19 38 20 37 21 36 23 34 24 33 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 logic diagram (positive logic) 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 56 54 55 1 3 2 C1 5 1D 52 1B1 C1 1D To Seven Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 29 31 30 28 26 27 C1 15 1D C1 1D To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 42 2B1 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH16543 . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH16543 . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH16543 SN74LVTH16543 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current –24 –32 mA Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 Outputs enabled 2 10 V 10 –40 ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V 7V VCC = 2 2.7 VOL VCC = 3 V Control inputs Ioff II(hold) ( ) A or B ports MIN –1.2 VCC–0.2 2.4 –1.2 VCC–0.2 2.4 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 0.55 VI = 5.5 V VI = 5.5 V 10 10 20 20 VCC = 3.6 V VI = VCC VI = 0 1 1 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care ICC VCC = 3.6 V, IO = 0, VI = VCC or GND V 0.55 IOL = 64 mA VI = VCC or GND IOZPU V 2 0.2 ±1 VCC = 3 V UNIT V 2 IOH = –32 mA IOL = 100 µA VI = 2 V VCC = 3.6 V§, VI = 0 to 3.6 V VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care –5 µA –5 ±100 75 75 –75 –75 µA µA ±500 Outputs high Outputs low Outputs disabled ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 Cio SN74LVTH16543 TYP† MAX MIN ±1 VCC = 3.6 V, VCC = 0 or 3.6 V, II A or B ports‡ SN54LVTH16543 TYP† MAX TEST CONDITIONS ±100* ± 100 µA ±100* ±100 µA 0.19 0.19 5 5 0.19 0.19 0.2 0.2 mA mA 4 4 pF 10 10 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH16543 VCC = 3.3 V ± 0.3 V MIN tw tsu th Pulse duration, LEAB or LEBA low VCC = 2.7 V MIN MAX MIN MAX VCC = 2.7 V MIN 3.3 3.3 3.3 3.3 A or B before LEAB↑ or LEBA↑ Data high 0.5 0.5 0.5 0.5 Data low 0.8 1.3 0.8 1.3 A or B before CEAB↑ or CEBA↑ Data high 0 0 0 0 Data low 0.6 1.1 0.6 1.1 A or B after LEAB↑ or LEBA↑ Data high 1.5 0.7 1.5 0.7 Data low 1.2 1.3 1.2 1.3 A or B after CEAB↑ or CEBA↑ Data high 1.7 0.9 1.7 0.9 Data low 1.6 1.8 1.6 1.8 Setup time Hold time MAX SN74LVTH16543 VCC = 3.3 V ± 0.3 V UNIT MAX ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH16543 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LE A or B tPZH tPZL OE A or B tPHZ tPLZ OE A or B tPZH tPZL CE A or B tPHZ tPLZ CE A or B VCC = 3.3 V ± 0.3 V SN74LVTH16543 VCC = 2.7 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN TYP† MAX 3.4 3.9 1.2 2.3 3.2 3.7 1.1 3.4 3.9 1.2 2.1 3.2 3.7 1.2 4.1 5.1 1.3 2.5 3.9 4.9 1.2 4.1 5.1 1.3 2.3 3.9 4.9 1.2 4.5 5.6 1.3 2.8 4.3 5.4 1.2 4.5 5.6 1.3 2.8 4.3 5.4 1.9 4.9 5.4 2 3.5 4.7 5.2 1.9 4.6 4.7 2 3.3 4.4 4.5 1.2 4.7 5.8 1.3 3 4.5 5.6 1.2 4.7 5.8 1.3 3 4.5 5.6 1.9 5.1 5.6 2 3.6 4.9 5.4 1.9 4.9 5.1 2 3.5 4.7 4.9 MIN MAX 1.1 MIN MIN UNIT MAX ns ns ns ns ns ns † All typical values are at VCC = 3.3 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω 2.7 V 1.5 V Timing Input LOAD CIRCUIT 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH tPLH VOH Output 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVTH16543DGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16543 Samples SN74LVTH16543DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16543 Samples SN74LVTH16543DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16543 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of