SCBS689H − MAY 1997 − REVISED OCTOBER 2003
D Support Mixed-Mode Signal Operation
D
D
D
D
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54LVTH373 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
2D
2Q
3Q
3D
4D
These octal latches are designed specifically for
low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a
5-V system environment.
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
3
8Q
D
(5-V Input and Output Voltages With
3.3-V VCC)
Typical VOLP (Output Ground Bounce)
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