SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
FEATURES
•
•
•
•
•
•
Member of the Texas Instruments Widebus+™
Family
Pinout Optimizes DDR2 DIMM PCB Layout
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
Chip-Select Inputs Gate Data Outputs From
Changing State and Minimize System Power
Consumption
Output Edge-Control Circuitry Minimizes
Switching Noise in Unterminated Line
Supports SSTL_18 Data Inputs
•
•
•
•
•
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on
Control and RESET Inputs
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 5000-V Human-Body Model (A114-A)
– 150-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1
pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to
a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the
A6, D6, and H6 terminals are driven low and should not be used.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared and the data outputs are driven low quickly, relative to the time to disable the differential input receivers.
However, when coming out of reset, the register becomes active quickly, relative to the time required to enable
the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the
low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTU32864C
must ensure that the outputs remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
ORDERING INFORMATION
PACKAGE (1)
TA
0°C to 70°C
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LFBGA – GKE
Tape and reel
SN74SSTU32864CGKER
S864C
LFBGA – ZKE
Tape and reel
SN74SSTU32864CZKER
S864C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always
must be held at a valid logic high or logic low level.
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS
or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR
control and forces the output low. If the DCS control functionality is not desired, the CSR input can be hard-wired
to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs.
The two VREF pins (A3 and T3) are connected together internally by approximately 150 Ω. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS FOR 1:1 REGISTER (C0 = 0, C1 = 0) (1) (2) (3)
1
(1)
(2)
(3)
2
3
4
5
6
A
D1 (DCKE)
NC
VREF
VCC
Q1 (QCKE)
DNU
B
D2
D15
GND
GND
Q2
Q15
C
D3
D16
VCC
VCC
Q3
Q16
D
D4 (DODT)
NC
GND
GND
Q4 (QODT)
DNU
E
D5
D17
VCC
VCC
Q5
Q17
F
D6
D18
GND
GND
Q6
Q18
G
NC
RESET
VCC
VCC
C1
C0
H
CLK
D7 (DCS)
GND
GND
Q7 (QCS)
DNU
J
CLK
CSR
VCC
VCC
NC
NC
K
D8
D19
GND
GND
Q8
Q19
L
D9
D20
VCC
VCC
Q9
Q20
M
D10
D21
GND
GND
Q10
Q21
N
D11
D22
VCC
VCC
Q11
Q22
P
D12
D23
GND
GND
Q12
Q23
R
D13
D24
VCC
VCC
Q13
Q24
T
D14
D25
VREF
VCC
Q14
Q25
Each pin name in parentheses indicates the DDR2 DIMM signal name.
NC - No internal connection
DNU - Do not use
3
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
LOGIC DIAGRAM FOR 1:1 REGISTER CONFIGURATION (POSITIVE LOGIC)
RESET
CLK
CLK
VREF
D1 (DCKE)
G2
H1
J1
A3, T3
A1
D
CLK
Q
CLK
Q
CLK
Q
A5
Q1 (QCKE)
R
D4 (DODT)
D1
D
D5
Q4 (QODT)
R
D7 (DCS)
H2
D
H5
Q7 (QCS)
R
CSR
J2
One of 22 Channels
D2
B1
D
CE
CLK
R
To 21 Other Channels (D3, D5, D6, D8−D25)
4
Q
B5
Q2
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS FOR 1:2 REGISTER A (C0 = 0, C1 = 1) (1) (2) (3)
1
(1)
(2)
(3)
2
3
4
5
6
A
D1 (DCKE)
NC
VREF
VCC
Q1A (QCKEA)
Q1B (QCKEB)
B
D2
DNU
GND
GND
Q2A
Q2B
C
D3
DNU
VCC
VCC
Q3A
Q3B
D
D4 (DODT)
NC
GND
GND
Q4A (QODTA)
Q4B (QODTB)
E
D5
DNU
VCC
VCC
Q5A
Q5B
F
D6
DNU
GND
GND
Q6A
Q6B
G
NC
RESET
VCC
VCC
C1
C0
H
CLK
D7 (DCS)
GND
GND
Q7A (QCSA)
Q7B (QCSB)
J
CLK
CSR
VCC
VCC
NC
NC
K
D8
DNU
GND
GND
Q8A
Q8B
L
D9
DNU
VCC
VCC
Q9A
Q9B
M
D10
DNU
GND
GND
Q10A
Q10B
N
D11
DNU
VCC
VCC
Q11A
Q11B
P
D12
DNU
GND
GND
Q12A
Q12B
R
D13
DNU
VCC
VCC
Q13A
Q13B
T
D14
DNU
VREF
VCC
Q14A
Q14B
Each pin name in parentheses indicates the DDR2 DIMM signal name.
NC - No internal connection
DNU - Do not use
5
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
LOGIC DIAGRAM 1:2 REGISTER-A CONFIGURATION (POSITIVE LOGIC)
RESET
CLK
CLK
VREF
D1 (DCKE)
G2
H1
J1
A3, T3
A1
A5
D
CLK
Q
A6
R
D4 (DODT)
D1
D5
D
CLK
D6
H2
H5
D
CLK
Q4A (QODTA)
Q4B (QODTB)
Q7A (QCSA)
Q
H6
R
CSR
Q1B (QCKEB)
Q
R
D7 (DCS)
Q1A (QCKEA)
Q7B (QCSB)
J2
One of Eleven Channels
D2
B1
B5
D CE
CLK
Q
B6
R
To 10 Other Channels (D3, D5, D6, D8−D14)
6
Q2A
Q2B
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS FOR 1:2 REGISTER B (C0 = 1, C1 = 1) (1) (2) (3)
1
(1)
(2)
(3)
2
3
4
5
6
A
D1
NC
VREF
VCC
Q1A
Q1B
B
D2
DNU
GND
GND
Q2A
Q2B
C
D3
DNU
VCC
VCC
Q3A
Q3B
D
D4
NC
GND
GND
Q4A
Q4B
E
D5
DNU
VCC
VCC
Q5A
Q5B
F
D6
DNU
GND
GND
Q6A
Q6B
G
NC
RESET
VCC
VCC
C1
C0
H
CLK
D7 (DCS)
GND
GND
Q7A (QCSA)
Q7B (QCSB)
J
CLK
CSR
VCC
VCC
NC
NC
K
D8
DNU
GND
GND
Q8A
Q8B
L
D9
DNU
VCC
VCC
Q9A
Q9B
M
D10
DNU
GND
GND
Q10A
Q10B
N
D11 (DODT)
DNU
VCC
VCC
Q11A (QODTA)
Q11B (QODTB)
Q12B
P
D12
DNU
GND
GND
Q12A
R
D13
DNU
VCC
VCC
Q13A
Q13B
T
D14 (DCKE)
DNU
VREF
VCC
Q14A (QCKEA)
Q14B (QCKEB)
Each pin name in parentheses indicates the DDR2 DIMM signal name.
NC - No internal connection
DNU - Do not use
7
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
LOGIC DIAGRAM 1:2 REGISTER-B CONFIGURATION (POSITIVE LOGIC)
RESET
CLK
CLK
VREF
D14 (DCKE)
G2
H1
J1
A3, T3
T1
T5
D
CLK
Q
T6
R
D11 (DODT)
N1
N5
D
CLK
N6
H2
H5
D
CLK
Q11A (QODTA)
Q11B (QODTB)
Q7A (QCSA)
Q
H6
R
CSR
Q14B (QCKEB)
Q
R
D7 (DCS)
Q14A (QCKEA)
Q7B (QCSB)
J2
One of Eleven Channels
D1
A1
A5
D CE
CLK
Q
A6
R
To 10 Other Channels (D2−D6, D8−D10, D12−D13)
8
Q1A
Q1B
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
TERMINAL FUNCTIONS
TERMINAL
NAME
GND
Ground
Ground input
VCC
Power-supply voltage
1.8 V nominal
VREF
Input reference voltage
0.9 V nominal
CLK
Positive master clock input
Differential input
CLK
Negative master clock input
Differential input
C0, C1
Configuration control inputs – Register A, Register B, 1:1, 1:2 select
LVCMOS inputs
RESET
Asynchronous reset input – resets registers and disables VREF data and clock
differential-input receivers. When RESET is low, all Q outputs are forced low.
LVCMOS input
D1–D25
Data inputs – clocked in on the crossing of the rising edge of CLK and the falling edge of
CLK
SSTL_18 inputs
Chip select inputs – disables register clocking (1) when both inputs are high
SSTL_18 inputs
DODT
The outputs of this register bit will not be suspended by the DCS and CSR control.
SSTL_18 input
DCKE
The outputs of this register bit will not be suspended by the DCS and CSR control.
SSTL_18 input
CSR, DCS
Q1–Q25 (2)
Data outputs that are suspended by the DCS and CSR control
1.8-V CMOS outputs
QCS
Data output that will not be suspended by the DCS and CSR control
1.8-V CMOS output
QODT
Data output that will not be suspended by the DCS and CSR control
1.8-V CMOS output
QCKE
Data output that will not be suspended by the DCS and CSR control
1.8-V CMOS output
NC
DNU
(1)
(2)
ELECTRICAL
CHARACTERISTICS
DESCRIPTION
No internal connection
Do not use – inputs are in standby-equivalent mode, and outputs are driven low.
Data inputs = D2, D3, D5, D6, D8–D25 when C0 = 0 and C1 = 0
Data inputs = D2, D3 D5, D6, D8-D14 when C0 = 0 and C1 = 1
Data inputs = D1–D6, D8–D12, D13 when C0 = 1 and C1 = 1
Data outputs = Q2, Q3, Q5, Q6, Q8–when C0 = 0 and C1 = 0
Data outputs = Q2, Q3 Q5, Q6, Q8–Q14 when C0 = 0 and C1 = 1
Data outputs = Q1–Q6, Q8–Q10, Q12, Q13 when C0 = 1 and C1 = 1
FUNCTION TABLES
INPUTS
RESET
DCS
CSR
CLK
CLK
Dn
OUTPUT
Qn
H
L
X
↑
↓
L
L
H
L
X
↑
↓
H
H
H
X
L
↑
↓
L
L
H
X
L
↑
↓
H
H
H
H
H
↑
↓
X
Q0
H
X
X
L or H
L or H
X
Q0
L
X or floating
X or floating
X or floating
X or floating
X or floating
L
INPUTS
OUTPUTS
RESET
CLK
CLK
DCKE,
DCS,
DODT
QCKE,
QCS,
QODT
H
↑
↓
H
H
↑
↓
L
H
L
H
L or H
L or H
X
Q0
L
X or floating
X or floating
X or floating
L
9
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
2.5
V
VI
Input voltage range (2) (3)
–0.5
2.5
V
–0.5
VCC + 0.5
range (2) (3)
UNIT
VO
Output voltage
IIK
Input clamp current
VI < 0 or VI > VCC
±50
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±50
mA
IO
Continuous output current
VO = 0 to VCC
±50
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
±100
–65
V
mA
36
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 2.5 V maximum.
The package thermal impendance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
MIN
NOM
UNIT
Supply voltage
VREF
Reference voltage
VI
Input voltage
VIH
AC high-level input voltage
Data inputs, CSR
VIL
AC low-level input voltage
Data inputs, CSR
VIH
DC high-level input voltage
Data inputs, CSR
VIL
DC low-level input voltage
Data inputs, CSR
VIH
High-level input voltage
RESET, Cn
VIL
Low-level input voltage
RESET, Cn
VICR
Common-mode input voltage range
CLK, CLK
0.675
VI(PP)
Peak-to-peak input voltage
CLK, CLK
600
IOH
High-level output current
–8
mA
IOL
Low-level output current
8
mA
TA
Operating free-air temperature
70
°C
(1)
10
1.7
MAX
VCC
0.49 × VCC
0
0.5 × VCC
1.9
V
0.51 × VCC
V
VCC
V
VREF + 250 mV
V
VREF – 250 mV
VREF + 125 mV
V
VREF – 125 mV
0.65 × VCC
V
V
0.35 × VCC
0
V
1.125
V
V
mV
The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating, unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS
Inputs, literature number SCBA004.
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
ICC
ICCD
IOL = 100 µA
V
0.4
All inputs (2)
VI = VCC or GND
1.9 V
±5
Static standby
RESET = GND
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
Dynamic operating –
clock only
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
Dynamic operating –
per each data input,
1:1 configuration
Chip-select-enabled
low-power active
mode, 1:1
configuration
IO = 0
RESET = VCC, VI = VIH(AC) or VIL(AC),
IO = 0
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
1.9 V
1.8 V
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
IO = 0
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
Data inputs, CSR
VI = VREF ± 250 mV
CLK, CLK
VICR = 0.9 V, VI(PP) = 600 mV
RESET
VI = VCC or GND
UNIT
1.3
0.2
Chip-select-enabled
low-power active
mode, 1:2
configuration
(1)
(2)
1.7 V
1.7 V
Chip-select-enabled
low-power active
mode, clock only
Ci
IOH = –6 mA
MAX
VCC – 0.2
1.7 V to 1.9 V
Dynamic operating –
per each data input,
1:2 configuration
ICCDLP
1.7 V to 1.9 V
IOL = 6 mA
VOL
II
MIN TYP (1)
VCC
V
µA
100
µA
40
mA
33
µA/MHz
19
35
µA/
clock
MHz/
D input
34
µA/MHz
2
1.8 V
µA/
clock
MHz/
D input
2
2.5
1.8 V
3
3.5
2
3
pF
2.5
All typical values are at VCC = 1.8 V, TA = 25°C.
Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open.
Timing Requirements (1)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
MIN
MAX
UNIT
500
MHz
fclock
Clock frequency
tw
Pulse duration, CLK, CLK high or low
tact
Differential inputs active time (2)
10
ns
tinact
Differential inputs inactive time (3)
15
ns
tsu
Setup time
th
(1)
(2)
(3)
Hold time
1
DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high
0.6
DCS before CLK↑, CLK↓, CSR low
0.5
DODT, DCKE, and Data before CLK↑, CLK↓
0.5
DCS, DODT, DCKE, and Data after CLK↑, CLK↓
0.5
ns
ns
ns
All input slew rates are 1 V/ns ±20%.
VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max after RESET is taken high.
VREF data and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max after RESET is taken low.
11
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpdm (1)
CLK and CLK
Q
tpdmss (1)
CLK and CLK
RESET
PARAMETER
fmax
tRPHL
(1)
(1)
VCC = 1.8 V
± 0.1 V
MIN
UNIT
MAX
500
MHz
1.4
2.4
ns
Q
2.6
ns
Q
3
ns
Includes 350-ps test-load transmission-line delay
Output Slew Rates
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
(1)
12
FROM
TO
VCC = 1.8 V
± 0.1 V
UNIT
MIN
MAX
dV/dt_r
20%
80%
1.9
4.9
V/ns
dV/dt_f
80%
20%
1.9
4.9
V/ns
dV/dt_∆ (1)
20% or 80%
80% or 20%
1.5
V/ns
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
ZO = 50 Ω,
tD = 350 ps
Test
Point
DUT
RL = 1 kΩ
CLK
RL = 100 Ω
Clock Inputs
CL = 30 pF
(see Note A)
ZO = 50 Ω,
tD = 350 ps
CLK
ZO = 50 Ω,
tD = 350 ps
Output
Test Point
Out
Test
Point
RL = 1 kΩ
LOAD CIRCUIT
tw
VIH
VREF
Input
VREF
VIL
VCC
LVCMOS
RESET
Input
VCC/2
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
0V
VI(PP)
tinact
tact
ICC
90%
ICC (operating)
Timing
Inputs
VICR
VICR
(see
Note B)
10%
ICC (standby)
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
tPLH
tPHL
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VI(PP)
Timing
Inputs
tsu
VIH
LVCMOS
RESET
Input
VICR
VCC/2
VIL
tPHL
th
VOH
VIH
Input
VREF
Output
VREF
VCC/2
VOL
VIL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E. VREF = VCC/2
F. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF − 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. VI(PP) = 600 mV
I. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
13
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542B – JANUARY 2004 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
DUT
RL = 50 Ω
VOH
Test Point
Out
80%
CL = 5 pF
(see Note A)
Output
20%
VOL
dV_f
dt_f
LOAD CIRCUIT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
dt_r
dV_r
Out
Test Point
CL = 5 pF
(see Note A)
RL = 50 Ω
LOAD CIRCUIT
LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOH
Output
20%
VOL
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
Figure 2. Output Slew-Rate Measurement Information
14
80%
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74SSTU32864CZKER
ACTIVE
Package Type Package Pins Package
Drawing
Qty
LFBGA
ZKE
96
1000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
SNAGCU
Level-3-260C-168 HR
(4)
0 to 70
S864C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74SSTU32864CZKER
Package Package Pins
Type Drawing
LFBGA
ZKE
96
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
5.7
B0
(mm)
K0
(mm)
P1
(mm)
13.7
2.0
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74SSTU32864CZKER
LFBGA
ZKE
96
1000
336.6
336.6
41.3
Pack Materials-Page 2
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