SN74SSTVF16859S8G3



       
  

 
 
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 D Member of the Texas Instruments D D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Widebus Family Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700 Operates at 2.5 V to 2.7 V for PC3200 (QFN Package) Pinout and Functionality Compatible With JEDEC Standard SSTV16859 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications 1-to-2 Outputs to Support Stacked DDR DIMMs Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line Outputs Meet SSTL_2 Class I Specifications Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Pinout Optimizes DIMM PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 description/ordering information VDDQ GND D13 D12 VCC VDDQ GND D11 D10 D9 GND D8 D7 RESET GND CLK CLK VDDQ VCC VREF D6 GND D5 D4 D3 GND VDDQ VCC D2 D1 GND VDDQ This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA QFN − RGQ (Tin-Pb Finish) 0°C to 70°C QFN − RGQ (Matte-Tin Finish) TOP-SIDE MARKING SN74SSTVF16859SR Tape and reel SSF859 SN74SSTVF16859S8 TSSOP − DGG Tape and reel SN74SSTVF16859GR SSTVF16859 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2004, Texas Instruments Incorporated   !"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0 $#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'( ('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+ '+('!5 #" &.. ,&$&%+'+$(0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 


       
  

 
 
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 description/ordering information (continued) All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads. The SN74SSTVF16859 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Q8A VDDQ Q9A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VCC VDDQ D11 RGQ PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND† D10 D9 D8 D7 RESET GND CLK CLK VDDQ VCC VREF D6 D5 D4 Q7B Q6B VDDQ Q5B Q4B Q3B Q2B Q1B VDDQ D1 D2 VCC VDDQ D3 Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B † The center die pad must be connected to GND. FUNCTION TABLE INPUTS 2 RESET CLK CLK D OUTPUT Q H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


       
  

 
 
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 logic diagram (positive logic) RESET CLK CLK VREF 51 48 49 45 One of 13 Channels D1 35 16 1D Q1A C1 R 32 Q1B To 12 Other Channels Pin numbers shown are for the DGG package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W (see Note 4): RGQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 


       
  

 
 
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 recommended operating conditions (see Note 5) MIN VCC Supply voltage PC1600, PC2100, PC2700 NOM MAX VDDQ 2.3 2.7 2.5 2.7 V 2.7 VDDQ Output supply voltage VREF Reference voltage (VREF = VDDQ/2) VI VIH Input voltage AC high-level input voltage Data inputs VIL VIH AC low-level input voltage Data inputs DC high-level input voltage Data inputs VIL VIH DC low-level input voltage Data inputs High-level input voltage RESET VIL VICR Low-level input voltage RESET Common-mode input voltage range CLK, CLK 0.97 VI(PP) Peak-to-peak input voltage CLK, CLK 360 IOH IOL High-level output current −16 Low-level output current 16 PC3200 UNIT PC1600, PC2100, PC2700 1.15 1.25 1.35 PC3200 1.25 1.3 1.35 0 V V VCC V VREF+310mV V VREF−310mV VREF+150mV V V VREF−150mV 1.7 V V 0.7 V 1.53 V mV mA TA Operating free-air temperature 0 70 °C NOTE 5: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = −18 mA IOH = −100 µA VOH ICC ICCD 2.3 V All inputs IOL = 8 mA VI = VCC or GND Static standby RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating − clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating − per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle Data inputs Ci§ 2.3 V to 2.7 V IOH = −8 mA IOL = 100 µA VOL II VCC† 2.3 V TEST CONDITIONS CLK, CLK IO = 0 IO = 0 VI = VREF ± 310 mV VICR = 1.25 V, VI(PP) = 360mV • DALLAS, TEXAS 75265 MAX UNIT −1.2 V VDDQ−0.2 1.95 V 2.3 V to 2.7 V 0.2 2.3 V 0.35 ±5 2.7 V V µA 10 µA 25 mA 19 µA/ MHz 7 µA/ clock MHz/ D input 2.5 V 2.5 V VI = VCC or GND † For this test condition, VDDQ always is equal to VCC. ‡ All typical values are at VCC = 2.5 V, TA = 25°C. § Measured at 50-MHz input frequency POST OFFICE BOX 655303 TYP‡ 2.7 V RESET 4 MIN 2.5 3 3.5 2.5 3 3.5 2.3 3 3.5 pF 


       
  

 
 
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 electrical characteristics for PC3200 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = −18 mA IOH = −100 µA VOH ICC ICCD 2.5 V All inputs IOL = 8 mA VI = VCC or GND Static standby RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating − clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating − per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle Data inputs Ci§ CLK, CLK MIN 2.5 V to 2.7 V IOH = −8 mA IOL = 100 µA VOL II VCC† 2.5 V TEST CONDITIONS TYP‡ MAX UNIT −1.2 V VDDQ−0.2 1.95 V 2.5 V to 2.7 V 0.2 2.5 V 0.35 2.7 V ±5 IO = 0 IO = 0 VI = VREF ± 310 mV VICR = 1.25 V, VI(PP) = 360mV 2.7 V RESET VI = VCC or GND † For this test condition, VDDQ always is equal to VCC. ‡ All typical values are at VCC = 2.6 V, TA = 25°C. § Measured at 50-MHz input frequency µA 10 µA 25 mA 19 µA/ MHz 7 µA/ clock MHz/ D input 2.6 V 2.6 V V 2.5 3 3.5 2.5 3 3.5 2.3 3 3.5 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V† MIN fclock tw Clock frequency tact tinact Differential inputs active time (see Note 6) 1 th Hold time Slow slew rate (see Notes 9 and 10) Fast slew rate (see Notes 8 and 10) Slow slew rate (see Notes 9 and 10) 1 22 Fast slew rate (see Notes 8 and 10) Data before CLK↑, CLK↓ Data after CLK↑, CLK↓ 0.65 0.65 0.75 0.75 0.65 0.65 0.8 0.8 UNIT MAX 500 22 Differential inputs inactive time (see Note 7) Setup time MIN 500 Pulse duration, CLK, CLK high or low tsu MAX VCC = 2.6 V ± 0.1 V† MHz ns 22 ns 22 ns ns ns † For this test condition, VDDQ always is equal to VCC. NOTES: 6. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. 8. For data signal input slew rate ≥1 V/ns. 9. For data signal input slew rate ≥0.5 V/ns and