SN75DP128A
www.ti.com............................................................................................................................................................................................ SLLS940 – NOVEMBER 2008
DisplayPort 1:2 Switch
FEATURES
APPLICATIONS
•
•
•
•
•
1
•
•
•
One Input Port to One of Two Output Ports
Supports Data Rates up to 2.7Gbps
Supports Dual-Mode DisplayPort
Output Waveform Mimics Input Waveform
Characteristics
Enhanced ESD:
– 12kV on all Main Link Pins
– 10kV on all Auxiliary Pins
Enhanced Commercial Temperature Range:
0°C to 85°C
56 Pin 8 × 8 QFN Package
Personal Computer Market
– Desktop PC
– Notebook PC
– Docking Station
– Standalone Video Card
DESCRIPTION
The SN75DP128A is a one Dual-Mode DisplayPort input to one of two Dual-Mode DisplayPort outputs. The
outputs will follow the input signal in a manner that provides the highest level of signal integrity while supporting
the EMI benefits of spread spectrum clocking. Through the SN75DP128A data rates of up to 2.7Gbps through
each link for a total throughput of up to 10.8Gbps can be realized. The SN75DP128A supports Display Port Spec
1.1a.
In addition to the switching of the DisplayPort high speed signal lines, the SN75DP128A also supports the
switching of the bi-directional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD)
channels. The Auxiliary differential pair supports Dual-Mode DisplayPort operation with the ability to be
configured as a bi-directional differential bus while in DisplayPort mode or an I2C™ bus while in TMDS mode.
The SN75DP128A is characterized for operation over ambient air temperature of 0°C to 85°C.
TYPICAL APPLICATION
DisplayPort
Enabled
Monitor or HDTV
DP++
GPU
DP++
SN75DP128A
DP++
DisplayPort
Enabled
Monitor or HDTV
Computer/Notebook/Docking Station
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN75DP128A
SLLS940 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DATA FLOW BLOCK DIAGRAM
DPVadj
ML _ A 0 ( p )
Driver
ML _ A 0 ( n )
V BIAS
50Ω
50Ω
Driver
ML _ IN 0 (p )
Receiver
ML _ IN 0 (n )
Driver
2-to-1
MUX
V BIAS
50Ω
ML _ A 3 ( p )
50Ω
Driver
ML _ IN 1 (p )
ML _ A 3 ( n )
Receiver
ML _ IN 1 (n )
ML _ B 0 (p )
Driver
V BIAS
50Ω
ML _ B 0 (n )
50Ω
ML _ IN 2 (p )
Driver
Receiver
ML _ IN 2 (n )
Driver
V BIAS
50Ω
50Ω
ML _ B 3 (p )
ML _ IN 3 (p )
Driver
ML _ B 3 (n )
Receiver
ML _ IN 3 (n )
HPD _ A
HPD
Switching
Logic
CAD _ A
Priority
HPD _ B
CAD
__
CAD _ B
LP
AUX _ A (p )
AUX _ A (n )
2
AUX (p )
AUX _ B (p )
AUX (n )
AUX _ B (n )
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Priority
LP
GND
CAD_B
HPD_B
VDD
AUX (n)
AUX (p)
HPD
CAD
VDD*1
HPD_A
GND
AUX_A (n)
CAD_A
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42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
43
AUX_B (p)
GND
44
27
GND
AUX_A (p)
45
26
AUX_B(n)
ML_A 3(n)
46
25
ML_B 0(p)
ML_A 3(p)
47
24
ML_B 0(n)
VDD
48
23
VDD
ML_A 2(n)
49
22
ML_B 1(p)
ML_A 2(p)
50
21
ML_B 1(n)
GND
51
20
GND
ML_A 1(n)
52
19
ML_B 2(p)
ML_A 1(p)
53
18
ML_B 2(n)
VDD
54
17
VDD
ML_A 0(n)
55
16
ML_B 3(p)
ML_A 0(p)
56
ML_B 3(n)
15
10 11 12 13 14
ML_IN 2(p)
ML_IN 2(n)
VDD
9
ML_IN 3(n)
8
GND
7
ML_IN 3(p)
6
VDD
ML_IN 0(p)
5
ML_IN 1(p)
VDD
4
ML_IN 1(n)
3
GND
2
ML_IN 0(n)
1
DP Vadj
SN75DP128A
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
MAIN LINK INPUT PINS
ML_IN 0
3, 4
I
DisplayPort Main Link Channel 0 Differential Input
ML_IN 1
6, 7
I
DisplayPort Main Link Channel 1 Differential Input
ML_IN 2
9, 10
I
DisplayPort Main Link Channel 2 Differential Input
ML_IN 3
12, 13
I
DisplayPort Main Link Channel 3 Differential Input
MAIN LINK PORT A OUTPUT PINS
ML_A 0
56, 55
O
DisplayPort Main Link Port A Channel 0 Differential Output
ML_A 1
53, 52
O
DisplayPort Main Link Port A Channel 1 Differential Output
ML_A 2
50, 49
O
DisplayPort Main Link Port A Channel 2 Differential Output
ML_A 3
47, 46
O
DisplayPort Main Link Port A Channel 3 Differential Output
MAIN LINK PORT B OUTPUT PINS
ML_B 0
25, 24
O
DisplayPort Main Link Port B Channel 0 Differential Output
ML_B 1
22, 21
O
DisplayPort Main Link Port B Channel 1 Differential Output
ML_B 2
19, 18
O
DisplayPort Main Link Port B Channel 2 Differential Output
ML_B 3
16, 15
O
DisplayPort Main Link Port B Channel 3 Differential Output
HOT PLUG DETECT PINS
HPD
37
O
Hot Plug Detect Output to the DisplayPort Source
HDP_A
40
I
Port A Hot Plug Detect Input
HPD_B
32
I
Port B hot Plug Detect Input
AUX
36, 35
I/O
Source Side Bidirectional DisplayPort Auxiliary Data Line
AUX_A
45, 43
I/O
Port A Bidirectional DisplayPort Auxiliary Data Line
AUXILIARY DATA PINS
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
AUX_B
28, 26
I/O
DESCRIPTION
I/O
Port B Bidirectional DisplayPort Auxiliary Data Line
CABLE ADAPTER DETECT PINS
CAD
39
O
Cable Adapter Detect Output to the DisplayPort Source
CAD_A
41
I
Port A Cable Adapter Detect Input
CAD_B
33
I
Port B Cable Adapter Detect Input
LP
30
I
Low Power Select Bar
Priority
29
I
Output Port Priority selection
DPVadj
1
I
DisplayPort Main Link Output Gain Adjustment
CONTROL PINS
SUPPLY and GROUND PINS
2, 8, 14, 17, 23,
34, 48, 54
VDD
VDD*1
38
GND
5, 11, 20, 27,
42, 44, 51
Primary Supply Voltage
HPD and CAD Output Voltage
Ground
Table 1. Control Pin Lookup Table
SIGNAL
LP
Priority
DPVadj
(1)
LEVEL (1)
STATE
H
Normal Mode
L
Low Power Mode
Device is forced into a Low Power state causing the outputs to go to a high impedance
state. All other inputs are ignored
H
Port B has Priority
If both HPD_A and HPD_B are high, Port B will be selected
L
Port A has Priority
If both HPD_A and HPD_B are high, Port A will be selected
4.53 kΩ
Increased Gain
6.49 kΩ
Normal Gain
10 kΩ
Decreased Gain
DESCRIPTION
Normal operational mode for device
Main Link DisplayPort Output will have an increased voltage swing
Main Link DisplayPort Output will have a nominal voltage swing
Main Link DisplayPort Output will have a decreased voltage swing
(H) Logic High; (L) Logic Low
Explanation of the internal switching logic of the SN75DP128A is located in the Application Information section at
the end of the data sheet.
ORDERING INFORMATION (1)
(1)
4
PART NUMBER
PART MARKING
PACKAGE
SN75DP128ARTQR
DP128A
56-pin QFN Reel (large)
SN75DP128ARTQT
DP128A
56-pin QFN Reel (small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
–0.3 to 5.25
V
1.5
V
HPD and CAD I/O
–0.3 to VDD + 0.3
V
Auxiliary I/O
–0.3 to VDD + 0.3
V
Control I/O
–0.3 to VDD + 0.3
V
Auxiliary I/O (AUX +/-, AUX_A +/-, & AUX_B +/-)
±10000
V
All Other Pins
±12000
Supply Voltage Range (2) VDD, VDD*1
Main Link I/O (ML_IN x, ML_A x, ML_B x) Differential Voltage
Voltage Range
Human body model
Electrostatic discharge
(3)
Charged-device model (3)
Machine model
(4)
Continuous power dissipation
(1)
(2)
(3)
(4)
±1000
V
±200
V
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
PACKAGE
PCB JEDEC
STANDARD
TA ≤ 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
Low-K
3623 mW
36.23 mW/°C
1449 mW
High-K
1109 mW
11.03 mW/°C
443.9 mW
56-pin QFN (RTQ)
(1)
TA = 85°C
POWER RATING
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RθJB
Junction-to-board thermal
resistance
RθJC
Junction-to-case thermal
resistance
PD
Device power dissipation
DisplayPort selected
PSD
Device power dissipation under low
LP = 0V, HPD/CAD A and B = 5V; VDD*1 = VDD
power
(1)
MIN
4x4 Thermal vias under powerpad
LP = 5V, ML: VID = 600 mV, 2.7 Gbps PRBS;
AUX: VID = 500 mV, 1Mbps PRBS;
HPD/CAD A and B = 5V; VDD*1 = VDD
TYP
MAX (1)
UNIT
11.03
°C/W
20.4
＝C/W
300
340
mW
85
µW
The maximum rating is simulated under 5.25 V VDD.
RECOMMENDED OPERATING CONDITIONS
VDD
VDD
Supply Voltage
*1
TA
HPD and CAD Output reference voltage
Operating free-air temperature
MIN
NOM
MAX
UNIT
4.5
5
5.25
V
1.62
5.25
V
0
85
°C
0.15
1.4
V
2.7
Gbps
55
Ω
2
V
MAIN LINK DIFFERENTIAL PINS
VID
Peak-to-peak input differential voltage
dR
Data rate
Rt
Termination resistance
VOterm
Output termination voltage
45
0
50
AUXILIARY PINS
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RECOMMENDED OPERATING CONDITIONS (continued)
MIN
VI
Input voltage
dR
Data rate
NOM
0
MAX
3.6
1
UNIT
V
MHz
HPD, CAD, AND CONTROL PINS
VIH
High-level input voltage
2
5.25
V
VIL
Low-level input voltage
0
0.8
V
DEVICE POWER
The SN75DP128A is designed to operate off a single 5V supply.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
65
mA
0.1
4
mA
1
16
µA
*1
IDD
Supply current
LP = 5V, VDD = VDD
ML: VID = 600 mV, 2.7 Gbps PRBS
AUX: VID = 500 mV, 1 Mbps PRBS
HPD/CAD A and B = 5 V
IDD*1
Supply current
VDD*1 = 5.25 V
ISD
Shutdown current
LP = 0 V
HOT PLUG AND CABLE ADAPTER DETECT
The SN75DP128A is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals.
The SN75DP128A has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD
and CAD pins is defined by the voltage level of the VDD*1 pin. Explanation of HPD and the internal logic of the
SN75DP128A is located in the application section at the end of the data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH5
High-level output voltage
IOH = –100 µA,
VDD*1 = 5 V
VOH3.3
High-level output voltage
IOH = –100 µA,
VDD*1 = 3.3 V
VOH2.5
High-level output voltage
IOH = –100 µA,
VOH1.8
High-level output voltage
IOH = –100 µA,
VOL
Low-level output voltage
IOH = 100 µA
IH
High-level input current
VIH = 2.0 V,
IL
Low-level input current
VIL = 0.8 V,
MIN
TYP
MAX
UNIT
4.5
5
V
3
3.3
V
VDD = 2.5 V
2.25
2.5
V
VDD*1 = 1.8 V
1.62
1.8
V
0
0.4
V
VDD = 5.25 V
–10
10
µA
VDD = 5.25 V
–10
10
µA
*1
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPD(CAD)
Propagation delay
VDD*1 = 5 V
5
30
ns
tPD(HPD)
Propagation delay
VDD*1 = 5 V
30
110
ns
*1
tT1(HPD)
HPD logic switch pause time
VDD = 5 V
2
4.7
ms
tT2(HPD)
HPD logic switch time
VDD*1 = 5 V
170
400
ms
tM(HPD)
Minimum output pulse duration
VDD*1 = 5 V
100
tZ(HPD)
Low Power to High-level propagation delay
VDD*1 = 5 V
30
6
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ns
50
110
ns
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HPD Input
HPD Output
DP128A
100KΩ
100KΩ
Figure 1. HPD Test Circuit
0V
VDD
HPD_B
HPD_A
Sink Hot Plug Detect
Pulse Duration
50%
0V
tPD(HPD)
VDD*1
HPD
Minimum
Hot Plug Detect
Output Pulse Duration
50%
tm(HPD)
0V
Figure 2. HPD Timing Diagram #1
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HPD_A & HPD_B
VDD
VDD
Priority
0V
Sink Hot Plug Detect
Timeout
tT2(HPD)
t1(HPD)
VDD*1
HPD
0V
Port B
Selected
Port A
Selected
Figure 3. HPD Timing Diagram #2
HPD_B
0V
VDD
HPD_A
50 %
0V
tZ(HPD)
VDD*1
HPD
50 %
0V
Figure 4. HPD Timing Diagram #3
Auxiliary Pins
The SN75DP128A is designed to support the 1:2 switching of the bidirectional auxiliary signals in both a
differential (DisplayPort) mode and an I2C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimized
based on the status of the selected output port’s CAD pin.
8
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPass1
Maximum passthrough voltage (CAD=1)
VDD = 4.5 V, VI = 5 V, IO = 100 µA
2.4
4.2
V
IOZ
Output current from unselected output
VDD = 5.25 V, VO = 0–3.6 V, VI = 0 V
–5
5
µA
CIO(off)
I/O capacitance when in low power
DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz,
9
12
pF
CIO(on)
DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, CAD =
I/O capacitance when in normal operation
High
18
25
pF
rON(C0-
On resistance AUX+
VDD = 4.5 V, VI = 0 V, IO = 5 mA, CAD = Low
3.5
10
Ω
On resistance AUX-
VDD = 4.5 V, VI = 3.6 V, IO = 5 mA, CAD = Low
3.5
10
Ω
On resistance
VDD = 4.5 V, VI = 0.4 V, IO = 3 mA, CAD = High
10
18
Ω
VAUX+
Voltage on the AUX+
VDD = 4.5 V, 100k pullup on AUX+ to 3.3V ±10%,
HPD_SINK = Low
1.48
1.81
V
VAUX-
Voltage on the AUX-
VDD = 4.5 V, 100k pulldown on AUX- to GND,
HPD_SINK = Low
1.48
1.81
V
AUX+)
rON(C0AUX-)
rON(C1)
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tsk(AUX)
Intra-pair skew
VID = 400 mV, VIC = 2 V
IL(AUX)
Single Line Insertion Loss
VID = 500 mV, VIC = 2 V, F = 1 MHz, CAD = Low
tPLH(AUXC0)
Propagation delay time, low to high
tPHL(AUXC0)
Propagation delay time, high to low
tPLH(AUXC1)
tPHL(AUXC1)
TYP MAX
350
UNIT
400
ps
0.4
dB
CAD = Low, F = 1 MHz
3
ns
CAD = Low, F = 1 MHz
3
ns
Propagation delay time, low to high
CAD = High, F = 100 kHz
5
ns
Propagation delay time, high to low
CAD = High, F = 100 kHz
5
ns
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IO = 5 mA
VI = 0 V
AUX+
IO = 5 mA
VI = 3.6 V
AUX-
SN75DP128A
CAD = 0
A
Sink
Connector
Source
Connector
GND
2.5 - 3.3 V
100 KΩ
1 MΩ
75-200 nF
75-200 nF
AUX+
50 Ω
50 Ω
0-2 V
0-2 V
50 Ω
AUX-
50 Ω
75-200 nF
75-200 nF
1 MΩ
SN75DP128A
100 KΩ
CAD = 0
B
3.3 V
GND
Figure 5. Auxiliary Channel Test Circuit (CAD = LOW)
3.3 V
3.3 V
SN75DP128A
2 KΩ
10 pF
AUX
+ or -
100 KΩ
50 pF
CAD = 1
Figure 6. Auxiliary Channel Test Circuit (CAD = HIGH)
2. 2 V
50 %
1. 8 V
Tsk(AUX)
Figure 7. Auxiliary Channel Skew Measurement
10
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2.2V
AUX Input
1.8V
Differential
0V
AUX Input
tPHL(AUXC0)
tPLH(AUXC0)
Differential
AUX Output 0 V
Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW)
3.6 V
AUX
Input
+ or -
1.8 V
0V
tPHL(AUXC1)
tPLH(AUXC1)
3.6 V
AUX
Output
+ or -
1.8 V
0V
Figure 9. Auxiliary Channel Delay Measurement (CAD = HIGH)
Main Link Pins
The SN75DP128A is designed to support the 1:2 switching of DisplayPort’s high speed differential main link. The
main link I/O of the SN75DP128A are designed to track the magnitude and frequency characteristics of the input
waveform and replicate them on the output. A feature has also been incorporated in the SN75DP128A to either
increase or decrease the output amplitude via the resistor connected between the DPVADJ pin and ground.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
ΔVI/O(2)
ΔVI/O(3)
ΔVI/O(4)
Difference between input and output)
voltages
(VOD – VID)
ΔVI/O(6)
RINT
Input termination impedance
VIterm
Input termination voltage
TEST CONDITIONS
MIN
TYP
MAX
VID = 200 mV, DPVadj = 6.5 kΩ
0
30
60
mV
VID = 300 mV, DPVadj = 6.5 kΩ
–24
11
36
mV
VID = 400 mV, DPVadj = 6.5 kΩ
–45
–15
15
mV
VID = 600 mV, DPVadj = 6.5 kΩ
–87
–47
–22
mV
45
50
55
Ω
2
V
0
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UNIT
11
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
115
160
ps
240
280
ps
F= 1 MHz, VID = 400 mV
20
ps
F= 1 MHz, VID = 400 mV
40
ps
35
ps
tR/F(DP)
Output edge rate (20%–80%)
Input edge rate = 80 ps (20%–80%)
tPD
Propagation delay time
F= 1 MHz, VID = 400 mV
tSK(1)
Intra-pair skew
tSK(2)
Inter-pair skew
tDPJIT(PP)
Peak-to-peak output residual jitter
dR = 2.7 Gbps, VID = 400 mV, PRBS 27-1
200
VIterm
25
0V to 2V
50 W
50 W
50 W
D+
V
VD+ ID
50 W
0.5 pF
Receiver
Driver
D-
Y
100 nF
VY
Z
VD-
100 nF
VZ
VOD = VY - VZ
VOC = (VY + VZ)
2
VID = VD+ - VDVICM = (VD+ + VD- )
2
Figure 10. Main Link Test Circuit
tR/FDP
Input
DVI/O
Output
Input Edge Rate
20% to 80%
80 ps
DVI/O
Figure 11. Main Link ΔVI/O and Edge Rate Measurements
12
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ML_IN x+
ML_IN x-
Main Link
Input
0V
tPD(ML)
tPD(ML)
Main Link
Output
0V
Figure 12. Main Link Delay Measurements
2.2 V
ML x+
50 %
ML x-
1.8 V
Tsk1
Tsk2
2.2 V
ML y+
50 %
ML y-
1.8 V
Tsk1
Figure 13. Main Link Skew Measurements
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SN75DP128A
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TYPICAL CHARACTERISTICS
INPUT/OUTPUT VOLTAGE
vs
RESISTANCE
INPUT/OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
150
80
Temp = 25oC
VID = 200 mV
100
DVI/O − Input/Output Voltage − mV
DVI\O − Input/Output Voltage − mV
70
VID = 200 mV
VID = 300 mV
50
VID = 400 mV
0
−50
VID = 600 mV
−100
Temp = 25oC
2k
4k
VID = 300 mV
50
40
VID = 400 mV
30
20
10
VID = 600 mV
0
-10
-20
4.4
−150
0
60
6k
8k
10k
12k
14k
4.6
DPVadj − Resistance − W
Figure 14.
Figure 15.
INPUT EDGE RATE
vs
OUTPUT EDGE RATE
POWER DISSIPATION
vs
DATA RATE
200
160
290
o
VDD = 5 V, 25 C
140
120
o
100
VDD = 4.5 V, 0 C
80
60
40
20
0
0
280
270
85oC
260
250
240
o
0C
25oC
230
220
210
200
50
100
150
Input Edge Rate 20% - 80% (ps)
200
0
Figure 16.
14
5.4
300
VDD = 5.25 V, 85oC
PD − Power Dissipation − mW
Output Edge Rate 20% - 80% (ps)
180
4.8
5
5.2
VDD − Supply Voltage − V
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500M
1G
1.5G
2G
2.5G
3G
Data Rate − Bps
Figure 17.
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SN75DP128A
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APPLICATION INFORMATION
SWITCHING LOGIC
The switching logic of the SN75DP128A is tied to the state of the HPD input pins as well as the priority pin and
low power pin. When both HPD_A and HPD_B input pins are LOW, the SN75DP128A enters the low power
state. In this state the outputs are high impedance, and the device is shutdown to optimize power conservation.
When either HPD_A or HPD_B goes high, the device enters the normal operational state, and the port
associated with the HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH, the port selection
is determined by the state of the priority pin.
Several key factors were taken into consideration with this digital logic implementation of channel selection as
well as HPD repeating. This logic has been divided into the following four scenarios.
1. Low power state to active state. There are two possible cases for this scenario depending on the state of the
low power pin:
– Case one: In this case both HPD inputs are initially LOW and the low power pin is also LOW. In this initial
state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device
remains in the low power mode with both the main link and auxiliary I/O in a high impedance state.
However, the port associated with the HPD input that went HIGH is still selected and the HPD output to
the source is enabled and follows the logic state of the input HPD (see Figure 18). The state of the
Priority pin has no effect in this scenario as only one HPD input port is active.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
HI-Z
Channel A
0
1
HI-Z
Channel B
0
Figure 18.
– Case two: In this case both HPD inputs are initially LOW and the low power pin is HIGH. In this initial
state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device
comes out of the low power mode and enters active mode enabling the main link and auxiliary I/O. The
port associated with the HPD input that went HIGH is selected and the HPD output to the source is
enabled and follows the logic state of the input HPD (see Figure 19). This is specified as tZ(HPD). Again,the
state of the Priority pin has no effect in this scenario as only one HPD input port is active.
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1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
HI-Z
Channel A
DATA
0
1
HI-Z
Channel B
0
Figure 19.
2. HPD Changes on the selected port. There are also two possible starting cases for this scenario:
– Case one: In this case only one HPD input is initially HIGH. The HPD output logic state follows the state
of the HPD input. If the HPD input pulses LOW, as may be the case if the Sink device is requesting an
interrupt, the HPD output to the source also pulses LOW for the same duration of time with a slight delay
(see Figure 20). The delay of this signal through the SN75DP128A is specified as tPD(HPD). If the duration
of the LOW pulse is less then tM(HPD), it may not be accurately repeated to the source. If the duration of
the LOW pulse exceeds tT2(HPD), the device assumes that an unplug event has occurred and enters the
low power state (see Figure 21). Once the HPD input goes high again, the device returns to the active
state as indicated in scenario 1. The state of the Priority pin has no effect in this scenario as only one
HPD input port is active.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 20.
16
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1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
HI-Z
0
1
HI-Z
Channel B
0
Figure 21.
– Case two: In this case both HPD inputs are initially HIGH and the selected port has been determined by
the state of the priority pin. The HPD output logic state follows the state of the selected HPD input. If the
HPD input pulses LOW, the HPD output to the source also pulses LOW for the same duration of time,
again with a slight delay (see Figure 22). If the duration of the LOW pulse exceeds tT2(HPD), the device
assumes that an unplug event has occurred and the other port is selected (see Figure 23). The case in
which the previously selected port with priority goes high again is covered in scenario 3.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 22.
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SN75DP128A
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1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
Channel A
DATA
HI-Z
HI-Z
DATA
0
1
Channel B
0
Figure 23.
3. One channel becomes active while other channel is already selected. There are also two possible starting
cases for this scenario:
– Case one: In this case the HPD input that is initially HIGH is from the port that has priority. Since the port
with priority is already selected, any activity on the HPD input from the other port doesnot have any effect
on the switch whatsoever (see Figure 24).
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 24.
– Case two: In this case the HPD input that is initially HIGH is not the port with priority. When the HPD input
of the port that has priority goes high, the HPD output is forced LOW for some time in order to simulate
an unplug event to the source device. The duration of this LOW output is defined as tT2(HPD). If the HPD
input of the port with priority pulses LOW for a short duration while the tT2(HPD) timer is counting down, the
timer is reset. Once this time has passed the switch switches to the port with priority and the output HPD
18
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once again follows the state of the newly selected channel’s HPD input (see Figure 25).
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
Channel A
DATA
HI-Z
HI-Z
DATA
0
1
Channel B
0
Figure 25.
4. 4. Priority pin is toggled. There are also two possible starting cases for this scenario:
– Case one: In this case only one HPD input is HIGH. A port whose HPD input is LOW cannot be selected.
In this case, the state of the priority pin has no effect on the switch (see Figure 26).
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 26.
– Case two: In this case both HPD inputs are HIGH. Changing the state of the priority pin when both HPD
inputs are high forces the device to switch which channel is selected. When a state change is detected on
the priority pin, the device waits for a short period of time tT1(HPD) before responding (see Figure 27). The
purpose for this pause is to allow for the priority signal to settle and also to allow the device to ignore
potential glitches on the priority pin. Once tT1(HPD) has expired, the HPD output is forced LOW for tT2(HPD)
and the device follows the chain of events outlined in scenario 3 case 2.
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SN75DP128A
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1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
Channel A
DATA
HI-Z
HI-Z
DATA
0
1
Channel B
0
Figure 27.
20
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Product Folder Link(s): SN75DP128A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75DP128ARTQR
ACTIVE
QFN
RTQ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
DP128A
SN75DP128ARTQT
ACTIVE
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
DP128A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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