SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
DisplayPort to TMDS Translator
FEATURES
APPLICATIONS
•
•
1
•
•
•
•
•
•
•
DisplayPort Physical Layer Input Port to TMDS
Physical Layer Output Port
Integrated TMDS Level Translator With
Receiver Equalization
Supports Data Rates up to 2.5 Gbps
Integrated I2C Logic Block for DVI / HDMI
Connector Recognition
Integrated Active I2C Buffer
Enhanced ESD: 12 kV on all Pins
Enhanced Commercial Temperature Range:
0°C to 85°C
36 Pin 6 × 6 QFN Package
Personal Computer Market
– DP/TMDS Hardware Key (Dongle)
– Desktop PC
– Notebook PC
– Docking Station
– Standalone Video Card
DESCRIPTION
The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output.
The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High
Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of
2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive
scan).
An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and
interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design
margin within the source system for DVI / HDMI compliance testing.
A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of
the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally
supporting HDMI content.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION
GPU
DP++
SN75DP129 TMDS
TMDS Buffer
DVI or HDMI
Compliant
Monitor or HDTV
Dongle
Computer Notebook
Docking Station
GPU—Graphics Processing Unit
DP++—Dual-Mode DisplayPort
TMDS—Transition-Minimized Differential Signaling
DVI—Digital Visual Interface
HDMI—High Definition Multimedia Interface
2
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
GND
TMDS_CLK(n)
TMDS_CLK(p)
VCC
TMDS_0(n)
TMDS_0(p)
GND
TMDS_1(n)
TMDS_1(p)
INTERNAL DATA CONNECTION DIAGRAM
SN75DP129
VCC
VCC
TMDS_2(n)
SCL
TMDS_2(p)
SDA
VSadj
HPD_IN
2
I C
Slave
2
I C _EN
VDD
LP
HPD_OUT
ML_IN 0(p)
AUX_I2C(n)
1
ML_IN 0(n)
AUX_I2C(p)
1
GND
(1)
VCC
ML_IN 3(n)
ML_IN 3(p)
GND
ML_IN 2(n)
ML_IN 2(p)
VCC
ML_IN 1(n)
ML_IN 1(p)
GND
I2C bus data (n-SDA) and clock (p-SCL) lines.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
3
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
PIN CONFIGURATION
TMDS_CLK(p)
TMDS_CLK(n)
GND
TMDS_0(p)
TMDS_0(n)
VCC
TMDS_1(p)
TMDS_1(n)
GND
RHH PACKAGE
(Top View)
27 26 25 24 23 22 21 20 19
VCC
28
18
VCC
TMDS_2(n)
TMDS_2(p)
VSadj
I2C_EN
29
17
30
16
SCL
SDA
HPD_IN
LP
ML_IN 0(p)
ML_IN 0(n)
33
13
34
12
35
11
VDD
HPD_OUT
1
AUX_I2C(n)
1
AUX_I2C(p)
GND
36
10
GND
15
31
5
6
7
8
9
VCC
VCC
ML_IN 2(p)
4
14
ML_IN 3(n)
3
GND
ML_IN 3(p)
2
ML_IN 1(n)
ML_IN 1(p)
1
ML_IN 2(n)
SN75DP129
32
I2C bus data (n-SDA) and clock (p-SCL) lines.
(1)
TERMINAL FUNCTIONS
TERMINAL
NO. (1)
NAME
AUX_I2C (2)
GND
11(p), 12(n)
I/O
I/O
6, 10, 19, 25, 36
DESCRIPTION
TYPE
Source Side Bidirectional DisplayPort Auxiliary Data Line
DDC LINK (Source)
Ground
Ground
HPD_IN
15
I
Hot Plug Detect (HPD) Input
Hot Plug Detect
HPD_OUT
13
O
Hot Plug Detect (HPD) Output
Hot Plug Detect
2
I2C_EN
LP
32
I
Internal I C register enable, used for HDMI / DVI connector
differentiation
Control
33
I
Low Power Select Bar
Control
ML_IN 0
34(p), 35(n)
I
DisplayPort Main Link Channel 0 Differential Input
Main Link Input Pins
ML_IN 1
1(p), 2(n)
I
DisplayPort Main Link Channel 1 Differential Input
Main Link Input Pins
ML_IN 2
4(p), 5(n)
I
DisplayPort Main Link Channel 2 Differential Input
Main Link Input Pins
ML_IN 3
7(p), 8(n)
I
DisplayPort Main Link Channel 3 Differential Input
Main Link Input Pins
TMDS_2
30(p), 29(n)
O
TMDS Data 2 Differential Output
Main Link Output
TMDS_1
27(p), 26(n)
O
TMDS Data 1 Differential Output
Main Link Output
TMDS_0
24(p), 23(n)
O
TMDS Data 0 Differential Output
Main Link Output
TMDS_CLK
21(p), 20(n)
O
TMDS Data Clock Differential Output
Main Link Output
2
SCL
17
I/O
TMDS Port Bidirectional I C Clock Line
DDC Link (Sink)
SDA
16
I/O
TMDS Port Bidirectional I2C Data Line
DDC Link (Sink)
VCC
3, 9, 18, 22, 28
3.3 V Supply
Voltage Supply
(1)
(2)
4
(p) Positive; (n) Negative
I2C bus data (n-SDA) and clock (p-SCL) lines.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O
NO. (1)
VDD
14
VSadj
31
I
DESCRIPTION
TYPE
HPD Supply
Voltage Supply
TMDS-Compliant Voltage Swing Control
Reference
Input/Output Equivalent Circuits
VTERM
VCC
VTERM
50 W
50 W
–
+
Figure 1. DisplayPort Input Stage
Y
Z
10 mA
Figure 2. TMDS Output Stage
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
5
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
2
I C_EN
LP
Figure 3. HPD and Control Input Stage
VDD
HPD_OUT
Figure 4. HPD Output Stage
SCL
SDA
AUX+/–
400 W
VOL
Figure 5. I2C Input and Output Stage
6
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
Table 1. Control Pin Lookup Table (1)
SIGNAL
LEVEL
STATE
H
Normal Mode
L
Low Power Mode
H
HDMI
L
DVI
4.65 kΩ
Compliant Voltage
Swing
LP
2
I C_EN
VSadj
(1)
DESCRIPTION
Normal operational mode for device
Device is forced into a Low Power state causing the outputs to go to a high impedance
state. All other inputs are ignored.
Internal I2C register is active and readable, indicating the connector in use is
HDMI-compliant.
Internal I2C register is disabled and unreadable, indicating the connector in use is
DVI-compliant.
Driver output voltage swing precision control to aid with system compliance.
(H) Logic High; (L) Logic Low
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
SN75DP129RHHR
DP129
36-pin QFN Reel (large)
SN75DP129RHHT
DP129
36-pin QFN Reel (small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
(2)
Supply voltage range
VALUE
UNIT
VCC
–0.3 to 3.6
V
VDD
–0.3 to 3.6
V
1.5
V
–0.3 to 4
V
HPD I/O
–0.3 to 5.5
V
Auxiliary I/O
–0.3 to 5.5
V
Control I/O
–0.3 to 5.5
V
Main link I/O (ML_IN x, DP_SINK x) differential voltage
TMDS I/O
Voltage range
Human body model
Electrostatic discharge
(3)
±12000
V
Charged-device model (4)
±1000
V
Machine model (5)
±200
V
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
See Dissipation Ratings Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
PACKAGE
36-pin QFN (RHH)
(1)
PCB JEDEC
STANDARD
TA ≤ 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
Low-K
1398 mW
13.98 mW/°C
559 mW
High-K
2941 mW
29.41 mW/°C
1176 mW
TA = 85°C
POWER RATING
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
7
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJB
Junction-to-board thermal resistance
9.44 (1)
°C/W
RθJC
Junction-to-case thermal resistance
24.74
°C/W
PD
Device power dissipation (2)
LP = 3.3 V, ML: VID = 500 mV, 2.5 Gbps
PRBS;
I2C: VID = 3.3 V, 100 Kbps PRBS; HPD = 5 V
PSD
Device power dissipation under low power
LP = 0 V
(1)
(2)
380
490
mW
5
20
µW
The maximum rating is simulated under 3.6 V VCC and VDD unless otherwise noted.
Power disipation is the sum of the power consumption from the VCC and VDD pins, plus the 132 mW of power from the AVCC (Receiver
Termination Supply).
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
UNIT
V
VDD
Supply voltage
1.65
3.6
V
TA
Operating free-air temperature
0
85
°C
0.15
1.40
V
2.5
Gbps
3.6
V
2.5
Gbps
55
Ω
5.5
V
100
kHz
MAIN LINK DIFFERENTIAL INPUT PINS
VID
Peak-to-peak input differential voltage
dR
Data rate
TMDS DIFFERENTIAL OUTPUT PINS
AVCC
TMDS output termination voltage
dR
Data rate
Rt
Termination resistance
3
3.3
45
50
AUXILIARY AND I2C PINS
VI
Input voltage
dR(I2C)
I2C data rate
0
HPD AND CONTROL PINS
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
Device Power
The SN75DP129 is designed to operate from one or two supply voltages, depending on the implementation of
the integrated Hot Plug Detect (HPD) level translator. The TMDS level translator is powered from a single 3.3-V
supply. The HPD translator is powered using the VDD pin and its voltage can range from 1.8 V to 3.3 V. This
voltage determines the HIGH-level output voltage of the HPD_OUT pin.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
Supply current
IDD
Supply current
ISD
Shutdown current
8
TEST CONDITIONS
LP = 3.6 V, VCC = VDD,
ML: VID = 500 mV, 2.7 Gbps PRBS
AUX: VI = 3.3 V, 100 kHz PRBS
HPD: HPD_IN = 5 V
LP = 0 V
Submit Documentation Feedback
MIN
TYP
MAX
UNIT
50
75
112
mA
1
2
mA
1
5
µA
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
Hot Plug and Cable Adapter Detect
The SN75DP129 has a built-in level shifter for the HPD outputs. The output voltage level of the HPD pin is
defined by the voltage level of the VDD pin.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH2.5
MIN
IOH = –100 µA, VDD×1 = 3.3 V
VOH3.3
High-level output voltage
VOH1.8
TYP
MAX
UNIT
3
3.3
V
IOH = –100 A, VDD×1 = 2.5 V
2.25
2.5
V
IOH = –100 A, VDD×1 = 1.8 V
1.62
1.8
V
VOL
Low-level output voltage
IOH = 100 µA
0
0.4
V
IH
High-level input current
VIH = 2.0 V, VDD = 3.6 V
–10
10
µA
IL
Low-level input current
VIL = 0.8 V, VDD = 3.6 V
–10
10
µA
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPD(HPD)
TEST CONDITIONS
Propagation delay
MIN
VDD = 3.6 V
HPD Input
5
TYP
MAX
30
UNIT
ns
HPD Output
DP129
100 kW
100 kW
Figure 6. HPD Test Circuit
5V
HPD_IN
50%
0V
tPD(HPD)
VDD
HPD_OUT
50%
0V
Figure 7. HPD Timing Diagram
AUX / I2C Pins
The SN75DP129 utilizes an active I2C repeater. The repeater isolates the parasitic effects of the system to aid
with system level compliance.
In addition to the I2C repeater, the SN75DP129 supports the connector detection I2C register. This register is
enabled using the I2C_EN pin. When active, an internal memory register is readable using the AUX_I2C pins.
This I2C register block functionality is described in the APPLICATION INFORMATION section.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
9
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
IL
Low input current
Ilkg(AUX)
Input leakage current
TEST CONDITIONS
AUX_I2C pins
2
MIN
TYP MAX
VCC = 3.6 V, VI = 0 V
–10
10
µA
VCC = 3.6 V, VI = 3.6 V
–10
10
µA
DC bias = 1.65 V, AC = 2.1 Vp-p, f = 100 kHz
UNIT
CIO(AUX)
Input/output capacitance
AUX_I C pins
15
pF
VIH(AUX)
High-level input voltage
AUX_I2C pins
1.6
5.5
V
VIL(AUX)
Low-level input voltage
AUX_I2C pins
–0.2
0.4
V
0.5
0.6
V
–10
10
µA
15
pF
2
VOL(AUX)
Low-level output voltage
AUX_I C pins
Ilkg(I2C)
Input leakage current
I2C SDA/SCL pins VCC = 3.6 V, VI = 4.95 V
IO = 4 mA
CIO(I2C)
Input/output capacitance
I2C SDA/SCL pins DC bias = 2.5 V, AC = 3.5 Vp-p, f = 100 kHz
2
VIH(I2C)
High-level input voltage
I C SDA/SCL pins
2.1
5.5
V
VIL(I2C)
Low-level input voltage
I2C SDA/SCL pins
–0.2
1.5
V
VOL(I2C)
Low-level output voltage
I2C SDA/SCL pins IO = 4 mA
0.2
V
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH1
Propagation delay time, low to high
Source to Sink
204
459
ns
tPHL1
Propagation delay time, high to low
Source to Sink
35
200
ns
tPLH2
Propagation delay time, low to high
Sink to Source
80
251
ns
tPHL2
Propagation delay time, high to low
Sink to Source
35
200
ns
tf1
Output signal fall time
Sink Side
20
72
ns
tf2
Output signal fall time
Source Side
20
72
ns
fSCL
SCL clock frequency for internal register
Source Side
100
kHz
tW(L)
Clock LOW period for I2C register
Source Side
4.7
µs
tW(H)
Clock HIGH period for internal register
Source Side
4.0
µs
tSU1
Internal register setup time, SDA to SCL
Source Side
250
ns
th(1)
Internal register hold time, SCL to SDA
Source Side
0
µs
t(buf)
Internal register bus free time between STOP and START
Source Side
4.7
µs
tsu(2)
Internal register setup time, SCL to START
Source Side
4.7
µs
th(2)
Internal register hold time, START to SCL
Source Side
4.0
µs
tsu(3)
Internal register hold time, SCL to STOP
Source Side
4.0
µs
3.3 V
VCC
R L = 2 kW
PULSE
GENERATOR
D.U.T.
CL = 100 pF
RT
VIN
VOUT
Figure 8. Source Side Test Circuit (AUX_I2C)
10
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
5V
VCC
R L = 2 kW
PULSE
GENERATOR
D.U.T.
CL = 400 pF
RT
VIN
VOUT
Figure 9. Sink Side Test Circuit (SCL, SDA)
5V
I2C_SCL
I2C_SDA
1.6 V
0.1 V
Input
tPHL2
tPLH2
3.3 V
80%
AUX_I2C (p)
AUX_I2C (n)
Output
1.6 V
20%
VOL
tf2
Figure 10. Source Side Output AC Measurements
3.3 V
AUX_I2C (p)
AUX_I2C (n)
Input
1.6 V
0.1 V
tPHL1
5V
I2C_SCL
I2C_SDA
80%
1.6 V
20%
Output
VOL
tf1
Figure 11. Sink Side Output AC Measurements
3.3 V
AUX_I2C (p)
AUX_I2C (n)
Input
0.5 V
tPLH1
I2C_SCL
I2C_SDA
Output
5V
1.6 V
Figure 12. Sink Side Output AC Measurements (continued)
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
11
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
TMDS and Main Link Pins
The main link inputs are designed to be compliant with the DisplayPort 1.1 specification. The TMDS outputs of
the SN75DP129 are designed to be compliant with the Digital Visual Interface 1.0 (DVI) and High Definition
Multimedia Interface 1.3 (HDMI) specifications. The differential output voltage swing can be fine-tuned with the
VSadj (TMDS-compliant Voltage Swing Control) resistor.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Single-ended HIGH level output voltage
AVCC–10
AVCC+10
mV
VOL
Single-ended LOW level output voltage
AVCC–600
AVCC–400
mV
VSWING
Single-ended output voltage swing
400
600
mV
VOC(SS)
Change in steady-state common-mode
output voltage between logic states
–5
5
mV
VOD(PP)
Peak-to-peak output differential voltage
800
1200
mV
AVCC–10
AVCC+10
mV
10
µA
15
mA
55
Ω
2
V
AVCC = 3.3 V, RT = 50 Ω
V(O)SBY
Single-ended standby output voltage
AVCC = 3.3 V, RT = 50 Ω,
LP = 0
I(O)OFF
Single-ended power down output current
0 V ≤ VCC ≥ 1.5 V, AVCC = 3.3 V,
RT = 50 Ω
–10
IOS
Short circuit output current
VID = 500 mV
–15
RINT
Input termination impedance
Vterm
Input termination voltage
45
50
1
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time
250
350
600
ps
tPHL
Propagation delay time
250
350
600
ps
tR
Rise time
60
90
140
ps
tF
Fall time
60
90
140
ps
tSK(P)
Pulse skew
8
15
ps
tSK(D)
Intra-pair skew
20
40
ps
tSK(O)
Inter-pair skew
20
65
ps
tJITD(PP)
Peak-to-peak output residual data jitter
AVCC = 3.3 V, RT = 50 Ω, dR = 2.5 Gbps
14
50
ps
tJITC(PP)
Peak-to-peak output residual clock jitter
AVCC = 3.3 V, RT = 50 Ω, f = 250 MHz
8
30
ps
12
AVCC = 3.3 V, RT = 50 Ω, f = 1 MHz
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
VTERM
3.3V
50 Ω
50 Ω
50 Ω
50 Ω
0.5 pF
D+
100 pF
VD+
Receiver
VID
D-
100 pF
V D-
Y
Driver
VY
Z
VOD = VY - VZ
VOC = (VY + VZ)
VID = VD+ - VDVICM = (VD+ + VD-)
2
VZ
2
Figure 13. TMDS Main Link Test Circuit
2.2 V
VTERM
VID
1.8 V
VID+
VID(pp)
0V
tPHL
80%
0V
20%
tf
VID-
tPLH
80%
VOD(pp)
VOD
20%
tr
Figure 14. TMDS Main Link Timing Measurements
VOC
ΔVOC (SS)
Figure 15. TMDS Main Link Common Mode Measurements
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
13
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
Avcc (4)
RT
Data +
Video
Data Patterm
Generator
800 mVpp or
1200 mVpp
Differential
Coax
Coax
SMA
SMA
RX
+EQ
SMA
(1)
FR 4 PCB trace
&
AC coupling Caps
Clk +
Clk -
Coax
Coax
SMA
SN 75 DP 129
Coax
Coax
FR 4 PCB trace
AVcc
RT
SMA
RX
+EQ
(5)
OUT
SMA
SMA
RT
Jitter Test
Instrument (2,3)
RT
Coax
OUT
SMA
Coax
Jitter Test
Instrument (2,3)
TTP 1
TTP 2
TTP 4
TTP 3
(1)
The FR4 trance between TTP1 and TTP2 is designed to emulate 8 inches of FR4, a connector, and another 8 inches
if FR4.
(2)
All jitter is measured at a BER of 10–12
(3)
Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.
(4)
AVCC = 3.3 V
(5)
RT = 50 Ω
Figure 16. TMDS Jitter Measurements
50 W
I OS
Driver
50 W
+ 0 V or 3.6 V
-
Figure 17. TMDS Main Link Short Circuit Output Circuit
14
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS
Power disipation is the sum of the power consumption from the VCC and VDD pins, plus the 132 mW of power from the
AVCC (Receiver Termination Supply).
POWER DISSIPATION
vs
DATA RATE
PEAK-TO-PEAK RESIDUAL DATA JITTER (at 2.5 Gbps)
vs
SUPPLY VOLTAGE
15
Peak-to-Peak Residual Data Jitter at 2.5 Gbps − ps
400
398
TA = 85°C
P − Power Dissipation − mW
396
394
392
TA = 25°C
390
388
TA = 0°C
386
384
382
380
0
500
1000
1500
2000
2500
TA = 85°C
14
TA = 25°C
13
TA = 0°C
12
2.7
3000
3.0
Data Rate − Mbps
G001
3.6
Figure 18.
Figure 19.
PEAK-TO-PEAK RESIDUAL DATA JITTER
vs
DATA RATE
GAIN
vs
FREQUENCY
20
3.9
G002
20
18
10
VID = 600 mV
16
0
14
−10
12
Gain − dB
Peak-to-Peak Residual Data Jitter − ps
3.3
VSS − Supply Voltage − V
VID = 400 mV
10
8
VID = 500 mV
−20
−30
6
−40
4
−50
2
0
−60
0
500
1000
1500
2000
2500
3000
0
2
Data Rate − Mbps
4
6
8
10
12
14
16
18
20
f − Frequency − GHz
G003
Figure 20.
G004
Figure 21.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
15
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)
Power disipation is the sum of the power consumption from the VCC and VDD pins, plus the 132 mW of power from the
AVCC (Receiver Termination Supply).
PEAK-TO-PEAK DROPOUT VOLTAGE
vs
RESISTANCE
VOD - Peak-to-Peak Dropout Voltage - mV
1400
1300
VCC = 3.3 V
1200
1100
1000
VCC = 3.6 V
VCC = 3 V
900
800
700
600
3.0E+03
4.0E+03
5.0E+03
6.0E+03
VSadj - Resistance - W
7.0E+03
Figure 22.
16
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
APPLICATION INFORMATION
I2C INTERFACE NOTES
The I2C interface can access the internal memory of the SN75DP129. I2C is a two-wire serial interface developed
by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line
(SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled
high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master
device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for
generating the SCL signal and device addresses. The master also generates specific conditions that indicate the
START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the
master device. The SN75DP129 works as a slave and supports the standard mode transfer (100 kbps) as
defined in the I2C-Bus Specification.
The basic I2C start and stop access cycles are shown in Figure 23.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SDA
SCL
SCL
Start
Condition
Stop
Condition
Figure 23. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
•
•
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line the SCL line is high, as shown in Figure 25. All I2C-compliant devices
should recognize a start condition.
The master generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on
the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 24). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
The master generates further SCL cycles to transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 26).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 26). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition ,followed by a
matching address.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
17
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 24. I2C Bit Transfer
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
Clock Pulse for
Acknowledgement
START
Condition
Figure 25. I2C Acknowledge
SCL
SDA
Acknowledge
Slave Address
Acknowledge
Data
Figure 26. I2C Address and Data Cycles
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 27 and Figure 28.
See the Reading from the SN75DP129, an example section for more information.
Figure 27. I2C Read Cycle
18
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
Figure 28. Multiple Byte Read Transfer
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7 bit address is
factory preset to 1000000. Table 2 lists the calls that the SN75DP129 will respond to.
Table 2. SN75DP129 Slave Address
READ/WRITE
BIT
FIXED ADDRESS
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (R/W)
1
0
0
0
0
0
0
1
Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address)
The SN75DP129 operates using a multiple byte transfer protocol similar to Figure 28. The internal memory of the
SN75DP129 contains the phrase DP-HDMI ADAPTOR converted to ASCII characters. The internal
memory address registers and the corresponding values can be found in Table 3.
During a read cycle, the SN75DP129 sends the data (within its selected sub-address) in a single transfer to the
master device requesting the information. See the Reading from the SN75DP129, an Example section of this
data sheet for the proper procedure.
Table 3. SN75DP129 Sink Port and Source Plug-In Status Registers Selection
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Data
44
50
2D
48
44
4D
49
20
41
44
41
50
54
4F
52
04
FF
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
19
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
READING FROM THE SN75DP129, AN EXAMPLE
The read operation consists of several steps. The I2C master begins the communication with the transmission of
the start sequence, followed by the slave address of the SN75DP129 and logic address of 00h. The SN75DP129
acknowledges it’s presence to the master and begins to transmit the memory registers contents . After each byte
is transferred, the SN75DP129 waits for an acknowledge (ACK) or a not-acknowledge (NACK) from the master.
If an ACK is received, the next byte of data is transmitted. If a NACK is received, the data transmission sequence
is expected to end and the master should send the stop command.
The SN75DP129 continues to send data until the master fails to acknowledge each byte transmission. If an ACK
is received after the transmission of byte 0x0F, the SN75DP129 transmits byte 0x10 and continues to transmit
byte 0x10 for all further ACK’s until a NACK is received.
SN75DP129 Read Phase
Step 1 (1)
0
I2C Start (Master)
S
(1)
The SN75DP129 also supports an accelerated read mode in which steps 1 through 6 can be skipped.
Step 2
7
6
5
4
3
2
1
0
I2C General Address Write (Master)
1
0
0
0
0
0
0
0
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
7
6
5
4
3
2
1
0
I C Logic Address (Master)
1
0
0
0
0
0
0
0
Step 5
9
2
2
I C Acknowledge (Slave)
A
Step 6
0
2
I C Stop (Master)
P
Step 7
0
I2C Start (Master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General Address Read (Master)
1
0
0
0
0
0
0
1
Step 9
9
I2C Acknowledge (Slave)
A
Step 10
I2C Read Data (Slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the Logic values Contained in the Sink Port Register
Step 11
9
2
I C Not-Acknowledge (Master)
X
Where X is an A (Acknowledge) or A (Not-Acknowledge)
An A causes the pointer to increment and step 10 is repeated.
An A causes the slave to stop transmitting and proceeds to step 12.
Step 12
0
I2C Stop (Master)
P
20
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
SN75DP129
www.ti.com
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
Revision History
Changes from Original (January 2008) to Revision A .................................................................................................... Page
•
•
•
•
•
•
•
•
Changed device power dissipation from 250 mW typ to 380 mW typ................................................................................... 8
Changed device power dissipation from 400 mW max to 490 mW max............................................................................... 8
Changed propagation delay time, high to low, sink to source from 140 ns max to 200 ns max ......................................... 10
Changed tPHL1 to tPLH1 in Figure 12 ...................................................................................................................................... 11
Changed tPHL propagation delay time from 800 ps max to 600 ps max .............................................................................. 12
Changed tJITD(PP) peak-to-peak output residual data jitter from 20 ps typ to 14 ps typ........................................................ 12
Changed tJITC(PP) peak-to-peak output residual clock jitter from 10 ps typ to 8 ps typ......................................................... 12
Added peak-to-peak dropout voltage vs resistance curves................................................................................................. 16
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75DP129RHHR
ACTIVE
VQFN
RHH
36
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
DP129
SN75DP129RHHT
ACTIVE
VQFN
RHH
36
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
DP129
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
