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SN75LVDS82
SLLS259J – NOVEMBER 1996 – REVISED OCTOBER 2016
SN75LVDS82 FlatLink™ Receiver
1 Features
3 Description
•
The SN75LVDS82 FlatLink™ receiver contains four
serial-in, 7-bit parallel-out shift registers, a 7× clock
synthesizer, and five low-voltage differential signaling
(LVDS) line receivers in a single integrated circuit.
1
•
•
•
•
•
•
•
•
•
•
4:28 Data Channel Expansion at up to
1904 Mbps Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
Four Data Channels and Clock Low-Voltage
Differential Channels In and 28 Data and
Clock Low-Voltage TTL Channels Out
Operates From a Single 3.3-V Supply With
250 mW (Typical)
5-V Tolerant SHTDN Input
Falling Clock-Edge-Triggered Outputs
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
Consumes Less Than 1 mW When Disabled
Pixel Clock Frequency Range of 31 MHz to
68 MHz
No External Components Required for PLL
Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
2 Applications
•
•
•
•
Printers
Appliances With an LCD
Digital Cameras
Laptop and PC Displays Industrial PC, Laptop,
and other Factory Automation Displays Patient
Monitor and Medical Equipment Displays
Projectors Weight Scales
These functions allow receipt of synchronous data
from a compatible transmitter, such as the
SN75LVDS83B, over five balanced-pair conductors,
and expansion to 28 bits of single-ended low-voltage
TTL (LVTTL) synchronous data at a lower transfer
rate. The SN75LVDS82 can also be used with the
SN75LVDS84 for 21-bit transfers.
When receiving, the high-speed LVDS data is
received and loaded into registers at the rate of
seven times (7×) the LVDS input clock (CLKIN). The
data is then unloaded to a 28-bit-wide LVTTL parallel
bus at the CLKIN rate. A phase-locked loop (PLL)
clock synthesizer circuit generates a 7× clock for
internal clocking and an output clock for the
expanded data. The SN75LVDS82 presents valid
data on the falling edge of the output clock
(CLKOUT).
The SN75LVDS82 requires only five line-termination
resistors for the differential inputs and little or no
control. The data bus appears the same at the input
to the transmitter and output of the receiver with the
data transmission transparent to the user.
Device Information(1)
PART NUMBER
SN75LVDS82
PACKAGE
TSSOP (56)
BODY SIZE (NOM)
14.00 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Spacer
Spacer
FFC
LV DS
LVDS
82
CMO
S
RGB
LCD
Drive
r
SoC
LVDS
LVDS
Serializer
CMOS
RGB
Video
Source
Can be discrete
SN75LVDS83B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVDS82
SLLS259J – NOVEMBER 1996 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
1
1
1
2
3
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics .......................................... 6
Timing Requirements ................................................ 7
Switching Characteristics .......................................... 7
Typical Characteristics .......................................... 10
8
Parameter Measurement Information ................ 11
9
Detailed Description ............................................ 12
8.1 Equivalent Input and Output Schematic Diagrams . 11
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 14
10 Application and Implementation........................ 16
10.1 Application Information.......................................... 16
10.2 Typical Applications .............................................. 16
11 Power Supply Recommendations ..................... 19
11.1 Decoupling Capacitor Recommendations............. 19
12 Layout................................................................... 19
12.1 Layout Guidelines ................................................. 19
12.2 Layout Example .................................................... 20
13 Device and Documentation Support ................. 21
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (April 2011) to Revision J
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Changed Feature From: "238 Mbytes/s Throughput" To: "1904 Mbps Throughput" ............................................................. 1
•
Deleted Feature: "Improved Replacement for the National™ DS90C582 " ........................................................................... 1
•
Added item to the Applications list: "Laptop and PC Display..."............................................................................................. 1
•
Changed text in the Description From: "such as the SN75LVDS81: To: "such as the SN75LVDS83B" ............................... 1
•
Changed text in the Description From: "SN75LVDS84 or SN75LVDS85 for 21-bit transfers." To: "SN75LVDS84 for
21-bit transfers" ...................................................................................................................................................................... 1
•
Changed device number SN75LVDS81 To: SN75LVDS83B in Figure 16........................................................................... 16
•
Deleted image 18-Bit Color Host to 24-Bit Color LCD Panel Display Application from the Application Information
section .................................................................................................................................................................................. 18
2
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5 Description (continued)
The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS receivers for lower power consumption. A low-level on SHTDN clears all internal registers
to a low level and places the TTL outputs in a high-impedance state.
The SN75LVDS82 is characterized for operation over ambient air temperatures of 0°C to 70°C.
6 Pin Configuration and Functions
DGG Package
56-Pin TSSOP
Top View
D22
1
56
VCC
D23
2
55
D21
D24
3
54
D20
GND
4
53
D19
D25
5
52
GND
D26
6
51
D18
D27
7
50
D17
LVDSGND
8
49
D16
A0M
9
48
VCC
A0P
10
47
D15
A1M
11
46
D14
A1P
12
45
D13
LVDSVCC
13
44
GND
LVDSGND
14
43
D12
A2M
15
42
D11
A2P
16
41
D10
CLKINM
17
40
VCC
CLKINP
18
39
D9
A3M
19
38
D8
A3P
20
37
D7
LVDSGND
21
36
GND
PLLGND
22
35
D6
PLLVCC
23
34
D5
PLLGND
24
33
D4
SHTDN
25
32
D3
CLKOUT
26
31
VCC
D0
27
30
D2
GND
28
29
D1
Not to scale
Pin Functions
Pin
Name
No.
I/O
Description
A0M, A0P
9, 10
LVDS Data Lane 0
A1M, A1P
11, 12
LVDS Data Lane 1
A2M, A2P
15, 16
A3M, A3P
19, 20
CLKINM,
CLKINP
LVDS Input
LVDS Data Lane 2
LVDS Data Lane 3
LVDS Clock
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Pin Functions (continued)
Pin
Name
No.
D0
27
D1
29
D2
30
D3
32
D4
33
D5
34
D6
35
D7
37
D8
38
D9
39
D10
41
D11
42
D12
43
D13
45
D14
46
D15
47
D16
49
D17
50
D18
51
D19
53
D20
54
D21
55
D22
1
D23
2
D24
3
D25
5
D26
6
D27
7
CLKOUT
26
SHTDN
25
LVDSGND
8, 14, 21
LVDSVCC
13
PLLGND
22
PLLVCC
23
I/O
LVTTL
Output
Description
Data Bus Output
Clock output for the data bus
Input
Shutdown Mode; Active-Low
LVDS Ground
LVDS Power supply 3.3 V
Power
PLL Ground
PLL Power supply 3.3 V
VCC
31,40, 48, 56
Digital Power supply 3.3 V
GND
4, 28, 36, 52
Digital Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage (2)
VO
Output voltage (Dxx terminals)
VI
Input voltage
(2)
UNIT
4
V
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
SHTDN
–0.5
5.5
V
See Thermal Information
Operating temperature
Tstg Storage temperature
(1)
MAX
Any terminal except SHTDN
Continuous total power dissipation
TA
MIN
–0.5
0
70
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND, unless otherwise noted.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
3.3
3.6
VCC
Supply voltage
3
VIH
High-level input voltage (SHTDN)
2
VIL
Low-level input voltage (SHTDN)
|VID|
Differential input voltage
VIC
Common-mode input voltage (see Figure 11 and Figure 7)
UNIT
V
V
0.1
|V
|
ID
2
0.8
V
0.6
V
|V
2.4 -
|
ID
2
V
VCC – 0.8
TA
Operating free-air temperature
0
70
°C
7.4 Thermal Information
SN75LVDS82
THERMAL METRIC (1)
DGG (TSSOP)
UNIT
56 PINS
RθJA
Junction-to-ambient thermal resistance
57.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
14.6
°C/W
RθJB
Junction-to-board thermal resistance
26.2
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
25.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
100
mV
VIT+
Positive-going differential input threshold voltage
VIT–
Negative-going differential input threshold voltage (2)
VOH
High-level output voltage
IOH = –4 mA
VOL
Low-level output voltage
IOL = 4 mA
0.4
V
Disabled, All inputs open
280
μA
ICC
Quiescent current (average)
–100
mV
2.4
V
Enabled, AnP = 1 V,
AnM = 1.4 V,
tc = 15.38 ns
60
Enabled, CL = 8 pF,
Grayscale pattern
(see Figure 13),
tc = 15.38 ns
74
Enabled, CL = 8 pF,
Worst-case pattern
(see Figure 14),
tc = 15.38 ns
107
74
mA
IIH
High-level input current (SHTDN)
VIH = VCC
±20
μA
IIL
Low-level input current (SHTDN)
VIL = 0
±20
μA
IIN
Input current (LVDS input terminals A and CLKIN)
0 ≤ VI ≤ 2.4 V
±20
μA
IOZ
High-impedance output current
VO = 0 or VCC
±10
μA
(1)
(2)
6
All typical values are at VCC = 3.3 V, TA = 25°C.
The algebraic convention, in which the less-positive (more-negative) limit is designed minimum, is used in this data sheet for the
negative-going input voltage threshold only.
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7.6 Timing Requirements
MIN
MAX
UNIT
tc
Cycle time, input clock (1)
14.7
32.3
ns
tsu1
Setup time, input (see Figure 2)
600
ps
th1
Hold time, input (see Figure 2)
600
ps
(1)
Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.
7.7 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tsu2
Setup time, D0–D27 valid to CLKOUT↓
CL = 8 pF, See Figure 1
5
ns
th2
Hold time, CLKOUT↓ to D0–D27 valid
CL = 8 pF, See Figure 1
5
ns
tRSKM
Receiver input skew margin (2)(see Figure 2)
tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps (3)
490
ps
td
Delay time, CLKIN↑ to CLKOUT↓ (see Figure 2)
tc = 15.38 ns (± 0.2%), CL = 8 pF
3.7
tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns,
See Figure 15
±80
Δtc(o)
Cycle time, change in output clock period (4)
tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns,
See Figure 15
ns
ps
±300
ten
Enable time, SHTDN↑ to Dn valid
See Figure 3
1
ms
tdis
Disable time, SHTDN↓ to off state
See Figure 4
400
ns
tt
Transition time, output (10% to 90% tr or tf)
CL = 8 pF
3
ns
tw
Pulse duration, output clock
0.43 tc
ns
(1)
(2)
(3)
(4)
All typical values are at VCC = 3.3 V, TA = 25°C.
The parameter t(RSKM) is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by
tc/14 – tsu1/th1.
|Input clock jitter| is the magnitude of the change in input clock period.
Δtc(o) is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
tsu2
70% VOH
Dn
30% VOH
th2
70% VOH
CLKOUT
30% VOH
Figure 1. Setup and Hold Time Waveforms
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tc
4 t
7 c
t
(RSKM)
tsu1
3 t
7 c
th1
t
(RSKM)
An
and An
CLKIN
7× CLK
(Internal)
td
tw
CLKOUT
tr < 1 ns
90%
CLKIN
or An
≈300 mV
0V
10%
≈−300 mV
td
VOH
CLKOUT
1.4 V
VOL
Figure 2. Receiver Input Skew Margin and Delay Timing Waveforms
8
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CLKIN
An
ten
SHTDN
Invalid
Dn
Valid
Figure 3. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 4. Disable Time Waveforms
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7.8 Typical Characteristics
300
85
Grayscale Data Pattern
CL = 8 pF
TA = 25°C
70
Input jitter = 750 sin (6.28 f(mod) t) ps
VCC = 3.3 V
TA = 25°C
250
75
Zero-to-Peak Output Jitter – ps
I CC − Supply Current − mA
80
VCC = 3.6 V
65
60
VCC = 3.3 V
55
50
45
200
150
100
50
40
VCC = 3 V
35
20
0
30
40
50
60
0
70
VIC – Common-Mode Input Voltage – V
2.5
0.5
1
1.5
2
2.5
3
f(mod) – Modulation Frequency – MHz
fclk − Clock Frequency − MHz
Figure 5. Supply Current vs Clock Frequency
Figure 6. Zero-to-Peak Output Jitter vs Modulation
Frequency
Maximum at VCC >3.15 V
Maximum at 3 V VCC
2
1.5
1
0.5
Minimum
0
0
0.1
0.2
0.3
0.4
0.5
0.6
|VID| – Differential Input Voltage – V
Figure 7. Common-Mode Input Voltage vs Differential Input Voltage
10
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8 Parameter Measurement Information
8.1 Equivalent Input and Output Schematic Diagrams
VCC
300 kΩ
VCC
300 kΩ
SHTDN
AnP
50 Ω
AnM
7V
7V
7V
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Figure 9. SHTDN Input
Figure 8. LVDS Input
VCC
AP
5Ω
(VIAP + VIAM)/2
7V
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Figure 10. Output
VID
VIAP
D Output
AM
VIC
VIAM
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Figure 11. Voltage Definitions
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9 Detailed Description
9.1 Overview
The SN75LVDS82 implements five low-voltage differential signal (LVDS) line receivers: 4 data lanes and 1 clock
lane. The clock is internally multiplied by 7 and used for sampling LVDS data. Each input lane contains a shift
register that converts serial data to parallel. 28 total bits per clock period are deserialized and presented on the
LVTTL output bus
9.2 Functional Block Diagram
Serial-In/ParallelOut Shift Register
A1P
A1M
Serial In
CLK
A, B, ...G
Serial-In/ParallelOut Shift Register
A2P
A2M
Serial In
A, B, ...G
CLK
Serial-In/ParallelOut Shift Register
Serial In
Input Bus
A3P
A3M
D8
D9
D12
D13
D14
D15
D18
A, B, ...G
CLK
Serial-In/ParallelOut Shift Register
A4P
A4M
D0
D1
D2
D3
D4
D6
D7
Serial In
CLK
D19
D20
D21
D22
D24
D25
D26
A, B, ...G
Control Logic
SHTDN
D27
D5
D10
D11
D16
D17
D23
7× Clock/PLL
CLKINP
CLKINM
7× CLK
Clock In
Clock Out
CLKOUT
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9.3 Feature Description
9.3.1 LVDS Input Data
The SN65LVDS82 is a simple deserializer that ignores bit representation in the LVDS stream. The data inputs to
the receiver come from a transmitters such as the SN75LVDS83B and consist of up to 24 bits of video
information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit.
The pixel data assignment is listed in Table 1 for 24-bit, 18-bit, and 12-bit color hosts.
Table 1. Pixel Data Assignment
SERIAL
CHANNEL
Y0
Y1
Y2
Y3
CLKOUT
8-BIT
DATA BITS
6-BIT
4-BIT
NON-LINEAR STEP LINEAR STEP
SIZE
SIZE
FORMAT-1
FORMAT-2
FORMAT-3
D0
R0D27
R2
R2
R0
R2
VCC
D1
R1
R3
R3
R1
R3
GND
D2
R2
R4
R4
R2
R0
R0
D3
R3
R5
R5
R3
R1
R1
D4
R4
R6
R6
R4
R2
R2
D6
R5
R7
R7
R5
R3
R3
D7
G0
G2
G2
G0
G2
VCC
D8
G1
G3
G3
G1
G3
GND
D9
G2
G4
G4
G2
G0
G0
D12
G3
G5
G5
G3
G1
G1
D13
G4
G6
G6
G4
G2
G2
D14
G5
G7
G7
G5
G3
G3
D15
B0
B2
B2
B0
B2
VCC
D18
B1
B3
B3
B1
B3
GND
D19
B2
B4
B4
B2
B0
B0
D20
B3
B5
B5
B3
B1
B1
D21
B4
B6
B6
B4
B2
B2
D22
B5
B7
B7
B5
B3
B3
D24
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
D25
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
D26
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
D27
R6
R0
GND
GND
GND
GND
D5
R7
R1
GND
GND
GND
GND
D10
G6
G0
GND
GND
GND
GND
D11
G7
G1
GND
GND
GND
GND
D16
B6
B0
GND
GND
GND
GND
D17
B7
B1
GND
GND
GND
GND
D23
RSVD
RSVD
GND
GND
GND
GND
CLKIN
CLK
CLK
CLK
CLK
CLK
CLK
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CLKIN
Previous Cycle
Current Cycle
Next Cycle
A0
D0–1
D7
D6
D4
D3
D2
D1
D0
D7+1
A1
D8–1
D18
D15
D14
D13
D12
D9
D8
D18+1
A2
D19–1
D26
D25
D24
D22
D21
D20
D19
D26+1
A3
D27–1
D23
D17
D16
D11
D10
D5
D27
D23+1
CLKOUT
Dn – 1
D0
Dn
Dn + 1
Copyright © 2016, Texas Instruments Incorporated
Figure 12. SN75LVDS82 Load and Shift Timing Sequences
9.4 Device Functional Modes
9.4.1
Low Power Mode
The SN75LVDS82 can be put in low-power consumption mode by active-low input SHTDN. Connecting pin
SHTDN to GND inhibits the clock and shut off the LVDS output drivers for lower power consumption. A low level
on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN to enable the device
for normal operation.
9.4.2 Test Patterns
CLKOUT
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4−7, 12−15, 20−23
D24−27
NOTE A: The 16-grayscale test-pattern tests device power consumption for a typical display pattern.
Figure 13. 16-Grayscale Test-Pattern Waveforms
14
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Device Functional Modes (continued)
tc
CLKOUT
EVEN Dn
ODD Dn
NOTE A: The worst-case test pattern produces the maximum switching frequency for all of the outputs.
Figure 14. Worst-Case Test-Pattern Waveforms
TektronixTM
HFS9003/HFS9DG1
Stimulus System
(repeating patterns of
F0FFFFF and 0F00000)
An
Device
Under
Test
(DUT)
CLKIN
A.
Tektronix
Microwave Logic
Multi-BERT-100RX
Word Error Detector
D0−D27
CLKOUT
CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The magnitude of
the advance or delay is t(RSKM).
Reference
+
∑
Device
Under
Test
VCO
+
Modulation
V(t) = A sin (2 p f(mod) t)
HP8656B
Signal Generator
0.1 MHz to 990 MHz
HP8665A
Synthesized Signal
Generator
0.1 MHz to 990 MHz
RF OUTPUT
RF Output
Device Under Test
Digital T
CLKIN
CLKOUT
Input
Modulation Input
Figure 15. Input Clock Jitter Test
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section describes provides information on how each signal should be connected from the graphic source
through the SN75LVDS83B and the SN75LVDS82 to the LCD panel input.
10.2 Typical Applications
10.2.1 Signal Connectivity
Host
Cable
Flat Panel Display
SN75LVDS83B
Y0M
48
9
A0M
100 W
Y0P
Y1M
47
10
46
11
A0P
A1M
100 W
Y1P
Y2M
45
12
42
15
A1P
A2M
100 W
Y2P
Y3M
41
16
38
19
A2P
A3M
100 W
Y3P
CLKOUTM
37
20
40
17
A3P
CLKINM
100 W
CLKOUTP
Graphic Controller
SN75LVDS82
39
18
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKOUT
27
29
30
32
33
35
7
34
37
38
39
43
45
46
41
42
47
51
53
54
55
1
49
50
3
5
6
2
26
12-BIT
RED0
RED1
RED2
RED3
RSVD
RSVD
NA
NA
GREEN0
GREEN1
GREEN2
GREEN3
RSVD
RSVD
NA
NA
BLUE0
BLUE1
BLUE2
BLUE3
RSVD
RSVD
NA
NA
H_SYNC
V_SYNC
ENABLE
NA
CLOCK
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
NA
NA
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
NA
NA
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
NA
NA
H_SYNC
V_SYNC
ENABLE
NA
CLOCK
24-BIT
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
H_SYNC
V_SYNC
ENABLE
RSVD
CLOCK
CLKINP
Copyright © 2016, Texas Instruments Incorporated
A.
The five 100-Ω terminating resistors are recommended to be 0603 types.
B.
NA — not applicable, these unused inputs should be left open.
Figure 16. 24-Bit Color Host to 24-Bit LCD Flat Panel Display Application
16
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Typical Applications (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 2.
Table 2. Design Parameters
DESIGN PARAMETERS
VALUE
VDD Main Power Supply
3.3 V
Input LVDS Clock Frequency
31 - 68 MHz
RL Differential Input Termination Resistance
100 Ω
LVDS Input Lanes
4
Color depth
24 Bit
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Power Up Sequence
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended.
Power up sequence (SN75LVDS82 /SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5 ms to 10 ms) but keep backlight turned off.
2. Wait for additional 0-200 ms to ensure display noise will not occur.
3. Enable video source output; start sending black video data.
4. Toggle SN75LVDS82 shutdown to SHTDN = VIH.
5. Send > 1 ms of black video data; this allows the SN75LVDS82 to be phase locked, and the display to show
black data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN75LVDS82 SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for > 2 frame times.
3. Set SN75LVDS82 input SHTDN = GND; wait for 250 ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
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Voltage - 200 mV/div
10.2.1.3 Application Curves
Time ± 20 ns/div
Voltage - 2 mV/div
Figure 17. LVDS Clock
Time ± 20 ns/div
Figure 18. Output Clock
18
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11 Power Supply Recommendations
11.1 Decoupling Capacitor Recommendations
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS82 power pins. It is
recommended to place one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on
each power node. The distance between the SN65LVDS82 and capacitors should be minimized to reduce loop
inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65LVDS82 on the bottom
of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize the EMI
performance.
12 Layout
12.1 Layout Guidelines
1. Use 45 degree bends (chamfered corners), instead of right-angle (90°) bends. Right-angle bends increase
the effective trace width, which changes the differential trace impedance creating large discontinuities. A 45
degree bend is seen as a smaller discontinuity.
2. Place passive components within the signal path, such as source-matching resistors or ac-coupling
capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b), the resulting
discontinuity, however, is limited to a far narrower area
3. When routing traces next to a via or between an array of vias, make sure that the via clearance section does
not interrupt the path of the return current on the ground plane below.
4. Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better
impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the
board during TDR testing.
5. Use solid power and ground planes for 100 Ω impedance control and minimum power noise. For a multilayer
PCB, it is recommended to keep one common GND layer underneath the device and connect all ground
terminals directly to this plane.
6. For 100 Ω differential impedance, use the smallest trace spacing possible, which is usually specified by the
PCB vendor.
7. Keep the trace length as short as possible to minimize attenuation.
8. Place bulk capacitors (that is, 10 μF) close to power sources, such as voltage regulators or where the power
is supplied to the PCB.
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12.2 Layout Example
Figure 19. Layout Example
20
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
FlatLink, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SN75LVDS82DGG
ACTIVE
TSSOP
DGG
56
35
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
SN75LVDS82
Samples
SN75LVDS82DGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
SN75LVDS82
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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