SN75LVDS83DGG

Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 D 4:28 Data Channel Compression at up to D D D D D D D D D D D D D 238 MBytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI 28 Data Channels and Clock-In Low-Voltage TTL 4 Data Channels and Clock-Out Low-Voltage Differential Operates From a Single 3.3-V Supply With 250 mW (Typ) ESD Protection Exceeds 6 kV 5-V Tolerant Data Inputs Selectable Rising or Falling Edge-Triggered Inputs Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the DS90C581 description DGG PACKAGE (TOP VIEW) VCC D5 D6 D7 GND D8 D9 D10 VCC D11 D12 D13 GND D14 D15 D16 CLKSEL D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 D4 D3 D2 GND D1 D0 D27 LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP Y3M Y3P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D26 GND The SN75LVDS83 FlatLink transmitter contains 28 29 four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit links with the SN75LVDS86 receiver. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN75LVDS83 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers to a low level. The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a registered trademark of Texas Instruments. Copyright  1997 − 2009, Texas Instruments Incorporated      !"#   $"%!  & #' &"!  !  $#!!  $# (# #  #)  "#   && * +' &"!  $!#, &#  #!#+ !"&# # ,   $# #' POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 functional block diagram D0, D1, D2, D3, D4, D6, D7 Parallel-Load 7-Bit Shift Register 7 A,B, ...G SHIFT/LOAD Y0P Y0M CLK D8, D9, D12, D13, D14, D15, D18 Parallel-Load 7-Bit Shift Register 7 Y1P A,B, ...G SHIFT/LOAD Y1M CLK D27, D5, D10, D11, D16, D17, D23 Y2P A,B, ...G SHIFT/LOAD 7 Input Bus D19, D20, D21, D22, D24, D25, D26 Parallel-Load 7-Bit Shift Register 7 Y2M CLK Parallel-Load 7-Bit Shift Register Y3P A,B, ...G SHIFT/LOAD Y3M CLK Control Logic SHTDN 7× Clock/PLL CLKIN 7×CLK CLKOUTP CLK CLKOUTM CLKINH CLKSEL 2 RISING/FALLING EDGE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Not Recommended for New Designs D0 ÉÉÉ ÉÉÉ

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 ÉÉÉ ÉÉÉ CLKIN or CLKIN ÉÉ ÉÉ CLKOUT ÇÇ ÇÇ ÉÉ ÉÉ Previous Cycle ÇÇ ÇÇ Next Cycle Current Cycle Y0 D0−1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8−1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19−1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27−1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. SN75LVDS83 Load and Shift Timing Sequences equivalent input and output schematic diagrams VCC VCC 5Ω Dn or SHTDN YnP or YnM 10 kΩ 50 Ω 7V 7V 300 kΩ INPUT OUTPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

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 Not Recommended for New Designs SLLS271I − MARCH 1997 − REVISED MAY 2009 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Output voltage range, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input voltage range, VI (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1377 mW 11.0 mW/°C 822 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. recommended operating conditions MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 High-level input voltage, VIH 2 Operating free-air temperature, TA V V Low-level input voltage, VIL Differential load impedance, ZL UNIT 0.8 V 90 132 Ω 0 70 °C timing requirements MAX UNIT tc tw Cycle time, input clock 14.7 MIN 32.3 ns Pulse duration, high-level input clock 0.4 tc 0.6 tc ns tt tsu Transition time, input signal 5 ns th Hold time, data, D0 − D27 valid after CLKIN↑ or CLKIN↓ (see Figure 2) 4 Setup time, data, D0 − D27 valid before CLKIN↑ or CLKIN↓ (see Figure 2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NOM 3 ns 1.5 ns Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT |VOD| Input threshold voltage ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) VOC(PP) Steady-state common-mode output voltage IIH IIL High-level input current TYP† MAX UNIT 454 mV 50 mV 1.4 Differential steady-state output voltage magnitude Peak-to-peak common-mode output voltage 247 RL = 100 Ω, See Figure 3 1.125 Short-circuit output current IOZ High-impedance state output current Quiescent supply current V 1.375 See Figure 3 VIH = VCC VIL = 0 Low-level input current IOS ICC MIN V 150 mV 25 µA ±10 µA VO(Yn) = 0 VOD = 0 ±24 mA ±12 mA VO = 0 to VCC Disabled, All inputs at GND ±10 µA 280 µA Enabled, RL = 100 Ω, Gray-scale pattern (see Figure 4), VCC = 3.3 V, tc = 15.38 ns 72 90 mA Enabled, RL = 100 Ω, Worst-case pattern (see Figure 5), tc = 15.38 ns 85 110 mA CI Input capacitance † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 pF 5 

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 Not Recommended for New Designs SLLS271I − MARCH 1997 − REVISED MAY 2009 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† 0 td0 Delay time, CLKOUT↑ to serial bit position 0 −0.2 td1 Delay time, CLKOUT↑ to serial bit position 1 td2 Delay time, CLKOUT↑ to serial bit position 2 td3 td4 Delay time, CLKOUT↑ to serial bit position 3 tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 Delay time, CLKOUT↑ to serial bit position 4 1 t * 0.2 7 c 2 t * 0.2 7 c 3 t * 0.2 7 c 4 t * 0.2 7 c td5 Delay time, CLKOUT↑ to serial bit position 5 td6 Delay time, CLKOUT↑ to serial bit position 6 tsk(o) Output skew, td7 Delay time, CLKIN↓ to CLKOUT↑ tn * n tc 7 tc = 18.51 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 ∆ tc(o) Cycle time, output clock jitter§ MAX UNIT 0.2 ns ns 5 t * 0.2 7 c 1 t ) 0.2 7 c 2 t ) 0.2 7 c 3 t ) 0.2 7 c 4 t ) 0.2 7 c 5 t ) 0.2 7 c 6 t * 0.2 7 c 6 t ) 0.2 7 c ns −0.2 0.2 ns 7.75 ns 3.75 5.6 ns ns ns ns tc = 15.38 ± 0.75 sin (2π500E3t) + 0.05 ns, See Figure 7 ± 70 ps tc = 15.38 ± 0.75 sin (2π3E6t) + 0.05 ns, See Figure 7 ± 187 ps 4t 7 c ns tw Pulse duration, high-level output clock tt Transition time, differential output (tr or tf) See Figure 3 ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 8 1 ms tdis Disable time, SHTDN↓ to off state (CLKOUT low) See Figure 9 250 ns 260 700 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ |Input clock jitter| is the magnitude of the change in the input clock period. § Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1500 ps Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION ÉÉÉÉÉ ÉÉÉÉÉ Dn tsu th ÉÉÉÉ ÉÉÉÉ CLKSEL LOW CLKIN CLKSEL HIGH NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Waveforms 49.9 Ω ± 1% (2 Places) YP VOD VOC YM CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) SCHEMATIC 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure 3. Test Load and Voltage Waveforms for LVDS Outputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION CLKIN D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4−7, 12−15, 20−23 D24−27 NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern. Pattern with CLKSEL low shown. Figure 4. 16-Grayscale Test-Pattern Waveforms tc CLKIN Even Dn Odd Dn NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with CLKSEL low shown. Figure 5. Worst-Case Test-Pattern Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION td7 CLKIN (see Note A) CLKIN (see Note B) CLKOUT Yn ÏÏÏ ÏÏÏ ÏÏÏ ÉÉ ÉÉ td1 ÎÎ ÎÎ ÎÎ td0 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÏÏ ÏÏ ÏÏ ÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉ td2 td3 td4 td5 td6 ≈ 2.5 V CLKIN 1.4 V VOD(H) CLKOUT or Yn 0.00 V ≈ 0.5 V VOD(L) td7 td0 − td6 NOTES: A. This wave form is valid when CLKSEL is low. B. This wave form is valid when CLKSEL is high. Figure 6. SN75LVDS83 Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz − 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz − 4200 MHz Device Under Test OUTPUT RF Output CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 7. Output Clock Jitter Testing CLKIN Dn ten SHTDN ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Yn Invalid Figure 8. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 9. Disable Time Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Valid Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY I CC − Average Supply Current − mA 80 VCC = 3.6 V 70 60 VCC = 3.3 V 50 VCC = 3 V 40 Grayscale Data Pattern RL = 100 Ω TA = 25°C 30 30 40 50 60 70 fclk − Clock Frequency − MHz Figure 10 ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 200 Zero-to-Peak Output Jitter − ps 180 160 140 120 100 80 60 40 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.3 V TA = 25°C 20 0 0 0.5 1 1.5 2 2.5 3 f(mod) − Modulation Frequency − MHz Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 APPLICATION INFORMATION Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK Cable Flat Panel Display SN75LVDS83 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK See Note A 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31 17 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL SN75LVDS82 Y0M 48 9 A0M 100 Ω Y0P Y1M 47 10 46 11 A0P A1M 100 Ω Y1P Y2M 45 12 42 15 A1P A2M 100 Ω Y2P Y3M 41 16 38 19 A2P A3M 100 Ω Y3P CLKOUTM 37 20 40 17 A3P CLKINM 100 Ω CLKOUTP 39 18 CLKINP NOTES: A. Connect this terminal to VCC for triggering to the rising edge of the input clock and to GND for the falling edge. B. The five 100-Ω terminating resistors are recommended to be 0603 types. Figure 12. 24-Bit Color Host To 24-Bit LCD Panel Display Application 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Not Recommended for New Designs

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 SLLS271I − MARCH 1997 − REVISED MAY 2009 APPLICATION INFORMATION Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK Cable Flat Panel Display SN75LVDS83 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK See Note A 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31 17 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL SN75LVDS86 Y0M 48 8 A0M 100 Ω Y0P Y1M 47 9 46 10 A0P A1M 100 Ω Y1P Y2M 45 11 42 14 A1P A2M 100 Ω Y2P Y3M Y3P CLKOUTM 41 15 A2P 38 37 40 16 CLKINM 100 Ω CLKOUTP 39 17 CLKINP NOTES: A. Connect this terminal to VCC for triggering to the rising edge of the input clock and to GND for the falling edge. B. The four 100-Ω terminating resistors are recommended to be 0603 types. Figure 13. 24-Bit Color Host To 18-Bit LCD Panel Display Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN75LVDS83DGG NRND TSSOP DGG 56 35 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS83 SN75LVDS83DGGG4 NRND TSSOP DGG 56 35 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS83 SN75LVDS83DGGR NRND TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS83 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of