SN75LVDS84DGGR

SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 FLATLINK™ TRANSMITTERS FEATURES 1 • 21:3 Data Channel Compression at up to 163 Million Bytes per Second Throughput • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI • 21 Data Channels Plus Clock-In Low-Voltage TTL and 3 Data Channels Plus Clock-Out Low-Voltage Differential • Operates From a Single 3.3-V Supply and 250 mW (Typ) • 5-V Tolerant Data Inputs • ESD Protection Exceeds 6 kV • SN75LVDS84 Has Falling-Clock Edge-Triggered Inputs • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch • Consumes Less Than 1 mW When Disabled • Wide Phase-Lock Input Frequency Range: – 31 MHz to 68 MHz • No External Components Required for PLL • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard • Improved Replacement for the DS90C561 DGG PACKAGE (TOP VIEW) 23 D4 VCC D5 D6 GND D7 D8 VCC D9 D10 GND D11 D12 NC D13 D14 GND D15 D16 D17 VCC D18 D19 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC - Not Connected D3 D2 GND D1 D0 NC LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D20 P0052-02 DESCRIPTION The SN75LVDS84 FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86. When transmitting, data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. AVAILABLE OPTIONS (1) LATCHING CLOCK EDGE FALLING SN75LVDS84DGG SN75LVDS84DGGR (1) The R suffix indicates taped and reeled packaging. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2007, Texas Instruments Incorporated SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 DESCRIPTION (CONTINUED) The SN75LVDS84 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The SN75LVDS84 is characterized for operation over ambient free-air temperatures of 0°C to 70°C. FUNCTIONAL BLOCK DIAGRAM 7 D0–D6 Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD Y0P Y0M CLK 7 D7–D13 Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD Y1P Y1M CLK 7 D14–D20 Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD Y2P Y2M CLK Control Logic SHTDN 7´ Clock/PLL 7´CLK CLKIN CLK CLKINH CLKOUTP CLKOUTM B0274-01 2 Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 D0 CLKIN CLKOUT Next Cycle Previous Cycle Current Cycle Y0 D0–1 D6 D5 D4 D3 D2 D1 D0 D6+1 Y1 D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1 Y2 D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1 T0274-01 Figure 1. Load and Shift Timing Sequences SCHEMATICS OF INPUT AND OUTPUT EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH OUTPUT VCC VCC D or SHTDN 5W 50 W 10 kW 7V YnP or YnM 7V 300 kW S0313-01 Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 3 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.5 to 4 V –0.5 to VCC + 0.5 V VCC Supply voltage range (2) VO Output voltage range (all terminals) VI Input voltage range (all terminals) –0.5 to 5.5 Continuous total power dissipation See Dissipation Rating Table Tstg Storage temperature range –6 to 150 °C 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals. DISSIPATION RATINGS (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1316 mW 13.1 mW/°C 726 mW This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 VIH High-level input voltage 2 VIL Low-level input voltage ZL Differential load impedance TA Operating free-air temperature UNIT V V 0.8 V 90 132 Ω 0 70 °C TIMING REQUIREMENTS PARAMETER tc Input clock period tw Pulse duration, high-level input clock tt Transition time, input signal tsu Setup time, data, D0–D27 valid before CLKIN↓ (See Figure 2) th Hold time, data, D0–D27 valid after CLKIN↓ (See Figure 2) 4 Submit Documentation Feedback MAX UNIT 14.7 MIN TYP 32.4 ns 0.4 tc 0.6 tc ns 5 ns 3 ns 1.5 ns Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 454 mV 50 mV VIT Input threshold voltagee |VOD| Differential steady-state output voltage magnitude Δ|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) Steady-state common-mode output voltage VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current VIH = VCC IIL Low-level input current VIL = 0 IOS Short-circuit output current VO(Yn) = 0 ±24 mA VOD = 0 ±12 mA IOZ High-impedance output current VO = 0 to VCC ±10 µA Disabled, all inputs at GND 280 µA ICC(AVG) CI (1) 1.4 Quiescent supply current (average) 247 RL = 100 Ω, See Figure 3 See Figure 3 1.125 V 1.375 80 V 150 mV 20 µA ±10 µA Enabled, RL = 100 Ω (4 places), gray-scale pattern (see Figure 4), VCC = 3.3 V, tc = 15.38 ns 68 80 mA Enabled, RL = 100 Ω, (4 places), worst-case pattern (see Figure 5), tc = 15.38 ns 75 100 mA Input capacitance 3 pF All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 5 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) MIN TYP (1) MAX td0 Delay time, CLKOUT↑ to serial bit position 0 –0.2 0 0.2 ns td1 Delay time, CLKOUT↑ to serial bit position 1 1 t * 0.2 7 c 1 t ) 0.2 7 c ns td2 Delay time, CLKOUT↑ to serial bit position 2 2 t * 0.2 7 c 2 t ) 0.2 7 c ns 3 t * 0.2 7 c 3 t ) 0.2 7 c ns PARAMETER TEST CONDITIONS tc = 15.38 ns (±0.2%), |Input clock jitter| < 50 ps (2), See Figure 6 UNIT td3 Delay time, CLKOUT↑ to serial bit position 3 td4 Delay time, CLKOUT↑ to serial bit position 4 4 t * 0.2 7 c 4 t ) 0.2 7 c ns td5 Delay time, CLKOUT↑ to serial bit position 5 5 t * 0.2 7 c 5 t ) 0.2 7 c ns 6 t * 0.2 7 c 6 t ) 0.2 7 c ns tsk(o) Delay time, CLKOUT↑ to serial bit position 6 t *nt Output skew, n 7 c –0.2 0.2 ns td7 Delay time, CLKIN↓ to CLKOUT↑ td6 Δtc(o) Cycle time, output clock jitter (3) tc = 15.38 ns (±0.2%), |Input clock jitter| < 50 ps (2), see Figure 6 4.2 ns tc = 15.38 + 0.75 sin (2π500E3t) ±0.05 ns, See Figure 7 ±70 ps tc = 15.38 + 0.75 sin (2π3E3t) ±0.05 ns, See Figure 7 ±187 ps 4t 7 c ns tw Pulse duration, high-level output clock tt Transition time, differential output voltage See Figure 3 (tr or tf) ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 8 1 ms tdis Disable time, SHTDN↓ to off state (CLKOUT low) See Figure 9 250 ns (1) (2) (3) 6 260 700 1500 ps All typical values are at VCC = 3.3 V, TA = 25°C. |Input clock jitter| is the magnitude of the change in the input clock period. Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles. Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION tsu th Dn CLKIN T0275-01 A. All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Definition 49.9 W ±1% (2 Places) YP VOD VOC YM CL = 10 pF Max (2 Places) Note: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) Schematic 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V (b) Waveforms S0314-01 Figure 3. Test Load and Voltage Definitions for LVDS Outputs Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 7 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) CLKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 All Others T0276-01 A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. B. VIH = 2 V and VIL = 0.8 V Figure 4. 16-Grayscale Test-Pattern Waveforms tc CLKIN Even Dn Odd Dn T0277-01 A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. B. VIH = 2 V and VIL = 0.8 V Figure 5. Worst-Case Test-Pattern Waveforms 8 Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) td7 CLKIN CLKOUT td0 Yn td1 td2 td3 td4 td5 td6 » 2.5 V VOD(H) CLKOUT or Yn 1.4 V CLKIN 0V » 0.5 V VOD(L) td7 td0–td6 T0278-01 Figure 6. Timing Definitions Device Under Test + Reference S VCO + Modulation V(t) = A sin (2p fmod t) HP8656B Signal Generator 0.1 MHz–990 MHz HP8665A Synthesized Signal Generator 0.1 MHz–4200 MHz OUTPUT RF Output Device Under Test CLKIN DTS2070C Digital Time Scope CLKOUT Input Modulation Input B0275-01 Figure 7. Clock Jitter Test Setup Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 9 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS CLKIN Dn ten SHTDN Invalid Yn Valid T0279-01 Figure 8. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT T0280-01 Figure 9. Disable Time Waveforms AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 200 75 180 VCC = 3.6 V Zero-to-Peak Output Jitter − ps ICC − Average Supply Current − mA 70 65 60 VCC = 3.3 V 55 50 VCC = 3 V 45 Grayscale Data Pattern RL = 100 Ω TA = 25°C 40 50 60 f(clk) − Clock Frequency − MHz 140 120 100 80 60 40 20 40 30 160 70 0 0.0 Input jitter = 750 sin (6.28 fmod t) ps VCC = 3.3 V TA = 25°C G001 Figure 10. 10 0.5 1.0 1.5 2.0 2.5 fmod − Modulation Frequency − MHz 3.0 G002 Figure 11. Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 APPLICATION INFORMATION Cable Flat Panel Display Host Graphics Controller SN75LVDS84 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKIN SN75LVDS86 8 41 Y0M A0M 100 W 40 9 Y0P A0P 39 10 Y1M A1M 100 W 38 11 Y1P A1P 35 14 Y2M A2M 100 W 34 15 Y2P A2P 33 16 CLKINM CLKOUTM 100 W 32 17 CLKINP CLKOUTP B0276-01 A. The five 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 12. Color Host to LCD Panel Application Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 11 SN75LVDS84 www.ti.com SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007 Cable Flat Panel Display Host Graphics Controller SN75LVDS84 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKIN SN75LVDS82 9 41 Y0M A0M 100 W 40 10 Y0P A0P 39 11 Y1M A1M 100 W 38 12 Y1P A1P 35 15 Y2M A2M 100 W 34 16 Y2P A2P 33 CLKINM CLKOUTM 100 W 32 CLKINP CLKOUTP A3M 100 W A3P B0277-01 A. The four 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application (See the FlatLink Designer's Guide (SLLA012) for more application information.) 12 Submit Documentation Feedback Copyright © 1997–2007, Texas Instruments Incorporated Product Folder Link(s) :SN75LVDS84 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SN75LVDS84DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS84 Samples SN75LVDS84DGGG4 ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS84 Samples SN75LVDS84DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS84 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of