TAS5036BPFC

         Data Manual November 2002 DAV Digital Audio/Speaker SLES044B Contents Contents Section 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Functional Block Diagram . . . . . . . . . . . . . 2 1.3 Terminal Assignments . . . . . . . . . . . . . . . . 3 1.4 Ordering Information . . . . . . . . . . . . . . . . . 4 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . 4 Architecture Overview . . . . . . . . . . . . . . . . . . . . . 6 2.1 Clock and Serial Data Interface . . . . . . . . 6 2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection . . 6 2.1.2 Clock Master/Slave Mode (M_S) . . . . . . . . . . . . . . . . . . . . 7 2.1.3 Clock Master Mode . . . . . . . . . 7 2.1.4 Clock Slave Mode . . . . . . . . . . 8 2.1.5 PLL Filter . . . . . . . . . . . . . . . . . 10 2.1.6 DCLK . . . . . . . . . . . . . . . . . . . . . 10 2.1.7 Serial Data Interface . . . . . . . . 10 2.2 Reset, Power Down, and Status . . . . . . . 15 2.2.1 Reset—RESET . . . . . . . . . . . . 15 2.2.2 Power Down—PDN . . . . . . . . 16 2.2.3 Status Registers . . . . . . . . . . . 16 2.3 Signal Processing . . . . . . . . . . . . . . . . . . . 17 2.3.1 Volume Control . . . . . . . . . . . . 17 2.3.2 Mute . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 Auto Mute . . . . . . . . . . . . . . . . . 18 2.3.4 Individual Channel Mute . . . . . 18 2.3.5 De-Emphasis Filter . . . . . . . . . 18 November 2002 Page 2.4 3 4 5 Pulse Width Modulator (PWM) . . . . . . . . . 19 2.4.1 Clipping Indicator . . . . . . . . . . . 19 2.4.2 Error Recovery . . . . . . . . . . . . 19 2.4.3 Individual Channel Error Recovery . . . . . . . . . . . . . . . . . . . . 20 2.4.4 PWM DC-Offset Correction . . 20 2.4.5 Inter-Channel Delay . . . . . . . . 20 2.4.6 ABD Delay . . . . . . . . . . . . . . . . 20 2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface . . . . 21 2.5 I2C Serial Control Interface . . . . . . . . . . . 21 2.5.1 Single Byte Write . . . . . . . . . . . 22 2.5.2 Multiple Byte Write . . . . . . . . . 22 2.5.3 Single Byte Read . . . . . . . . . . . 23 2.5.4 Multiple Byte Read . . . . . . . . . 23 Serial Control Interface Register Definitions . 24 3.1 General Status Register (x00) . . . . . . . . . 25 3.2 Error Status Register (x01) . . . . . . . . . . . . 25 3.3 System Control Register 0 (x02) . . . . . . . 25 3.4 System Control Register 1 (x03) . . . . . . . 26 3.5 Error Recovery Register (x04) . . . . . . . . . 26 3.6 Automute Delay Register (x05) . . . . . . . . 26 3.7 DC-Offset Control Registers (x06–x0B) . 27 3.8 Interchannel Delay Registers (x0C–x11) 27 3.9 ABD Delay Register (x12) . . . . . . . . . . . . . 27 3.10 Individual Channel Mute Register (x19) . 27 System Initialization . . . . . . . . . . . . . . . . . . . . . . . 28 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SLES044B 3 List of Illustrations 5.1 5.2 5.3 5.4 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . 29 Recommended Operating Conditions (Fs = 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . 29 5.3.1 Static Digital Specifications Over Recommended Operating Conditions . . . . . . . . . . . . . 29 5.3.2 Digital Interpolation Filter and PWM Modulator Over Recommended Operating Conditions Fs = 48 kHz . . . . . . . . . . . . . . . 29 5.3.3 TAS5036/TAS5100 System Performance Measured at the Speaker Terminals Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . 30 6 Switching Characteristics . . . . . . . . . . . . . 30 5.4.1 Command Sequence Timing . 30 5.4.2 Serial Audio Port . . . . . . . . . . . 34 5.4.3 Serial Control Port—I2C Operation . . . . . . . . . . . . . . . . . . . . 37 Application Information . . . . . . . . . . . . . . . . . . . . 38 6.1 Serial Audio Interface Clock Master and Slave Interface Configuration . . . . . . . . . . 39 6.1.1 Slave Configuration . . . . . . . . . 39 6.1.2 Master Configuration . . . . . . . 39 Appendix A—Volume Table . . . . . . . . . . . . . . . . . . . . 41 List of Illustrations Figure 2–1 Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2–2 External PLL Loop Filter . . . . . . . . . . . . . . . . . . . . 10 2–3 I2S 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2–4 I2S 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2–5 Left-Justified 64-Fs Format . . . . . . . . . . . . . . . . . . 12 2–6 Left-Justified 48-Fs Format . . . . . . . . . . . . . . . . . . 13 2–7 Right-Justified 64-Fs Format . . . . . . . . . . . . . . . . . 13 2–8 Right-Justified 48-Fs Format . . . . . . . . . . . . . . . . . 14 2–9 DSP Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2–10 Attenuation Curve . . . . . . . . . . . . . . . . . . . . . . . . . 17 2–11 De-Emphasis Filter Characteristics . . . . . . . . . . 19 4 SLES044B Title Page 2–12 PWM Outputs and H-Bridge Driven in BTL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2–13 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . . 22 2–14 Single Byte Write Transfer . . . . . . . . . . . . . . . . . 22 2–15 Multiple Byte Write Transfer . . . . . . . . . . . . . . . . 23 2–16 Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . 23 2–17 Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . . 23 4–1 RESET During System Initialization . . . . . . . . . . . 28 5–1 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5–2 Power-Down and Power-Up Timing—RESET Preceding PDN . . . . . . . . . . . . . . . . . . . . . . . . . 31 5–3 Power-Down and Power-Up Timing—RESET Following PDN . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5–4 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . . 33 November 2002 List of Tables 5–5 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5–6 Right-Justified, IIS, Left-Justified Serial Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5–7 Right, Left, and IIS Serial Mode Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5–8 Serial Audio Ports Master Mode Timing . . . . . . . 35 5–9 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . . 35 5–10 DSP Serial Port Expanded Timing . . . . . . . . . . . 36 5–11 DSP Absolute Timing . . . . . . . . . . . . . . . . . . . . . . 36 5–12 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . 37 5–13 Start and Stop Conditions Timing . . . . . . . . . . . . 37 6–1 Typical TAS5036 Application . . . . . . . . . . . . . . . . . 38 6–2 TAS5036 Serial Audio Port—Slave Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . 39 6–3 TAS5036 Serial Audio Port—Master Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . 39 List of Tables Table 2–1 Normal-Speed, Double-Speed, and Quad-Speed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2–2 Master and Slave Clock Modes . . . . . . . . . . . . . . 9 2–3 LRCLK, MCLK_IN, and External PLL Rates . . . 9 2–4 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2–5 Supported Word Lengths . . . . . . . . . . . . . . . . . . . . 11 2–6 Device Outputs During Reset . . . . . . . . . . . . . . . . 15 2–7 Values Set During Reset . . . . . . . . . . . . . . . . . . . . 15 2–8 Device Outputs During Power Down . . . . . . . . . . 16 2–9 Volume Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2–10 De-Emphasis Filter Characteristics . . . . . . . . . . 18 2–11 Device Outputs During Error Recovery . . . . . . . 20 November 2002 Title Page 3–1 I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3–2 General Status Register (Read Only) . . . . . . . . . 25 3–3 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . 25 3–4 System Control Register 0 . . . . . . . . . . . . . . . . . . 25 3–5 System Control Register 1 . . . . . . . . . . . . . . . . . . 26 3–6 Error Recovery Register . . . . . . . . . . . . . . . . . . . . 26 3–7 Automute Delay Register . . . . . . . . . . . . . . . . . . . . 26 3–8 DC-Offset Control Registers . . . . . . . . . . . . . . . . . 27 3–9 Six Inter-Channel Delay Registers . . . . . . . . . . . . 27 3–10 ABD Delay Register . . . . . . . . . . . . . . . . . . . . . . . 27 3–11 Individual Channel Mute Register . . . . . . . . . . . . 27 SLES044B 5 1 Introduction The TAS5036 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse width modulator (PWM) based on Equibit technology. Combined with a TI digital amplifier power stage, these devices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5036 is designed to drive up to six digital power devices to provide six channels of digital audio amplification. The digital power devices can be six conventional monolithic power stages (such as the TAS5110) or six discrete differential power stages using gate drivers and MOSFETs. The TAS5036 has six independent volume controls and mute. It is designed to drive a digital amplifier power stage (such as the TAS5182) in an H-bridge (bridge tied load) configuration. The device operates in AD and BD modes. This all-digital audio system contains only two analog components in the signal chain—an LC low-pass filter at each speaker terminal and can provide up to 96-dB SNR at the speaker terminals. The TAS5036 has a wide variety of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit) left justified, or DSP (16-bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and 48-kHz sample rates. The TAS5036 plus the TAS51xx power stage device combination was designed for home theater applications such as DVD minicomponent systems, home theater in a box (HTIB), DVD receiver, A/V receiver, or TV sets. 1.1 Features • • • • • • • • • • • • • • True Digital Audio Amplifier High Quality Audio – 96-dB SNR –