TAS5176DDWR

TM TAS5176 www.ti.com SLES196 – JUNE 2007 6-Channel, 100-W, Digital-Amplifier Power Stage FEATURES • • • • • • • • • Total Output Power at 10% THD+N – 5 × 15 W at 8 Ω + 1 × 25 W at 4 Ω (Single-Ended) – 2 x 30 W at 8 Ω (BTL) – 1 x 40 W at 6 Ω (BTL) 105-dB SNR (A-Weighted), with TAS5086 Modulator < 0.05% THD+N at 1 W Power Stage Efficiency > 90% Into Recommended Loads (SE) Integrated Self-Protection Circuits – Undervoltage – Overtemperature – Overload – Short Circuit Integrated Active-Bias Control to Avoid DC Pop Footprint Compatible with the TAS5186A for Scaleable Designs Thermally Enhanced 44-pin HTSSOP Package with PowerPad located on the bottom of the device EMI-Compliant When Used With Recommended System Design Furthermore, the TAS5176 can drive three-channels in BTL mode, with the same high-performance but with a higher power level. In BTL mode, the TAS5176 is capable of driving 8-Ω loads to greater than 30 Watts at 10% THD+N performance. A low-cost, high-fidelity audio system can be built using a TI chipset comprising a modulator (e.g., TAS5086) and the TAS5176. This device does not require power-up sequencing because of the internal power-on reset. The TAS5176 requires only simple passive demodulation filters on its outputs to deliver high-quality, high-efficiency audio amplification. The efficiency of the TAS5176 is greater than 90% when driving 8-Ω satellites and a 4-Ω subwoofer speaker. The TAS5176 has an innovative protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overload protection, undervoltage protection, and overtemperature protection. The TAS5176 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. A new programmable overcurrent detector allows the use of lower-cost inductors in the demodulation output filter. OUTPUT POWER vs SUPPLY VOLTAGE 35 SE, 4 W Sub THD = 10% APPLICATIONS DVD Receiver Home Theater in a Box Televisions DESCRIPTION The TAS5176 is a high-performance, six-channel, digital-amplifier power stage with an improved protection system. The TAS5176 is capable of driving a 8-Ω, single-ended load up to 15 W per each front/satellite channel and a 4-Ω, single-ended subwoofer greater than 25 W at 10% THD+N performance. PO – Output Power – W • • • 30 25 20 15 10 5 0 0 10 20 30 PVDD – Supply Voltage – V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, PurePath Digital are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TAS5176 www.ti.com SLES196 – JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION TERMINAL ASSIGNMENT The TAS5176 is available in a thermally enhanced 44-pin HTSSOP PowerPAD™ package. The heat slug is located on the bottom side of the device for convenient thermal coupling to the printed circuit board which is used as the heatsink for this device. DDW PACKAGE (TOP VIEW) PGND PWM_F GVDD_DEF VDD PWM_E PWM_D RESET M3 M2 M1 GND AGND VREG OC_ADJ SD OTW PWM_C PWM_B PWM_A GVDD_ABC BST_BIAS OUT_BIAS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 BST_F PVDD_F OUT_F PGND OUT_E PVDD_E BST_E BST_D PVDD_D OUT_D PGND PGND OUT_C PVDD_C BST_C BST_B PVDD_B OUT_B PGND OUT_A PVDD_A BST_A P0016-02 2 Submit Documentation Feedback TAS5176 www.ti.com SLES196 – JUNE 2007 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL NAME NO. TYPE (1) DESCRIPTION AGND 12 P Analog ground BST_A 23 P HS bootstrap supply (BST), capacitor to OUT_A required BST_B 29 P HS bootstrap supply (BST), external capacitor to OUT_B required BST_BIAS 21 P BIAS bootstrap supply, external capacitor to OUT_BIAS required BST_C 30 P HS bootstrap supply (BST), external capacitor to OUT_C required BST_D 37 P HS bootstrap supply (BST), external capacitor to OUT_D required BST_E 38 P HS bootstrap supply (BST), external capacitor to OUT_E required BST_F 44 P HS bootstrap supply (BST), external capacitor to OUT_F required GND 11 P Chip ground GVDD_ABC 20 P Gate drive voltage supply GVDD_DEF 3 P Gate drive voltage supply M1 10 I Mode selection pin M2 9 I Mode selection pin M3 8 I Mode selection pin OC_ADJ 14 O Overcurrent threshold programming pin, resistor to AGND required OTW 16 O Overtemperature warning open-drain output signal, active-low OUT_A 25 O Output, half-bridge A, satellite OUT_B 27 O Output, half-bridge B, satellite OUT_BIAS 22 O BIAS half-bridge output pin OUT_C 32 O Output, half-bridge C, subwoofer OUT_D 35 O Output, half-bridge D, satellite OUT_E 40 O Output, half-bridge E, satellite OUT_F 42 O Output, half-bridge F, satellite PGND 1, 26, 33, 34, 41 P Power ground PVDD_A 24 P Power-supply input for half-bridge A PVDD_B 28 P Power-supply input for half-bridge B PVDD_C 31 P Power-supply input for half-bridge C PVDD_D 36 P Power-supply input for half-bridge D PVDD_E 39 P Power-supply input for half-bridge E PVDD_F 43 P Power-supply input for half-bridge F PWM_A 19 I PWM input signal for half-bridge A PWM_B 18 I PWM input signal for half-bridge B PWM_C 17 I PWM input signal for half-bridge C PWM_D 6 I PWM input signal for half-bridge D PWM_E 5 I PWM input signal for half-bridge E PWM_F 2 I PWM input signal for half-bridge F RESET 7 I Reset signal (active-low logic) SD 15 O Shutdown open-drain output signal, active-low VDD 4 P Power supply for digital voltage regulator VREG 13 O Digital regulator supply filter pin, output (1) I = input; O = output; P = power Submit Documentation Feedback 3 TAS5176 www.ti.com SLES196 – JUNE 2007 Table 1. MODE Selection Pins MODE PINS (1) MODE M2 M3 0 0 2.1 mode Channels A, B, and C enabled; channels D, E, and F disabled 0 1 5.1 mode All channels enabled 1 0 3.0 mode BTL Mode 1 1 Reserved (1) NAME DESCRIPTION M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG. PACKAGE HEAT DISSIPATION RATINGS (1) (1) (2) PARAMETER TAS5176DDW RθJC (°C/W)—1 satellite (sat.) FET only 10.3 RθJC (°C/W)—1 subwoofer (sub.) FET only 5.2 RθJC (°C/W)—1 sat. half-bridge 5.2 RθJC (°C/W)—1 sub. half-bridge 2.6 RθJC (°C/W)—5 sat. half-bridges + 1 sub. 1.74 Typical pad area (2) 24.72 mm2 JC is junction-to-case, CH is case-to-heatsink. RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RθCH with this condition is typically 2°C/W for this package. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNITS VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V PVDD_X to PGND_X (2) –0.3 V to 50 V OUT_X to PGND_X (2) –0.3 V to 50 V BST_X to PGND_X (2) –0.3 V to 63.2 V VREG to AGND –0.3 V to 4.2 V PGND_X to GND –0.3 V to 0.3 V PGND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V RESET, SD, OTW to AGND –0.3 V to 7 V Maximum operating junction temperature range (TJ ) 0 to 125°C Storage temperature Lead temperature – 1,6 mm (1/16 inch) from case for 10 seconds 260°C Minimum PWM pulse duration, low 30 ns (1) (2) 4 –40°C to 125°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. Submit Documentation Feedback TAS5176 www.ti.com SLES196 – JUNE 2007 TYPICAL SYSTEM DIAGRAM (Single-ended Mode) BST_BIAS OUT_BIAS 3 12 V 21 22 PVDD PVDD_F GVDD_ABC BST_F 1 mF 10 mF + 4 OUT_F PGND_EF 0.1 mF 14 PGND_EF VREG PVDD_E OC_ADJ BST_E 15 kΩ 12 10 9 11 OUT_E PWM2 PWM3 PurePath Digital ? Modulator TAS5086 PWM4 PWM5 PWM6 5 6 17 18 19 VALID2 VALID1 8 33 nF 16 SAT 330 Ω 270 mF 1 mF 1 39 270 mF 22 mH 41 0.1 mF + 38 0.47 mF 40 33 nF SAT 270 mF 330 Ω 22 mH 1 mF M2 GND PVDD_D TAS5176 BST_D 36 0.1 mF + 37 0.47 mF 35 34 33 nF SAT 270 mF 330 Ω 22 mH 270 mF 1 mF PWM_F PVDD_C PWM_E BST_C PWM_D OUT_C PWM_C PGND_C 31 0.1 mF + 30 0.47 mF 32 33 33 nF RESET M3 BST_B OUT_B SD OTW PGND_AB PVDD_A BST_A OUT_A 1000 mF 330 Ω 22 mH PWM_B PWM_A SUB 1000 mF 28 1 mF 0.1 mF + 29 0.47 mF 27 33 nF 15 To mP 0.47 mF 42 M1 PVDD_B 7 + 270 mF PGND_D 2 0.1 mF 44 AGND OUT_D PWM1 43 VDD 0.1 mF 13 680 Ω GVDD_DEF 1 mF 20 33 nF SAT 270 mF 330 Ω 22 mH 26 270 mF 1 mF 24 0.1 mF + 23 0.47 mF 25 33 nF SAT 270 mF 22 mH 330 Ω 270 mF 1 mF S0061-02 Submit Documentation Feedback 5 TAS5176 www.ti.com SLES196 – JUNE 2007 TYPICAL SYSTEM DIAGRAM (BTL Mode) BST_BIAS OUT_BIAS 3 12 V PVDD_F GVDD_DEF 1 mF BST_F 20 GVDD_ABC OUT_F 1 mF 10 mF PGND_EF + 4 VDD 0.1 mF PGND_EF 21 22 33 nF PVDD 43 44 42 1.0 mF 0.1 mF 16.0 mH 33 nF 41 + 470 mF 1 0.47 mF 14 TBD kΩ 12 PVDD_E OC_ADJ BST_E AGND OUT_E 13 0.1 mF 8 10 9 11 PVDD_D VREG BST_D M3 OUT_D 39 38 40 1.0 mF 0.1 mF 16.0 mH 33 nF 36 37 35 1.0 mF 0.1 mF 16.0 mH 33 nF M1 M2 + TAS5176 PGND_D 34 470 mF GND 0.47 mF PVDD_C PWM_P_1 PWM_M_1 PWM_P_2 PurePath ? Digital Modulator TAS5504A PWM_M_2 PWM_P_4 PWM_M_4 VALID 2 5 6 17 18 19 7 PWM_F PWM_E PWM_D BST_C OUT_C PGND_C 31 30 32 1.0 mF 0.1 mF 16.0 mH 33 nF 33 PWM_C PWM_B PVDD_B PWM_A BST_B RESET OUT_B 28 29 27 1.0 mF 0.1 mF 16.0 mH 33 nF + PGND_AB 15 16 26 470 mF SD OTW 0.47 mF PVDD_A BST_A To mP OUT_A 24 23 25 0.1 mF 33 nF PurePath Digital™ 6 Submit Documentation Feedback 1.0 mF 16.0 mH TAS5176 www.ti.com SLES196 – JUNE 2007 FUNCTIONAL BLOCK DIAGRAM Undervoltage Protection OTW VDD Internal Pullup Resistors to VREG SD Protection and I/O Logic M1 M2 Power On Reset VREG VREG AGND Temperature Sense GND M3 Overload Protection RESET ISense OC_ADJ GVDD_DEF BST_F PWM_F PWM Receiver PVDD_F Control Timing Gate Drive OUT_F PGND_EF BST_E PWM_E PWM Receiver PVDD_E Control Timing Gate Drive OUT_E PGND_EF BST_D PWM_D PWM Receiver PVDD_D Control Timing Gate Drive OUT_D PGND_D GVDD_ABC BST_C PVDD_C PWM_C PWM Receiver Control Timing Gate Drive OUT_C PGND_C BST_B PVDD_B PWM_B PWM Receiver Control Timing Gate Drive OUT_B PGND_AB BST_A PVDD_A PWM_A PWM Receiver Control Timing Gate Drive OUT_A BST_BIAS Control Timing Gate Drive OUT_BIAS B0034-01 Submit Documentation Feedback 7 TAS5176 www.ti.com SLES196 – JUNE 2007 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply, SE DC supply voltage at pin(s) 0 31 34 V GVDD Gate drive and guard ring supply voltage DC voltage at pin(s) 10.8 12 13.2 V VDD Digital regulator supply DC supply voltage at pin 10.8 12 13.2 V RL,SAT Resistive load impedance, satellite channels (1) Recommended demodulation filter 6 8 Ω RL,SUB Resistive load impedance, subwoofer channel Recommended demodulation filter 3.5 4 Ω Loutput Demodulation filter inductance Minimum output inductance under short-circuit condition 5 22 μH Coutput,sat Demodulation filter capacitance 1 μF Coutput,sub Demodulation filter capacitance FPWM PWM frame rate (1) μF 1 192 384 432 kHz Load impedance outside range listed might cause shutdown due to OLP, OTE, or NLP. AUDIO SPECIFICATION (Single-Ended Operation) PVDD_X = 31 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, FPWM = 384 kHz, case temperature = 75°C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless otherwise specified. PARAMETER PO,sat Power output per satellite channel PO,sub Power output, subwoofer THD + N MIN TYP MAX RL = 8 Ω, 10% THD, clipped input signal 15 RL = 8 Ω, 0 dBFS, unclipped input signal 12 RL = 4 Ω, 10% THD, clipped input signal 25 RL = 4 Ω, 0 dBFS, unclipped input signal 22 Total harmonic distortion + noise, RL = 8 Ω, PO = 10 W satellite RL = 8 Ω, 1 W UNIT W W .1 .05 % Total harmonic distortion + noise, RL = 4 Ω, PO = 20 W subwoofer RL = 4 Ω, 1 W .05 Output integrated noise, satellite A-weighted 55 Vn Output integrated noise, subwoofer A-weighted 60 μV SNR System signal-to-noise ratio A-weighted 105 dB DNR Dynamic range (1) A-weighted, –60 dBFs input signal 105 dB Power dissipation due to idle losses (IPVDDX) PO = 0 W, all channels running 5.1 mode (2) 4.5 W PO = 0 W, 2.1 mode 2.2 W Pidle (1) (2) 8 CONDITIONS SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback .1 TAS5176 www.ti.com SLES196 – JUNE 2007 AUDIO SPECIFICATION (BTL Operation) PVDD_X = 24 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, FPWM = 384 kHz, case temperature = 75°C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless otherwise specified. PARAMETER PO,sat Power output per satellite channel PO,sub Power output subwoofer channel CONDITIONS Vn SNR Total harmonic distortion + noise RL = 8 Ω, 0 dBFS, unclipped input signal 20 RL = 6 Ω, 10% THD, clipped input signal 40 RL = 6 Ω, 0 dBFS, unclipped input signal 30 RL = 8 Ω, 1 W RL = 6 Ω, PO = 30 W MAX UNIT W W .2 .05 .2 % RL = 6 Ω, 1 W .05 Output integrated noise, satellite A-weighted 60 Output integrated noise, subwoofer A-weighted 65 System signal-to-noise ratio A-weighted 105 dB A-weighted, –60 dBFs input signal 105 dB PO = 0 W, all channels running 5.1 mode (2) 4.5 W PO = 0 W, 2.1 mode 2.2 W (1) DNR Dynamic range Pidle Power dissipation due to idle losses (IPVDDX) (1) (2) TYP 30 RL = 8 Ω, PO = 20 W THD + N MIN RL = 8 Ω, 10% THD, clipped input signal μV SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback 9 TAS5176 www.ti.com SLES196 – JUNE 2007 ELECTRICAL CHARACTERISTICS FPWM = 384 kHz, PVDD = 31V, GVDD = 12 V, VDD = 12 V, TC (case temperature) = 25°C, unless otherwise noted. All performance is in accordance with recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 3 UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION VREG Voltage regulator, only used as reference node IVDD VDD supply current IGVDD_X Gate supply current per half-bridge IPVDD_X Half-bridge idle current VDD = 12 V 3.3 3.6 Operating, 50% duty cycle 7 20 Idle, reset mode 6 16 50% duty cycle 5 22 Idle, reset mode 1 3 50% duty cycle, without output filter or load, 5.1 mode 180 50% duty cycle, without output filter or load, 2.1 mode 100 V mA mA mA OUTPUT STAGE MOSFETs RDS(on), LS Sat Drain-to-source resistance, low side, satellite TJ = 25°C, includes metallization resistance 210 mΩ RDS(on), HS Sat Drain-to-source resistance, high side, satellite TJ = 25°C, includes metallization resistance 210 mΩ RDS(on), LS Sub Drain-to-source resistance, low side, subwoofer TJ = 25°C, includes metallization resistance 110 mΩ RDS(on), HS Sub Drain-to-source resistance, high side, subwoofer TJ = 25°C, includes metallization resistance 110 mΩ I/O PROTECTION VUVP, G VUVP, hyst Undervoltage protection limit GVDD_X 10 V Undervoltage protection hysteresis 250 mV OTW (1) Overtemperature warning 125 °C OTWhyst (1) Temperature drop needed below OTW temp. for OTW to be inactive after the OTW event 25 °C OTE (1) Overtemperature error 155 °C OTEHYST (1) Temperature drop needed below OTE temp. for SD to be released after the OTE event 25 °C OLCP Overload protection counter (1) 1.25 ms Overcurrent limit protection, sat. Resistor programmable, high end, Rocp = 18 kΩ 4.5 A Overcurrent limit protection, sub. Resistor programmable, high end, Rocp = 18 kΩ 8 A IOC IOCT Overcurrent response time Rocp OC programming resistor range Resistor tolerance = 5% 210 ns 27 kΩ STATIC DIGITAL SPECIFICATION VIH High-level input voltage VIL Low-level input voltage Ilkg Input leakage current PWM_X, M1, M2, M3, RESET Static condition 2 0.8 –80 80 V μA OTW/SHUTDOWN (SD) RINT_PU Internal pullup resistor to DREG (3.3 V) for SD and OTW VOH High-level output voltage VOL Low-level output voltage FANOUT Device fanout OTW, SD (1) 10 26 Internal pullup resistor only 3.3 3.6 IO = 4 mA 0.2 0.4 No external pullup 30 External pullup: 4.7-kΩ resistor to 5 V Specified by design. Submit Documentation Feedback 3 kΩ 4.5 5 V Devices TAS5176 www.ti.com SLES196 – JUNE 2007 TYPICAL CHARACTERISTICS, 5.1 MODE TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 20 SE, 8 W PVDD = 31 V 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.007 20m 100m 500m 1 2 5 10 THD+N – Total Harmonic Distortion + Noise – % THD+N – Total Harmonic Distortion + Noise – % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 20 4W 10 SE, PVDD = 31 V 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.004 20m PO – Output Power – W 500m 1 2 5 10 30 PO – Output Power – W Figure 1. Figure 2. OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs SUPPLY VOLTAGE 18 16 100m 35 SE, 4 W Sub THD = 10% SE, 8 W Sat THD = 10% 30 PO – Output Power – W PO – Output Power – W 14 12 10 8 6 4 20 15 10 5 2 0 0 25 10 20 30 0 0 PVDD – Supply Voltage – V Figure 3. 10 20 30 PVDD – Supply Voltage – V Figure 4. Submit Documentation Feedback 11 TAS5176 www.ti.com SLES196 – JUNE 2007 OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs SUPPLY VOLTAGE 27.5 14 SE, 0 dB 4 W Sub 25 22.5 PO – Output Power – W PO – Output Power – W 12 SE, 0 dB 8 W Sat 10 8 6 4 20 17.5 15 12.5 10 7.5 5 2 2.5 0 0 0 0 10 20 30 PVDD – Supply Voltage – V Figure 5. Figure 6. SYSTEM EFFICIENCY vs TOTAL OUTPUT POWER SYSTEM POWER LOSS vs TOTAL OUTPUT POWER PVDD = 31 V 7 8 W Sat 4 W Sub 80 70 60 50 40 30 PVDD = 31 V 8 W Sat 4 W Sub 20 10 20 40 60 System Power Loss – W System Efficiency – % 30 8 90 6 5 4 3 2 1 0 0 PO – Total Output Power – W Figure 7. 12 20 PVDD – Supply Voltage – V 100 0 0 10 20 40 PO – Total Output Power – W Figure 8. Submit Documentation Feedback 60 TAS5176 www.ti.com SLES196 – JUNE 2007 OUTPUT POWER vs CASE TEMPERATURE OUTPUT POWER vs CASE TEMPERATURE 18 PO – Output Power – W 16 14 12 10 8 6 PVDD = 31 V SE, 8 W Sat 4 30 25 20 15 10 5 2 0 0 25 50 75 25 100 50 75 100 TC – Case Temperature – °C TC – Case Temperature – °C Figure 9. Figure 10. NOISE AMPLITUDE vs FREQUENCY +0 -20 Noise Amplitude – dB PO – Output Power – W PVDD = 31 V SE, 4 W Sub 35 -40 -60 -80 -100 -120 -140 0 5k 10k 15k 20k f – Frequency – kHz Figure 11. Submit Documentation Feedback 13 TAS5176 www.ti.com SLES196 – JUNE 2007 TYPICAL CHARACTERISTICS, 3.0 BTL MODE OUTPUT POWER vs SUPPLY VOLTAGE 20 10 5 45 BTL Mode PVDD = 24 V TC = 75°C 40 PO – Output Power – W THD+N – Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 2 1 0.5 8W 0.2 0.1 0.05 6W 35 30 20 100m 1 2 10 0 0 5 10 20 50 Figure 13. OUTPUT POWER vs SUPPLY VOLTAGE SYSTEM EFFICIENCY vs TOTAL POWER OUTPUT 100 BTL Mode 1 Channel TC = 75°C Unclipped Input Signal 90 80 25 20 6W 15 8W 10 70 60 50 40 BTL Mode 2 Channels = 8 W 1 Channel = 6 W PVDD = 24 V TC = 25°C 30 20 0 0 20 Figure 12. 5 10 10 20 0 0 PVDD – Supply Voltage - V Figure 14. 14 10 PVDD – Supply Voltage - V System Efficiency – % PO – Output Power – W 30 8W 15 PO – Output Power – W 35 6W 25 5 0.02 0.01 10m BTL Mode 1 Channel TC = 75°C THD+N = 10% 50 100 PO – Output Power – W Figure 15. Submit Documentation Feedback TAS5176 www.ti.com SLES196 – JUNE 2007 SYSTEM POWER LOSS vs TOTAL OUTPUT POWER OUTPUT POWER vs CASE TEMPERATURE 45 14 6W 40 PO – Output Power – W 10 8 6 BTL 2.1 Mode 2 Channels = 8 W 1 Channel = 6 W PVDD = 23 V TC = 25°C 4 2 0 0 35 30 8W 25 20 15 10 BTL Mode 1 Channel THD+N = 10% 5 0 25 50 75 50 100 100 TC – Case Temperature – °C PO – Output Power – W Figure 16. Figure 17. NOISE AMPLITUDE vs FREQUENCY +0 -20 Noise Amplitude – dB System Power Loss – W 12 -40 BTL Mode 1 Channel PVDD = 23 V RL = 8 W TC = 75°C -60 -80 -100 -120 -140 0 5k 10k 15k f – Frequency – Hz 20k Figure 18. Submit Documentation Feedback 15 TAS5176 www.ti.com SLES196 – JUNE 2007 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5176 needs only a 12-V supply in addition to a typical 31-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide outstanding electrical and acoustic characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_X) and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as power supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_X and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output voltage is high, the bootstrap capacitor voltage is shifted above the output voltage potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap capacitor. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully started during all of the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 250 kHz to 192 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system 16 reliability it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin on the same side of the PCB as the TAS5176. It is recommended to follow the PCB layout and PowerPad layout of the TAS5176 reference design. For additional information on the recommended power supply and required components, see the application diagrams given in this data sheet. The 12-V supply should be powered from a low-noise, low-output-impedance voltage regulator. Likewise, the PVDD power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical due to the internal power-on-reset circuit. Moreover, the TAS5176 is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dv/dt) are typically noncritical. SYSTEM POWER-UP/DOWN SEQUENCE The TAS5176 does not require a power-up sequence. The outputs of the H-bridge remain in a high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. When the TAS5176 is being used with TI PWM modulators such as the TAS5086, no special attention to the state of RESET is required, provided that the chipset is configured as recommended. Powering Down The TAS5176 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) threshold level (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops and clicks When the TAS5176 is being used with TI PWM modulators such as the TAS5086, no special attention to the state of RESET is required, provided that the chipset is configured as recommended. Error Reporting The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Submit Documentation Feedback TAS5176 www.ti.com SLES196 – JUNE 2007 Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see the following table). SD OTW 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) DESCRIPTION 0 1 Overload (OLP) or undervoltage (UVP) 1 0 Overtemperature warning. Junction temperature higher than 125°C, typical 1 1 Normal operation. Junction temperature lower than 125°C, typical It should be noted that asserting RESET low forces the SD and OTW signals high independently of faults being present. It is recommended to monitor the OTW signal using the system microcontroller and to respond to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device that would result in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both the SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). Device Protection System The TAS5176 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as safeguarding the device from permanent failure due to a wide range of fault conditions such as short circuit, overload, and undervoltage. The TAS5176 responds to a fault by immediately setting the power stage in a high-impedance state (Hi-Z) and asserting the SD pin low. In situations other than overload, the device automatically recovers when the fault condition has been removed, e.g., the supply voltage has increasedor the temperature has dropped. For highest possible reliability, recovering from an overload fault requires external reset of the device no sooner than 1 second after the shutdown (see the Device Reset section of this data sheet). OVERCURRENT (OC) PROTECTION WITH CURRENT LIMITING AND OVERLOAD DETECTION The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing. I.e., it performs a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load-impedance drops. If the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND. OC-Adjust Resistor Values (kΩ) Maximum Current Before OC Occurs (A) 18K 4.5 (sat), 8.0 (sub) 27K TBD It should be noted that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter at the power-stage output. Short-circuit protection is not provided directly at the output pins of the power stage but only on the speaker terminals (after the demodulation filter). It is required to follow certain guidelines when selecting the OC threshold and an appropriate demodulation inductor. • For the lowest-cost bill of materials in terms of component selection, the OC threshold current should be limited, considering the power output requirement and minimum load impedance. Higher-impedance loads require a lower OC threshold. • The demodulation filter inductor must retain at least 5 μH of inductance at twice the OC threshold setting. Most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to inductor core losses and the dc resistance of the inductor copper winding. A thorough analysis of inductor saturation and thermal properties is strongly recommended. Setting the OC threshold too low might cause issues such as lack of output power and/or unexpected shutdowns due to sensitive overload detection. In general, it is recommended to follow closely the external component selection and PCB layout as given in the application section. Submit Documentation Feedback 17 TAS5176 www.ti.com SLES196 – JUNE 2007 OVERTEMPERATURE PROTECTION The TAS5176 has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical), and If the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance state (Hi-Z) and SD being asserted low. THERMAL CONSIDERATIONS The TAS5176 device package (DDW) is designed with the PowerPad on the bottom of the device. It must be soldered to the ground plane on the printed circuit board (PCB). Under the PowerPad, there should be a pattern of vias to conduct heat through the PCB to the bottom layer ground plane. Using this technique alone, the device is capable of a total continuous power of 80 Watts. Additional heatsinking is required for total continuous power of 100 Watts. An exposed area in the bottom layer soldermask can be created and then a aluminum bracket mechanically and thermally coupled (with heatsink paste) to the exposed area. The other end of the aluminum bracket can then be mechanically and thermally connected to the system chassis. This technique will allow the TAS5176 to run at higher ambient temperatures and/or deliver more power. UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR) The UVP and POR circuits of the TAS5176 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach 10 V (typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. A rising-edge transition on the RESET input allows the device to resume operation after an overload fault. ACTIVE-BIAS CONTROL (ABC) Audible pop noises are often associated with single-rail, single-ended power stages at power-up or at the start of switching. This commonly known problem has been virtually eliminated by incorporating a proprietary active-bias control circuitry as part of the TAS5176 feature set. By the use of only a few passive external components (typically resistors), the ABC can pre-charge the dc-blocking element in the audio path, i.e., split-cap capacitors or series capacitor, to the desired potential before switching is started on the PWM outputs. (For recommended configuration, see the typical application schematic included in this data sheet). The start-up sequence can be controlled through sequencing the M3 and RESET pins according to Table 2 and Table 3. Table 2. 5.1 Mode—All Output Channels Active M3 RESET OUT_BIAS OUT_A, OUT_D, _B, _C _E, _F 0 0 Hi-Z Hi-Z Hi-Z All outputs disabled, nothing is switching. 1 0 Active Hi-Z Hi-Z OUT_BIAS enabled, all other outputs disabled 1 1 Hi-Z Active Active OUT_BIAS disabled, all other outputs switching Table 3. 2.1 Mode—Only Output Channels A, B, and C Active M3 RESET OUT_BIAS OUT_A, OUT_D, _B, _C _E, _F 0 Hi-Z Hi-Z Hi-Z All outputs disabled, nothing is switching. 1 0 Active Hi-Z Hi-Z OUT_BIAS enabled, all other outputs disabled 0 1 Hi-Z Active Hi-Z OUT_BIAS disabled, all other outputs switching Asserting the RESET input low removes any fault information to be signaled on the SD output, i.e., SD is forced high. 18 COMMENT 0 DEVICE RESET When RESET is asserted low, the output FETs in all half-bridges are forced into a high-impedance (Hi-Z) state. COMMENT Submit Documentation Feedback TAS5176 www.ti.com SLES196 – JUNE 2007 Table 4. 3.0 Mode—Output Channels In BTL Mode M3 RESET OUT_BIAS OUT_A, OUT_D, _B, _C _E, _F 0 0 Hi-Z Hi-Z Hi-Z COMMENT All outputs disabled, nothing is switching. M3 RESET OUT_BIAS OUT_A, OUT_D, _B, _C _E, _F COMMENT 1 0 Active Hi-Z Hi-Z OUT_BIAS enabled, all other outputs disabled 0 1 Hi-Z Active Hi-Z OUT_BIAS disabled, all other outputs switching When the TAS5176 is used with the TAS5086 PWM modulator, no special attention to start-up sequencing is required, provided that the chipset is configured as recommended. Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TAS5176DDW ACTIVE HTSSOP DDW 44 35 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TAS5176 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of