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TCA7408
SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
TCA7408 Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output, RESET
Input, I/O Direction Registers, and Programmable Pull-Up/Pull-Down
1 Features
3 Description
•
TCA7408 is an 8-bit I/O expander for the two-line
bidirectional bus (I2C) and is designed to provide
general-purpose remote I/O expansion through the
I2C interface.
1
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•
•
•
•
•
•
•
•
•
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Operating Power-Supply Voltage Range of 1.65 to
3.6 V
Allows Bidirectional Voltage-Level Translation and
GPIO Expansion Between 1.8-V, 2.5-V, 3.3-V
GPIO Port and
– 1.8-V SCL/SDA
– 2.5-V SCL/SDA
– 3.3-V SCL/SDA
– 5-V SCL/SDA
Standby Current Consumption of < 2 µA at 1.8 V
Active Current Consumption of:
– < 2 µA at 1.8-V 100-kHz Clock
– < 5 µA at 1.8-V 400-kHz Clock
100-kHz, 400-kHz Fast Mode
Internal Power-on-Reset and Watchdog Timer
Fail Safe I2C, INT, and RESET lines
Noise Filter on SCL/SDA and Inputs
Active-Low Reset (RESET) Input
Open-Drain Active-Low Interrupt (INT) Output
Programmable Pull-up/Pull-down Resistors for
GPIO Inputs
Programmable Edge Detection for Generating
Interrupts
Interrupt Latching
Software Reset
Input/Output Direction Register
Power Up With All Channels Configured as Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Package: µCSP 16 Ball (4 x 4), 2.0 mm x 2.0 mm,
0.5-mm pitch, 0.55-mm height
The major benefit of this device is its wide VCC range.
It can operate from 1.65 V to 3.6 V on the GPIO-port
side and 1.65 V to 5.5 V on the SDA/SCL side. This
allows the TCA7408 to interface with next-generation
microprocessors and microcontrollers on the
SDA/SCL side, where supply levels are dropping
down to conserve power.
The bidirectional voltage-level translation in the
TCA7408 is provided through VCCI. VCCI should be
connected to the VCC of the external SCL/SDA lines.
The voltage level on the GPIO-port of the TCA7408 is
determined by VCCP.
At power on, the I/Os are configured as inputs;
however, the system master can enable the I/Os as
either inputs or outputs by writing to the I/O direction
bits. The data for each input or output is kept in the
corresponding Input or Output register. All registers
can be read by the system master.
TCA7408 has open-drain interrupt (INT) output pin
that goes LOW when the input state of a GPIO-port
changes from the input-state default register value.
The device also has an interrupt masking feature by
which the user can mask the interrupt from an
individual GPIO-port.
Device Information(1)
PART NUMBER
PACKAGE
TCA7408
µCSP (16)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ZSZ Package
(Top Through View)
1
2
3
4
A
GND
GPIO7
GPIO6
GPIO5
B
VCCI
VCCP
ADDR
GPIO4
C
SDA
INT
RESET
GPIO3
D
SCL
GPIO0
GPIO1
GPIO2
2 Applications
•
•
•
Personal electronics (e.g. Smartphones, Gaming
Consoles, Personal Computers)
Servers, Routers (Telecom Switching Equipment),
Industrial Automation
Products with GPIO-Limited Processors
Not to scale
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA7408
SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
14
16
8.5 Programming........................................................... 16
8.6 Register Map........................................................... 19
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 25
10.1 Power-On Reset Requirements ........................... 25
10.2 Recommended Supply Sequencing and Ramp
Rates at TA = 25°C .................................................. 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2015) to Revision D
Page
•
Changed the ZSZ pinout image, and deleted the Top Through View table in the Pin Configuration and Functions............. 3
•
Changed Register 09h DEFAULT values From: 1111 1111 To: 0000 0000 in Register 09h – Input Default State ............ 20
Changes from Revision B (March 2013) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Removed RθJA thermal parameter with "TBD" value from Absolute Maximum Ratings table ................................................ 4
Changes from Revision A (November 2012) to Revision B
•
2
Page
Reverted document back to previous version ........................................................................................................................ 1
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SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
5 Pin Configuration and Functions
ZSZ Package
16-Pin µCSP
(Top Through View)
1
2
3
4
A
GND
GPIO7
GPIO6
GPIO5
B
VCCI
VCCP
ADDR
GPIO4
C
SDA
INT
RESET
GPIO3
D
SCL
GPIO0
GPIO1
GPIO2
Not to scale
Pin Functions
PIN
DESCRIPTION
NAME
NO.
GND
A1
Ground
GPIO7
A2
GPIO-port input/output (push-pull design structure). At power on, GPIO7 is configured as an input.
GPIO6
A3
GPIO-port input/output (push-pull design structure). At power on, GPIO6 is configured as an input.
GPIO5
A4
GPIO-port input/output (push-pull design structure). At power on, GPIO5 is configured as an input.
VCCI
B1
Supply voltage of I2C bus. Connect directly to the VCCI of the external I2C master. Provides voltage level translation.
VCCP
B2
Supply voltage of TCA7408 for GPIO-port
ADDR
B3
Address input. Connect directly to VCCI or ground.
GPIO4
B4
GPIO-port input/output (push-pull design structure). At power on, GPIO4 is configured as an input.
SDA
C1
Serial data bus. Connect to VCCI through a pull-up resistor.
INT
C2
Active-low interrupt output. Connect to VCCI through a pull-up resistor.
RESET
C3
Active-low reset input. Connect to VCCI through a pull-up resistor, if no active connection is used.
GPIO3
C4
GPIO-port input/output (push-pull design structure). At power on, GPIO3 is configured as an input.
SCL
D1
Serial clock bus. Connect to VCCI through a pull-up resistor.
GPIO0
D2
GPIO-port input/output (push-pull design structure). At power on, GPIO0 is configured as an input.
GPIO1
D3
GPIO-port input/output (push-pull design structure). At power on, GPIO1 is configured as an input.
GPIO2
D4
GPIO-port input/output (push-pull design structure). At power on, GPIO2 is configured as an input.
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SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
VCCI
VCCP
Supply voltage
MIN
MAX
–0.3
6
–0.3
4
–0.3
6
UNIT
V
VI
Input voltage
VO
Output voltage
6
V
IIK
Input clamp current
ADDR, RESET, SCL
VI < 0
±20
mA
IOK
Output clamp current
INT
VO < 0
±20
mA
IIOK
Input/output clamp current
GPIO port
VO < 0 or VO > VCCP
±20
SDA
VO < 0 or VO > VCCI
±20
IOL
Continuous output low
current
GPIO port
VO = 0 to VCCP
10
SDA, INT
VO = 0 to VCCI
10
IOH
Continuous output high
current
GPIO port
VO = 0 to VCCP
10
ICC
Tstg
(1)
(2)
–0.3
Continuous current through GND
200
Continuous current through VCCP
160
Continuous current through VCCI
10
Storage temperature
–65
150
V
mA
mA
mA
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
6.3 Recommended Operating Conditions
VCCI
VCCP
MIN
MAX
1.65
5.5
1.65
3.6
0.7 × VCCI
5.5
RESET, ADDR
0.65 × VCCI
5.5
GPIO7 to GPIO0
0.65 × VCCP
3.6
SCL, SDA
–0.3
0.3 × VCCI
RESET, ADDR
–0.3
0.35 x VCCI
GPIO7 to GPIO0
–0.3
0.35 × VCCP
Supply voltage
SCL, SDA
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
GPIO7 to GPIO0
IOL
Low-level output current
GPIO7 to GPIO0
TA
Operating free-air temperature
–40
UNIT
V
V
V
10
mA
10
mA
85
°C
6.4 Thermal Information
TCA7408
THERMAL METRIC (1)
ZSZ (µCSP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
158.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
101.2
°C/W
RθJB
Junction-to-board thermal resistance
96.8
°C/W
ψJT
Junction-to-top characterization parameter
10.8
°C/W
ψJB
Junction-to-board characterization parameter
96.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
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6.5 Electrical Characteristics
VCCI
VCCP
VIK
Input diode clamp voltage
PARAMETER
II = –18 mA
TEST CONDITIONS
1.65 to 5.5 V
1.65 to 3.6 V
VPORR
Power-on reset voltage, VCC rising (1)
VI = VCCP or GND, IO = 0
1.65 to 5.5 V
1.65 to 3.6 V
VPORF
Power-on reset voltage, VCC falling (1)
VI = VCCP or GND, IO = 0
1.65 to 5.5 V
1.65 to 3.6 V
0.75
1.65 V
1.65 V
1.2
2.3 V
2.3 V
1.8
3V
3V
2.6
1.65 V
1.65 V
1.1
2.3 V
2.3 V
1.7
3V
3V
2.5
1.65 V
1.65 V
0.45
2.3 V
2.3 V
0.25
3V
3V
0.25
1.65 V
1.65 V
0.6
2.3 V
2.3 V
0.3
3V
3V
0.25
1.65 to 5.5 V
1.65 to 3.6 V
10
2.3 to 5.5 V
2.3 to 3.6 V
20
1.65 to 5.5 V
1.65 to 3.6 V
3
VI = VCCI or GND
1.65 to 5.5 V
1.65 to 3.6 V
±0.1
VI = VCCP or GND
1.65 to 5.5 V
1.65 to 3.6 V
±0.1
VI = VCCP
1.65 to 5.5 V
1.65 to 3.6 V
1
VI = GND
1.65 to 5.5 V
1.65 to 3.6 V
1
VI on SDA, ADDR, and
RESET = VCCI or GND,
VI on GPIO port = VCCP
or GND, IO = 0, I/O =
inputs, FSCL = 400 kHz
3.6 to 5.5 V
3.6 V
10
20
2.3 to 3.6 V
2.3 to 3.6 V
6.5
15
1.65 to 2.3 V
1.65 to 2.3 V
4
9
IOH = –6 mA
VOH
GPIO-port high-level output voltage
IOH = –10 mA
IOL = 6 mA
VOL
GPIO-port low-level output voltage
IOL = 10 mA
SDA (2)
IOL
VOL = 0.4 V
INT
II
SCL, SDA, RESET, ADDR
IIH
GPIO port
IIL
Fast Mode operating mode
SDA, GPIO port,
ADDR, RESET
ICC (ICCI +
ICCP) (3)
Stand By mode
SCL, SDA, GPIO
port, ADDR, RESET
VI on SCL, SDA and
RESET = VCCI or GND,
VI on GPIO port and
ADDR = VCCI or GND, IO
= 0, I/O = inputs, FSCL =
0
MIN TYP
MAX
–1.2
UNIT
V
1.2
1.5
1
V
V
V
V
V
V
mA
3.6 to 5.5 V
3.6 V
1.5
7
2.3 to 3.6 V
2.3 to 3.6 V
1
3.2
1.65 to 2.3 V
1.65 to 2.3 V
0.5
1.7
μA
μA
μA
μA
SCL, SDA, RESET
One input at VCCI – 0.6
V. Other inputs at VCCI or
GND.
1.65 to 5.5 V
1.65 to 3.6 V
25
μA
GPIO port, ADDR
One input at VCCP – 0.6
V. Other inputs at VCCP
or GND.
1.65 to 5.5 V
1.65 to 3.6 V
80
μA
SCL
VI = VCCI or GND
1.65 to 5.5 V
1.65 to 3.6 V
SDA
VIO = VCCI or GND
GPIO port
VIO = VCCP or GND
RPU (3)
Pull up resistor
RPD (3)
Pull down resistor
ΔICCI (3)
Additional current in standby
mode
ΔICCP (3)
Ci (3)
Cio (3)
(1)
(2)
(3)
6
6
7
μA
1.65 to 5.5 V
1.65 to 3.6 V
VI = GND
1.65 to 5.5 V
1.65 to 3.6 V
100
kΩ
VI = VCCP
1.65 to 5.5 V
1.65 to 3.6 V
100
kΩ
7.5
pF
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA7408 in a reset condition until VCCP has reached
VPOR. At that time, the reset condition is released, and the TCA7408 registers and I2C/SMBus state machine initialize to their default
states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.
IOL for SDA is specified for standard mode, fast mode, and fast mode plus capability (at 2.3 V).
All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
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SCPS235D – NOVEMBER 2011 – REVISED APRIL 2018
6.6 I2C Interface Timing Requirements
STANDARD MODE
I2C BUS
PARAMETER
FAST MODE
I2C BUS
MIN
MAX
100
UNIT
MIN
MAX
0
400
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
μs
tscl
I2C clock low time
4.7
1.3
μs
2
tsp
I C spike time
tsds
I2C serial data setup time
50
tsdh
I2C serial data hold time
ticr
I2C input rise time
50
250
100
0
0
2
kHz
ns
ns
ns
1000
20 + 0.1Cb
300
ns
ticf
I C input fall time
300
20 + 0.1Cb
300
ns
tocf
I2C output fall time; 10 pF to 400 pF bus
300
20 + 0.1Cb
300
μs
tbuf
I2C bus free time between Stop and Start
2
4.7
1.3
μs
tsts
I C Start or repeater Start condition setup time
4.7
0.6
μs
tsth
I2C Start or repeater Start condition hold time
4
0.6
μs
tsps
I2C Stop condition setup time
4
0.6
μs
tvd(data)
Valid data time; SCL low to SDA output valid
1
0.3
0.9
μs
tvd(ack)
Valid data time of ACK condition; ACK signal from SCL
low to SDA (out) low
1
0.3
0.9
μs
6.7 Reset Timing Requirements
STANDARD MODE, FAST MODE,
I2C BUS
PARAMETER
UNIT
MIN
MAX
tW
Reset pulse duration
250
ns
tREC
Reset recovery time
250
ns
tRESET
Time to reset
250
ns
6.8 Switching Characteristics
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
STANDARD MODE, FAST MODE,
I2C BUS
MIN
UNIT
MAX
tiv
Interrupt valid time
GPIO port
INT
20
ns
tir
Interrupt reset delay time
SCL
INT
250
ns
tpv
Output data valid
SCL
GPIO7 to GPIO0
250
ns
tps
Input data setup time
GPIO port
SCL
0
ns
tph
Input data hold time
GPIO port
SCL
300
ns
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7 Parameter Measurement Information
VCCI
R L = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
Address
Bit 7
(MSB)
Stop
Start
Condition Condition
(P)
(S)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 x VCCI
SCL
0.3 x VCCI
ticr
tsp
ticf
tbuf
tvd
tvd
tocf
tsts
tsps
SDA
0.7 x VCCI
0.3 x VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
A.
DESCRIPTION
2
1
I C address
2
Input register port data
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF. All inputs are supplied by
generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. All parameters and
waveforms are not applicable to all devices.
Figure 1. I2C Interface Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
0
AD
DR
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
0.7 ´ VCCI
R/W
tiv
A
0.3 ´ VCCI
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
A.
Data 2
View B−B
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. All parameters and waveforms are not applicable to all devices.
Figure 2. Interrupt Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
Pn
500 Ω
DUT
2 x VCCP
CL = 50 pF
(see Note A)
500 Ω
GPIO-PORT LOAD CONFIGURATION
SCL
Bit 0
A
0.7 x VCCP
Bit 7
0.3 x VCCI
Slave
ACK
SDA
tpv
(see Note B)
GPIOn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 x VCCI
SCL
GIPO0
tps
A
GPIO7
0.3 x VCCI
tph
0.5 x VCCP
GPIOn
READ MODE (R/W = 1)
NOTE: CL includes probe and jig capacitance. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. All inputs are
supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. The outputs are
measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all
devices.
Figure 3. GPIO-Port Load Circuit And Timing Waveforms
10
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Parameter Measurement Information (continued)
VCCI
RL = 1 kΩ
500 Ω
Pn
SDA
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 x VCCP
CL = 50 pF
(see Note A)
500 Ω
GPIO-PORT LOAD CONFIGURATION
SCL
ACK or Read Cycle
Start
SDA
0.3 x VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
GPIOn
tRESET
NOTE: CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices.
Figure 4. Reset Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
TCA7408 is an 8-bit I/O expander for the two-line bidirectional bus (I2C) and is designed to provide generalpurpose remote I/O expansion through the I2C interface [serial clock (SCL) and serial data (SDA)].
The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 3.6 V on the GPIO-port side
and 1.65 V to 5.5 V on the SDA/SCL side. This allows the TCA7408 to interface with next-generation
microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve
power.
The bidirectional voltage-level translation in the TCA7408 is provided through VCCI. VCCI should be connected to
the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA7408. The voltage
level on the GPIO-port of the TCA7408 is determined by VCCP.
At power on, the I/Os are configured as inputs; however, the system master can enable the I/Os as either inputs
or outputs by writing to the I/O direction bits. The data for each input or output is kept in the corresponding Input
or Output register. All registers can be read by the system master.
The system master can reset the TCA7408 in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset (POR) puts the registers in their default state and initializes the
I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the
part. The system master can also execute a software reset by asserting bit B0 HIGH in register 01h. The POR
and hardware reset events will reset the state machine and the registers to the default state. A software reset
only resets the registers to the default state and does not reset the state machine. In addition, the watch dog
timer only resets the state machine.
The TCA7408 open-drain interrupt (INT) output is activated when any GPIO set as an input has a transition to
the state opposite of that in the Input Default State (09h) register and the corresponding bit in the Interrupt Mask
register (11h) is set to 0. It is used to indicate to the system master that an input has changed to a predetermined
state. INT is also activated after either a hardware reset or software reset. Watch dog timer does not activate the
INT pin.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate
through the I2C bus. Thus, the TCA7408 can remain a simple slave device.
One hardware pin (ADDR) can be used to program the I2C address and allow up to two devices to share the
same I2C bus or SMBus.
The integrated watchdog timer resets the I2C state machine in the event the SDA is internally held low, after 200
ms (nominal). This reset does not reset the registers as they retain their previous value.
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8.2 Functional Block Diagram
PDZ / PU
Register
Data From
Shift Reg.
D
QZ
Write PD/PU
PULL ENAB
Register
Data From
Shift Reg.
PD/PU Data
Q
OFF
D
VDD
PULL ENAB Data
Q
OFF
Write PULL ENAB
OUT STATE
Register
Data From
Shift Reg.
Q3
QZ
D
D1
Q1
ESD
Protection
Diode
OUT STATE Data
R1
Q
100k
OFF
Write OUT STATE
QZ
GPIO
OUT HIGHZ
Register
Data From
Shift Reg.
D
Q
IO DIR.
Register
D
INPUT STATUS Data
IO DIR Data
Data From
Shift Reg.
Q
D
INT MASK
Register
D
Q4
Q
GND
QZ
INT MASK Data
INT STAT
Register
INPUT DEF STATE Data
Q
D
QZ
QZ
To INTz
(One of ANDed 8)
Q
OFF
OFF
ESD
Protection
Diode
OFF
Write INT MASK
QZ
IN DEFAULT
Register
Write INPUT DEFAULT
D2
OFF
Write IO DIRECTION
Data From
Shift Reg.
100k
Q2
QZ
Write OUT HIGHZ
Data From
Shift Reg.
R2
OUT HIGHZ Data
OFF
INTERUPT STATUS Data
On power up or reset, all registers return to default values.
Figure 5. Simplified Logic Diagram (Positive Logic)
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8.3 Feature Description
Table 1. Voltage Translation
VCCI
(SCL AND SDA OF I2C MASTER)
(V)
VCCP
(GPIO-PORT)
(V)
1.8
1.8
1.8
2.5
1.8
3.3
2.5
1.8
2.5
2.5
2.5
3.3
3.3
1.8
3.3
2.5
3.3
3.3
5
1.8
5
2.5
5
3.3
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the Output Port Register. In
this case, there are low impedance paths between the I/O pin and either VCCP or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
Q4 is turned on at power-on to enable the pull-down resistor. Q3 and Q4 are enabled accordingly to the Pull-up
or Pull-down Select Register and the Pull-up or Pull-down Enable Register.
When the GPIO-port is set as an output the input buffers are disabled such that the bus is allowed to float.
8.3.2 Device Address
The address of the device is shown below in Table 2. Setting ADDR pin to GND (0) results in B[3:1] bits set as
011, and setting ADDR pin to VCCI (1) results in B[3:1] bits set as 100.
Table 2. Address Reference
ADDR
SLAVE ADDRESS
I2C BUS SLAVE ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
0
0
1
1
0 (W)
134 (decimal), 86(h)
0
1
0
0
0
0
1
1
1 (R)
135 (decimal), 87(h)
1
1
0
0
0
1
0
0
0 (W)
136 (decimal), 88(h)
1
1
0
0
0
1
0
0
1 (R)
137 (decimal), 89(h)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.3.3 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the Control Register in the TCA7408. Five bits of this data byte state the operation (read or write) and
the internal registers that will be affected. This register can be written or read through the I2C bus. The command
byte is sent only during a write transmission.
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8.3.4 Auto Increment Mode
An automatic increment feature as been added to the control register for block writes. The master can write to all
10 registers with 1 command byte being sent initially. In auto-increment mode the last five bits of the command
byte are automatically incremented after the byte is written and the next data byte is stored in the corresponding
register. Registers are written in the order shown in the Register Map section. Writes attempted to read only
registers do not change the value in the register.
If B7 = 0, all the data bytes are written to or read from the register defined by B4 through B0 in a nonincremented fashion. B6 and B5 should always be 0.
Data byte write to
Device ID and Control Register
Data byte write to
Output State Register
1000 0001, 0x02, 0x02, 0x02, …
Command byte:
B7 = 1 enables auto-increment mode
B6 = 0
B5 = 0
B4-B0 = 0 0001 points to Device ID and Control register
Data byte write to
I/O Direction Register
Figure 6. Example I2C Transaction with Auto increment Functionality Explained
8.3.5 Reset (RESET) Input
The RESET input can be asserted to initialize the system while keeping VCCP at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of tW. The TCA7408 registers and I2C/SMBus
state machine are changed to their default state once RESET is low (0). Only when RESET is high (1), GPIO
registers can be accessed by the I2C pin. This input requires a pull-up resistor to VCCI, if no active connection is
used.
8.3.6 Interrupt (INT) Output
An interrupt is generated by a rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved by reading the Interrupt Status Register. Resetting occurs
in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Each change of the I/Os after resetting is detected and is transmitted as INT. The values in the interrupt
status register are sampled on the rising edge of SCL during the read address acknowledge. If an interrupt
occurs before this event, it will be reflected in this register in the next read cycle. If an interrupt occurs very close
to this event, it may be reflected in both the current and the next read cycle. At no point is a valid interrupt ever
missed.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Default State Register.
The INT output has an open-drain structure and requires a pull-up resistor to VCCP or VCCI depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
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8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA7408 in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA7408 registers and
I2C/SMBus state machine initialize to their default states. After that, VCCP must be lowered to below VPORF and
back up to the operating voltage for a power-reset cycle.
• During power up, if VCCI ramps before VCCP, a power on reset event occurs and the I2C registers are reset.
• If VCCP ramps up before VCCI, then the device will reset as if RESET = 0
• The device is reset regardless of which VCCx ramps first.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to VCCI through a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high. After the Start condition, the device address byte is sent, most
significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 7. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 8. Bit Transfer
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Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 9. Acknowledgment on I2C Bus
8.5.2 Bus Transactions
Data is exchanged between the master and TCA7408 through write and read commands.
8.5.2.1 Writes
Data is transmitted to the TCA7408 by sending the device address and setting the least significant bit (LSB) to a
logic 0. The command byte is sent after the address and determines which register receives the data that follows
the command byte. There is no limitation on the number of data bytes sent in one write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
0
0
Command Byte
0
1
1
A
0
0
0
0
0
1
Data to Port
0
1
A
R/W ACK From Slave
Start Condition
Data 1
A
ACK From Slave
P
ACK From Slave
Write to Register
Data Out
On enabled GPIOs
Data 1 Valid
tpv
Note: Addr = 0
Figure 10. Write To Output State Register
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
1
0
0
Start Condition
0
0
1
Command Byte
1
0
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
1
1
A
Data
ACK From Slave
A
P
ACK From Slave
Note: Addr = 0
Figure 11. Write To I/O Direction Register
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Programming (continued)
8.5.2.2 Reads
The bus master first must send the TCA7408 address with the LSB set to a logic 0. The command byte is sent
after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA7408.
Data is clocked into the register on the rising edge of the ACK clock pulse.
ACK From
Slave
Slave Address
S 1
0
0
0
0
1
1
0
ACK From
Slave
Command Byte
A
R/W
A 1
ACK From
ACK From
Slave Data from Register Master
Slave Address
0
0
0
0
0 1
At this moment, master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
1
Data
1 A
A
First byte
R/W
Data from Register
Note: All registers other than interrupt status registers and
Input status registers will repeatedly read the written value
NACK From
Master
Data
NA P
Last Byte
Figure 12. Read From Register
1
SCL
2
3
4
5
6
7
8
Data From Port
Slave Address
SDA
S
1
0
0
0
1
0
Start
Condition
0
1
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
Note: ADDR = 0
Figure 13. Read From Input Status Register
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 0Fh
(read Input Status Register). This figure eliminates the command byte transfer, a restart, and slave address call
between the initial slave address call and actual data transfer from GPIO.
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8.6 Register Map
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
AI
0
0
0
0
0
0
1
01h
Device ID and Control
Read (B7-B1) Write (B0)
0100 0010
AI
0
0
0
0
0
1
1
03h
I/O Direction
Read/write byte
0000 0000
AI
0
0
0
0
1
0
1
05h
Output State
Read/write byte
0000 0000
AI
0
0
0
0
1
1
1
07h
Output High-Impedance
Read/write byte
1111 1111
AI
0
0
0
1
0
0
1
09h
Input Default State
Read/write byte
0000 0000
AI
0
0
0
1
0
1
1
0Bh
Pull-up/down Enable
Read/write byte
1111 1111
AI
0
0
0
1
1
0
1
0Dh
Pull-up/down Select
Read/write byte
0000 0000
AI
0
0
0
1
1
1
1
0Fh
Input Status
Read byte
xxxx xxxx
AI
0
0
1
0
0
0
1
11h
Interrupt Mask
Read/write byte
0000 0000
AI
0
0
1
0
0
1
1
13h
Interrupt Status
Read byte
0000 0000
8.6.1 Register Descriptions
8.6.1.1 Register 01h – Device ID and Control
The Device ID and Control register contains the manufacturer ID and firmware revision. The Control register
indicates whether the device has been reset and the default values have been set.
• The Reset Interrupt is set B1 = 1 when the device is either reset by the RESET pin, a power on reset, or
software reset.
• Reset Interrupt is then cleared after being read by the master.
• Writing to B7 – B1 has no effect on these bits in the register.
• A software reset is issued when the master writes B0=1.
• When reading from B0, the value read will always be 0.
BIT
DESCRIPTION
DEFAULT
B7
0
B6
Manufacturer ID
1
B5
B4
0
0
B3
Firmware Revision
0
B2
0
B1
Reset Interrupt
1
B0
Software Reset
0
8.6.1.2 Register 03h – I/O Direction
The I/O Direction Register configures the direction of the I/O pins.
• If a bit in this register is set to 0, the corresponding port pin is enabled as an input
• If a bit in this register is set to 1, the corresponding port pin is enabled as an output.
• When the port is set as an output the input buffers are disabled such that the bus can float.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
0
B6
GPIO6
0
B5
GPIO5
0
B4
GPIO4
0
B3
GPIO3
0
B2
GPIO2
0
B1
GPIO1
0
B0
GPIO0
0
8.6.1.3 Register 05h – Output Port Register
The Output Port Register sets the outgoing logic levels of the pins defined as outputs.
• When Bx is set to 0, GPIOx = L
• When Bx is set to 1, GPIOx = H
• Bit values in this register have no effect on pins defined as inputs
• Reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual
pin value.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
0
B6
GPIO6
0
B5
GPIO5
0
B4
GPIO4
0
B3
GPIO3
0
B2
GPIO2
0
B1
GPIO1
0
B0
GPIO0
0
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8.6.1.4 Register 07h – Output High-Impedance
The Output High-Impedance Register determines whether pins set as output are enabled or high-impedance
• When a bit in this register is set to 0, the corresponding GPIO-port output state follows register the output port
register (05h).
• When a bit in this register is set to 1, the corresponding GPIO-port output is set to high-impedance.
• Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the
value that is in the flip-flop controlling the output selection, not the actual pin value.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
1
B6
GPIO6
1
B5
GPIO5
1
B4
GPIO4
1
B3
GPIO3
1
B2
GPIO2
1
B1
GPIO1
1
B0
GPIO0
1
8.6.1.5 Register 09h – Input Default State
The Input Default State Register sets the default state of the GPIO-port input for generating interrupts.
• When a bit in this register is set to 0, the default for the corresponding input is set to LOW
• When a bit in this register is set to 1, the default for the corresponding input is set to HIGH
• Bit values in this register have no effect on pins defined as outputs. In turn, reads from this register reflect the
value that is in the flip-flop controlling the default state, not the actual pin value.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
0
B6
GPIO6
0
B5
GPIO5
0
B4
GPIO4
0
B3
GPIO3
0
B2
GPIO2
0
B1
GPIO1
0
B0
GPIO0
0
8.6.1.6 Register 0bh – Pull-Up/-Down Enable
The Pull-up/-down Enable Register enables or disables the pull-up/down resistor on the GPIO-port as defined in
the Pull-up/down Select Register (0Dh).
• When a bit in this register is set to 0, the pull-up/down on the corresponding GPIO is disabled.
• When a bit in this register is set to 1, the pull-up/down on the corresponding GPIO is enabled.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
1
B6
GPIO6
1
B5
GPIO5
1
B4
GPIO4
1
B3
GPIO3
1
B2
GPIO2
1
B1
GPIO1
1
B0
GPIO0
1
8.6.1.7 Register 0dh – Pull-Up/-Down Select
The Pull-up/down Select Register allows the user to select either a pull-up or pull-down on the GPIO-port. This
register only selects the pull-up/down resistor on the GPIO-port, while the enabling/disabling is controlled by the
Pull-up/down Enable Register (0Bh).
• When a bit in this register is set to 0, the pull-down on the corresponding GPIO is selected.
• When a bit in this register is set to 1, the pull-up on the corresponding GPIO is selected.
BIT
DESCRIPTION
DEFAULT
20
B7
GPIO7
0
B6
GPIO6
0
B5
GPIO5
0
B4
GPIO4
0
B3
GPIO3
0
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B2
GPIO2
0
B1
GPIO1
0
B0
GPIO0
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8.6.1.8 Register 0fh – Input Status Register
The Input Status Register reflects the incoming logic levels of the GPIOs set as inputs.
• The default value, X, is determined by the externally applied logic level.
• It only acts on read operation. Attempted writes to this register have no effect.
• For GPIOs set as outputs this register will read HIGH.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
X
B6
GPIO6
X
B5
GPIO5
X
B4
GPIO4
X
B3
GPIO3
X
B2
GPIO2
X
B1
GPIO1
X
B0
GPIO0
X
8.6.1.9 Register 11h – Interrupt Mask Register
The Interrupt Mask Register controls the generation of an interrupt to the INT pin when the GPIO-port input state
changes state.
• When a bit in this register is set to 0, an interrupt generated by the interrupt status register causes the INT pin
to be asserted LOW.
• When a bit in this register is set to 1, the interrupt for the corresponding GPIO is disabled. The corresponding
bit in the Interrupt Status Register (13h) will still be asserted.
• INT is not affected when GPIO-port is defined as outputs.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
0
B6
GPIO6
0
B5
GPIO5
0
B4
GPIO4
0
B3
GPIO3
0
B2
GPIO2
0
B1
GPIO1
0
B0
GPIO0
0
8.6.1.10 Register 13h – Interrupt Status Register
The Interrupt Status Register bit is asserted when the bit changes to a value opposite to the default value defined
in the Input Default State Register (09h).
• This bit is cleared and the INT pin is de-asserted upon read of this register.
• The input must be asserted back to the default state before this bit is set again.
• If the GPIO-port pin is defined as an output, this bit is never set.
• Attempted writes to this register, have no effect.
BIT
DESCRIPTION
DEFAULT
B7
GPIO7
0
B6
GPIO6
0
B5
GPIO5
0
B4
GPIO4
0
B3
GPIO3
0
B2
GPIO2
0
B1
GPIO1
0
B0
GPIO0
0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 14 shows an application in which the TCA7408 is used.
9.2 Typical Application
VCCI
VCCP
2 kΩ
RPU
VCCP
VCCI
SDA
Subsystem 1
(e.g. temperature sensor)
SDA
GPIO0
Master
controller
SCL
GPIO1
SCL
INT
GPIO2
INT
INT
TCA7408
GPIO3
GND
RESET
GPIO4
Subsystem 2
(e.g. counter)
GPIO5
RESET
GPIO6
GPIO7
ADDR
A
GND
ENABLE
B
ALARM
Subsystem 3
(e.g. alarm system)
VCCP
(1)
The SCL and SDA pins must be tied directly to VCCI because if SCL and SDA are tied to an auxiliary power supply
that could be powered on while VCCI is powered off, then the supply current, ICC, will increase as a result.
A.
Device address is configured as 86(h) or 87(h) for this example (depending on R/W bit).
B.
GPIO0, GPIO2, and GPIO3 are configured as outputs.
C.
GPIO1, GPIO4, and GPIO5 are configured as inputs.
D.
GPIO6 and GPIO7 are not used.
Figure 14. Application schematic example of TCA7408
22
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 14. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT drop
below VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 15 shows a highvalue resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
VCC
LED
100 k
VCC
LEDx
Figure 15. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
LEDx
Figure 16. Device Supplied by a Lower Voltage
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA7408, Ci for SCL or
Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.
9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC 2 V
Figure 18. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA7408 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in the figures below:
Figure 19. VCC is Lowered Below 0.2 V or 0 V and then Ramped Up to VCC
Figure 20. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tGW)
and height (tGH) are dependent on each other. The bypass capacitance, source impedance, and device
impedance are factors that affect power-on reset performance. Figure 21 provides more information on how to
measure these specifications.
Figure 21. Glitch Width And Glitch Height
VPORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state
machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or
from 0 (VPORR, VPORF). Figure 22 provides more details on this specification.
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Power-On Reset Requirements (continued)
VPORR
Figure 22. Waveform describing VCC voltage level at which power-on-reset (POR) occurs
The table below specifies the performance of the power-on reset feature for TCA7408 for both types of power-on
reset.
10.2 Recommended Supply Sequencing and Ramp Rates at TA = 25°C (1)
PARAMETER
MAX
UNIT
1
100
ms
Rise rate
0.1
100
ms
Time to re-ramp (when VCC drops to GND)
40
μs
tRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
40
μs
VCC_GH
Level that VCCP can glitch down to, but not cause a functional disruption when
VCCX_GW = 1 μs
1.2
V
tGW
Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx
10
μs
tFT
Fall rate
tRT
tRR_GND
(1)
26
MIN
TYP
Not tested. Specified by design.
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA7408, common PCB layout practices should be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs
are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away
from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry
higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling
capacitors are commonly used to control the voltage on the VCCI and VCCP pins, using a larger capacitor to
provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out highfrequency ripple. These capacitors should be placed as close to the TCA7408 as possible. These best
practices are shown in Figure 23.
For the layout example provided in Figure 23, it would be possible to fabricate a PCB with only 2 layers by
using the top layer for signal routing and the bottom layer as a split plane for power (VCCI, VCCP) and
ground (GND); however, a 4 layer board is preferable for boards with higher density signal routing. On a 4
layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground
plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes
for power and ground, vias are placed directly next to the surface mount component pad which needs to
attach to VCC or GND and the via is connected electrically to the internal layer or the other side of the board.
Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this
technique is not demonstrated in Figure 23.
11.2 Layout Example
LEGEND
By-pass/de-coupling
capacitors
VC
By-pass/de-coupling
capacitors
Via to GND plane
CP
GN
D
Partial view of plane
(inner layer)
Via to power plane
VC
CI
D
GPIO5
GPIO7
VCCI
VCCP
ADDR
SDA
INT
RESET
SCL
GPIO0
GPIO1
GPIO2
1
2
3
4
B
C
GPIO6
GND
GPIO4
G
ND
To I/Os
To processor
A
GPIO3
Figure 23. TCA7408 Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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21-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TCA7408ZSZR
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
uCSP
ZSZ
16
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SN98.5/AG1/CU0.5
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
ZUQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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