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TCA9544APWR

TCA9544APWR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP20

  • 描述:

    IC MULTIPLEXER 2 X 1:4 20TSSOP

  • 数据手册
  • 价格&库存
TCA9544APWR 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 TCA9544A Low Voltage 4-Channel I2C and SMBus Multiplexer With Interrupt Logic 1 Features 2 Applications • • • • • • • • • 1 • • • • • • • • • • • • 1-of-4 Bidirectional Translating Switches I2C Bus and SMBus Compatible Four Active-Low Interrupt Inputs Active-Low Interrupt Output Three Address Pins, Allowing up to Eight TCA9544A Devices on the I2C Bus Channel Selection Via I2C Bus Power-Up With All Switch Channels Deselected Low RON Switches Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses No Glitch on Power-Up Supports Hot Insertion Low Standby Current Operating Power Supply Voltage Range of 1.65 V to 5.5 V 5.5-V Tolerant Inputs 0 to 400-kHz Clock Frequency Latch-Up Performance Exceeds 100 mA Per JESD 78 ESD Protection Exceeds JESD 22 – 4000-V Human-Body Model (A114-A) – 1500-V Charged-Device Model (C101) Servers Routers (Telecom Switching Equipment) Factory Automation Products With I2C Slave Address Conflicts (For Example, Multiple, Identical Temp Sensors) 3 Description The TCA9544A is a 4-channel, bidirectional translating I2C Muliplexer. The master SCL/SDA signal pair is directed to one of the four channels of slave devices, SC0/SD0-SC3/SD3. Four interrupt inputs (INT3–INT0), one for each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the four interrupt inputs. A power-on reset function returns the registers to their default state and initializes the I2C state machine, with all channels deselected. The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage which will be passed by the TCA9544A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5 V tolerant. Device Information(1) PART NUMBER TCA9544A PACKAGE TSSOP (20) BODY SIZE (NOM) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic I2C or SMBus Master SDA SCL INT VCC Channel 0 SD0 SC0 INT0 SD1 SC1 INT1 (e.g. Processor) TCA9544A A0 A1 A2 GND SD2 SC2 INT1 SD3 SC3 INT3 Slaves A0, A1...AN Channel 1 Slaves B0, B1...BN Channel 2 Slaves C0, C1...CN Channel 3 Slaves D0, D1...DN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 4 5 6 6 7 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... I2C Interface Timing Requirements........................... Switching Characteristics .......................................... Interrupt Timing Requirements ................................. Typical Characteristics .............................................. Parameter Measurement Information .................. 8 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Control Register ...................................................... 11 11 11 13 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application .................................................. 16 10 Power Supply Recommendations ..................... 19 10.1 Power-On Reset Requirements ........................... 19 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History Changes from Revision B (May 2018) to Revision C • Page Changed VCC = 1.65 V to 5.5 V To: VCC = 2.5 V in Figure 15 ............................................................................................. 16 Changes from Revision A (May 2014) to Revision B Page • Changed the first paragraph of the Description...................................................................................................................... 1 • Added Tstg to the Absolute Maximum Ratings table............................................................................................................... 4 • Changed the first paragraph of the Overview section .......................................................................................................... 10 • Changed "switch" to "multiplexer" in the Feature Description section.................................................................................. 11 • Changed text in the Control Register Definition section From: "One or several SCn/SDn downstream pairs, or channels, are selected..." To: "One SCn/SDn downstream pair, or channel, is selected..."................................................ 14 Changes from Original (May 2014) to Revision A • 2 Page Updated document from PREVIEW to PRODUCTION DATA. ............................................................................................. 1 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 5 Pin Configuration and Functions PW Package Top View A0 1 20 VCC A1 2 19 SDA A2 3 18 SCL INT0 4 17 INT SD0 5 16 SC3 SC0 6 15 SD3 INT1 7 14 INT3 SD1 8 13 SC2 SC1 9 12 SD2 GND 10 11 INT2 Not to scale Pin Functions PIN NAME DESCRIPTION NO. A0 1 Address input 0. Connect directly to VCC or ground. A1 2 Address input 1. Connect directly to VCC or ground. A2 3 Address input 2. Connect directly to VCC or ground. INT0 4 Active-low interrupt input 0. Connect to VDPU0 (1) through a pull-up resistor. SD0 5 Serial data 0. Connect to VDPU0 (1) through a pull-up resistor. SC0 6 Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor. INT1 7 Active-low interrupt input 1. Connect to VDPU1 (1) through a pull-up resistor. SD1 8 Serial data 1. Connect to VDPU1 (1) through a pull-up resistor. SC1 9 Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor. GND 10 Ground INT2 11 Active-low interrupt input 2. Connect to VDPU2 (1) through a pull-up resistor. SD2 12 Serial data 2. Connect to VDPU2 (1) through a pull-up resistor. SC2 13 Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor. INT3 14 Active-low interrupt input 3. Connect to VDPU3 (1) through a pull-up resistor. SD3 15 Serial data 3. Connect to VDPU3 (1) through a pull-up resistor. SC3 16 Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor. INT 17 Active-low interrupt output. Connect to VDPUM (1) through a pull-up resistor. SCL 18 Serial clock line. Connect to VDPUM (1) through a pull-up resistor. SDA 19 Serial data line. Connect to VDPUM (1) through a pull-up resistor. VCC 20 Supply power (1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0 — VDPU3 are the slave channel reference voltages. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 3 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature (unless otherwise noted) VCC MIN MAX Supply voltage –0.5 7 (2) –0.5 UNIT V VI Input voltage II Input current ±20 7 mA V IO Output current ±25 mA Continuous current through VCC ±100 mA Continuous current through GND ±100 mA 400 mW Ptot Total power dissipation TA Operating free-air temperature range –40 85 °C Tstg Storage temperature range –65 150 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –4000 4000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –1500 1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) MIN MAX 1.65 5.5 SCL, SDA 0.7 × VCC 6 A2–A0, INT3–INT0 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A2–A0, INT3–INT0 –0.5 0.3 × VCC –40 85 UNIT V V V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.4 Thermal Information (1) over operating free-air temperature range (unless otherwise noted) TCA9544A THERMAL METRIC (1) PW UNIT 20 PIN RθJA Junction-to-ambient thermal resistance 118.2 °C/W RθJCtop Junction-to-case (top) thermal resistance 51.4 °C/W RθJB Junction-to-board thermal resistance 69.3 °C/W ψJT Junction-to-top characterization parameter 7.7 °C/W ψJB Junction-to-board characterization parameter 68.8 v (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 6.5 Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VPORR Power-on reset voltage, VCC rising No load: VI = VCC or GND VPORF Power-on reset voltage, VCC falling (3) No load: VI = VCC or GND VCC MIN TYP (2) MAX 1.2 1.5 0.8 5V 2.6 3.3 V Switch output voltage VSWin = VCC ISWout = –100 μA 3 to 3.6 V 1.65 to 1.95 V VO = VCC VOL = 0.6 V INT 2.8 1.4 1.0 1.65 to 5.5 V VOL = 0.4 V 1.8 0.5 1.1 10 3 7 6 10 A2–A0 VI = VCC or GND ±1 1.65 to 5.5 V ±1 INT3–INT0 VI = VCC or GND IO = 0 tr,max = 300 ns Operating mode fSCL = 100 kHz VI = VCC or GND IO = 0 tr,max = 1 µs ICC Low inputs VI = GND IO = 0 Standby mode High inputs INT3–INT0 Supply-current change SCL, SDA (1) (2) (3) A2–A0 INT3–INT0 μA ±1 fSCL = 400 kHz Ci mA ±1 SC3–SC0, SD3–SD0 ΔICC μA 3 SCL, SDA II V 0.8 1.65 to 5.5 V VOL = 0.4 V SDA IOL 4.5 1.6 1.8 V INT V 1.9 2.5 V 2.3 to 2.7 V IOH V 3.6 4.5 to 5.5 V Vpass 1 UNIT VI = VCC IO = 0 5.5 V 50 3.6 V 20 2.7 V 11 1.65 V 6 5.5 V 35 3.6 V 14 2.7 V 5 1.65 V 2 5.5 V 1.6 2 3.6 V 1.0 1.3 2.7 V 0.7 1.1 1.65 V 0.4 0.55 5.5 V 1.6 2 3.6 V 1.0 1.3 2.7 V 0.7 1.1 1.65 V 0.4 0.55 3 20 3 20 2 15 2 15 4.5 6 4.5 6 One INT3–INT0 input at 0.6 V, Other inputs at VCC or GND One INT3–INT0 input at VCC – 0.6 V, Other inputs at VCC or GND SCL or SDA input at 0.6 V, Other inputs at VCC or GND 1.65 to 5.5 V SCL or SDA inputs at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND 1.65 to 5.5 V μA μA pF For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges. All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA = 25°C. The power-on reset circuit resets the I2C bus logic when VCC < VPORF. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 5 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com Electrical Characteristics(1) (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER (4) Cio(OFF) SCL, SDA SC3–SC0, SD3–SD0 RON VI = VCC or GND Switch OFF VO = 0.4 V IO = 15 mA MAX 15 19 6 8 4.5 to 5.5 V 10 16 VCC 1.65 to 5.5 V 3 to 3.6 V 13 20 2.3 to 2.7 V 16 45 1.65 to 1.95 V 25 70 Switch-on resistance VO = 0.4 V (4) MIN TYP (2) TEST CONDITIONS IO = 10 mA UNIT pF Ω Cio(ON) depends on device capacitance and load that is downstream from the device. 6.6 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) STANDARD-MODE I2C BUS MIN MAX 100 FAST-MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 μs tscl I2C clock low time 4.7 1.3 μs 2 50 tsp I C spike time tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0 (1) 0 (1) μs 2 50 kHz ns ticr I C input rise time 1000 20 + 0.1Cb (2) 300 ns ticf I2C input fall time 300 20 + 0.1Cb (2) 300 ns tocf I2C output fall time (10-pF to 400-pF bus) 300 20 + 0.1Cb (2) 300 ns tbuf I2C bus free time between stop and start 2 4.7 1.3 μs tsts I C start or repeated start condition setup 4.7 0.6 μs tsth I2C start or repeated start condition hold 4 0.6 μs tsps I2C stop condition setup 4 0.6 μs (3) tvdL(Data) Valid-data time (high to low) tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low Cb I2C bus capacitive load (1) (2) (3) SCL low to SDA output low valid 1 1 μs 0.6 0.6 μs 1 1 μs 400 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5). 6.7 Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 5) PARAMETER tpd (1) Propagation delay time RON = 20 Ω, CL = 15 pF RON = 20 Ω, CL = 50 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn MIN MAX 0.3 1 UNIT ns tiv Interrupt valid time (2) INTn INT 4 μs tir Interrupt reset delay time (2) INTn INT 2 μs (1) (2) 6 The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 6). Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 6.8 Interrupt Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT tPWRL Low-level pulse duration rejection of INTn inputs (1) 1 μs tPWRH High-level pulse duration rejection of INTn inputs (1) 0.5 μs (1) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 6). 6.9 Typical Characteristics 800 1.8 VCC = 5.5V VCC = 3.3V VCC = 1.65V 1.6 ICC, Standby Mode (µA) 700 VOL (mV) 600 500 400 300 200 1.2 1 0.8 0.6 25ºC (Room Temperature) 85ºC -40ºC 0.4 100 0.2 1.5 0 0 2 4 IOL 6 (mA) 8 10 12 2 2.5 3 D003 Figure 1. SDA Output Low Voltage (VOL) vs Load Current (IOL) at Three VCC Levels 3.5 VCC (V) 4 4.5 5 5.5 D004 Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at Three Temperature Points 30 6 25ºC (Room Temperature) 85ºC -40º 5.8 5.6 25 5.4 20 RON (Ohm) CIO(OFF) (pF) 1.4 5.2 5 4.8 15 10 4.6 4.4 25ºC (Room Temperature) 85ºC -40ºC 5 4.2 0 4 0 0.5 1 1.5 2 2.5 3 VCC (V) 3.5 4 4.5 5 5.5 0 0.5 D006 Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs. Supply Voltage (VCC) at Three Temperature Points 1 1.5 2 2.5 3 VCC (V) 3.5 4 4.5 5 5.5 D001 Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at Three Temperatures Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 7 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com 7 Parameter Measurement Information VCC RL = 1 kΩ SDn, SCn DUT CL = 50 pF (See Note A) I2C-PORT LOAD CONFIGURATION Two Bytes for Complete Device Programming Address Stop Start Address Bit 7 Condition Condition Bit 6 (MSB) (P) (S) BYTE DESCRIPTION 1 I2C address + R/W 2 Control register data Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) ACK (A) Stop Condition (P) tsch 0.7 × VCC SCL ticr ticf tbuf tsp tvd(ACK) or tvdL tvdH 0.3 × VCC tsts 0.7 × VCC SDA 0.3 × VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 Parameter Measurement Information (continued) VCC RL = 4.7 kΩ DUT INT CL = 100 pF (See Note A) INTERRUPT LOAD CONFIGURATION INTn (input) 0.5 × VCC INTn (input) tir tiv INT (output) 0.5 × VCC 0.5 × VCC INT (output) VOLTAGE WAVEFORMS (tiv) 0.5 × VCC VOLTAGE WAVEFORMS (tir) NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. Figure 6. Interrupt Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 9 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com 8 Detailed Description 8.1 Overview The TCA9544A is a 4-channel, bidirectional translating I2C Muliplexer. The master SCL/SDA signal pair is directed to one of the four channels of slave devices, SC0/SD0-SC3/SD3. Four interrupt inputs (INT3–INT0), one for each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the four interrupt inputs. The device can be reset by cycling the power supply, VCC, also known as a power-on reset (POR), which resets the state machine and allows the TCA9544A to recover should one of the downstream I2C buses get stuck in a low state. A POR event will cause all channels to be deselected. The connections of the I2C data path are controlled by the same I2C master device that is switched to communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware selectable by A0-A2 pins), a single 8-bit control register is written to or read from to determine the selected channels and state of the interrupts. The TCA9544A may also be used for voltage translation, allowing the use of different bus voltages on each SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel. 8.2 Functional Block Diagram TCA9544A SC0 SC1 SC2 SC3 SD0 SD1 6 9 13 16 5 8 12 SD2 SD3 GND VCC SCL SDA INT0 INT1 INT2 INT3 10 15 Switch Control Logic 10 20 Power-on Reset 18 19 1 Input Filter 4 7 11 14 2 I2C Bus Control Interrupt Logic Submit Documentation Feedback 3 Output Filter 17 A0 A1 A2 INT Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 8.3 Feature Description The TCA9544A is a 4-channel, bidirectional translating multiplexer for I2C buses that supports Standard-Mode (100 kHz) and Fast-Mode (400 kHz) operation. The TCA9544A features I2C control using a single 8-bit control register in which the three least significant bits control the enabling and disabling of the 4 switch channels of I2C data flow. The TCA9544A also supports interrupt signals for each slave channel and this data is held in the four most significant bits of the control register. Depending on the application, voltage translation of the I2C bus can also be achieved using the TCA9544A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on the I2C bus enters a fault state, the TCA9544A can be reset to resume normal operation by means of a power-on reset which results from cycling power to the device. 8.4 Device Functional Modes 8.4.1 Power-On Reset When power is applied to VCC, an internal power-on reset holds the TCA9544A in a reset condition until VCC has reached VPORR. At this point, the reset condition is released, and the TCA9544A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below VPORF to reset the device. 8.5 Programming 8.5.1 I2C Interface The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7). SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 7. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 8). SDA SCL S P Start Condition Stop Condition Figure 8. Definition of Start and Stop Conditions Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 11 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com Programming (continued) A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master, and the devices that are controlled by the master are the slaves (see Figure 9). SDA SCL Master Transmitter/ Receiver Slave Transmitter/ Receiver Slave Receiver I2C Multiplexer Master Transmitter/ Receiver Master Transmitter Slave Figure 9. System Configuration The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 10). Setup and hold times must be taken into account. Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for ACK Start Condition Figure 10. Acknowledgment on the I2C Bus A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. Data is transmitted to the TCA9544A control register using the write mode shown in Figure 11. 12 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 Programming (continued) Slave Address SDA S 1 1 1 0 Control Register A2 A1 A0 Start Condition 0 A X X X X X B2 B1 B0 R/W ACK From Slave A ACK From Slave P Stop Condition Figure 11. Write Control Register Data is read from the TCA9544A control register using the read mode shown in Figure 12. Slave Address SDA S 1 1 1 0 A2 Control Register A1 Start Condition A0 1 A R/W INT3 INT2 INT1 INT0 B2 0 ACK From Slave B1 B0 NA NACK From Master P Stop Condition Figure 12. Read Control Register 8.6 Control Register 8.6.1 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the TCA9544A is shown in Figure 13. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. Slave Address 1 1 1 Fixed 0 A2 A1 A0 R/W Hardware Selectable Figure 13. TCA9544A Address The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected, while a logic 0 selects a write operation. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 13 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com Control Register (continued) 8.6.2 Control Register Description Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9544A, which is stored in the control register. If multiple bytes are received by the TCA9544A, it saves the last byte received. This register can be written and read via the I2C bus. Channel-Selection Bits (Read/Write) Interrupt Bits (Read Only) 7 6 5 4 INT3 INT2 INT1 INT0 3 2 1 0 X B2 B1 B0 Enable Bit INT0 INT1 INT2 INT3 Figure 14. Control Register 8.6.3 Control Register Definition Only one SCn/SDn downstream pair, or channel, can be selected by the contents of the control register (see Table 1). This register is written after the TCA9544A has been addressed. The three LSBs of the control byte are used to determine which channel (or channels) is to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur right after the acknowledge cycle. Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1) (1) 14 INT3 INT2 INT1 INT0 D3 B2 B1 B0 X X X X X 0 X X No channel selected COMMAND X X X X X 1 0 0 Channel 0 enabled X X X X X 1 0 1 Channel 1 enabled X X X X X 1 1 0 Channel 2 enabled X X X X X 1 1 1 Channel 3 enabled 0 0 0 0 0 0 0 0 No channel selected, power-up default state Only one channel may be selected at a time. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 8.6.4 Interrupt Handling The TCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When an interrupt is generated by any device, it is detected by the TCA9544A, and the interrupt output is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see Table 2). Bits 4–7 of the control register correspond to channels 0–3 of the TCA9544A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 causes bit 4 of the control register to be set on the read. The master then can address the TCA9544A and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can reconfigure the TCA9544A to select this channel and locate the device generating the interrupt and clear it. Once the device responsible for the interrupt clears, the interrupt clears. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VCC. Table 2. Control Register Read (Interrupt) (1) INT3 X X X 0 1 (1) INT2 X X 0 1 X INT1 X INT0 0 D3 B2 B1 B0 X X X X X X X X X X X X X X X X X X X X X 0 1 1 COMMAND No interrupt on channel 0 Interrupt on channel 0 No interrupt on channel 1 Interrupt on channel 1 No interrupt on channel 2 Interrupt on channel 2 No interrupt on channel 3 Interrupt on channel 3 Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt on channels 0 and 3, and there is interrupt on channels 1 and 2. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 15 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Applications of the TCA9544A will contain an I2C (or SMBus) master device and up to four I2C slave devices. The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next channel. In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave address conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design requirements must be considered (See Design Requirements and Detailed Design Procedure). 9.2 Typical Application A typical application of the TCA9544A contains anywhere from 1 to 5 separate data pull-up voltages, VDPUX , one for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the event where the master device and all slave devices operate at the same voltage, then the supply voltage can be VCC = VDPUX. In an application where voltage translation is necessary, additional design requirements must be considered (See Design Requirements). Figure 15 shows an application in which the TCA9544A can be used. VDPUM = 1.65 V to 5.5 V VCC = 2.5 V VDPU0 = 1.65 V to 5.5 V 20 SDA I2C/SMBus Master SCL VCC 19 SD0 5 SC0 6 4 SDA 18 17 SCL INT INT0 Channel 0 VDPU1 = 1.65 V to 5.5 V SD1 SC1 INT1 8 Channel 1 9 7 VDPU2 = 1.65 V to 5.5 V TCA9544A SD2 SC2 12 Channel 2 13 11 INT2 3 A2 2 A1 1 A0 10 GND SD3 SC3 INT3 VDPU3 = 1.65 V to 5.5 V 15 Channel 3 16 14 Figure 15. Typical Application Schematic 16 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 Typical Application (continued) 9.2.1 Design Requirements The pull-up resistors on the INT3-INT0 pins in the application schematic are not required in all applications. If the device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up resistor is not required. The interrupt inputs should not be left floating in the application. The A0 and A1 pins are hardware selectable to control the slave address of the TCA9544A. These pins may be tied directly to GND or VCC in the application. If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to GND on the master side will be the sum of the currents through all pull-up resistors, Rp. The pass-gate transistors of the TCA9544A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. Figure 16 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9544A to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 16, Vpass(max) is 2.7 V when the TCA9544A supply voltage is 4 V or lower, so the TCA9544A supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 15). 9.2.2 Detailed Design Procedure Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a function of VDPUX, VOL,(max), and IOL: VDPUX - VOL(max) Rp(min) = IOL (1) The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL = 400 kHz) and bus capacitance, Cb: tr Rp(max) = 0.8473 ´ Cb (2) The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9544A, Cio(OFF), the capacitance of wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 17 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com Typical Application (continued) 9.2.3 TCA9544A Application Curves 25 5 20 Rp(max) (kOhm) 4 Vpass (V) Standard-mode Fast-mode 25ºC (Room Temperature) 85ºC -40ºC 3 2 15 10 5 1 0 0 0 0.5 Space spacespace 1 1.5 2 2.5 3 VCC (V) 3.5 4 4.5 5 0 5.5 50 100 150 200 250 Cb (pF) D007 Space spacespace Standard-mode (fSCL= 100 kHz, tr = 1 µs) Figure 16. Pass-Gate Voltage (Vpass) vs Supply Voltage (VCC) at Three Temperature Points 300 350 400 450 D008 Fast-mode (fSCL= 400 kHz, tr= 300 ns) Figure 17. Maximum Pull-up resistance (Rp(max)) vs Bus Capacitance (Cb) 1.8 1.6 Rp(min) (kOhm) 1.4 1.2 1 0.8 0.6 0.4 VDPUX > 2V VDPUX 2 V Figure 18. Minimum Pull-up Resistance (Rp(min)) vs Pull-up Reference Voltage (VDPUX) 18 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 10 Power Supply Recommendations The operating power-supply voltage range of the TCA9544A is 1.65 V to 5.5 V applied at the VCC pin. When the TCA9544A is powered on for the first time or anytime the device needs to be reset by cycling the power supply, the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly. 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, TCA9544A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. A power-on reset is shown in Figure 19. VCC Ramp-Up Ramp-Down VCC_TRR VCC drops below VPORF – 50 mV Time Time to Re-Ramp VCC_FT VCC_RT Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 3 specifies the performance of the power-on reset feature for TCA9544A for both types of power-on reset. Table 3. Recommended Supply Sequencing And Ramp Rates (1) PARAMETER MIN TYP MAX UNIT VCC_FT Fall time See Figure 19 1 ms VCC_RT Rise time See Figure 19 0.1 ms VCC_TRR Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND) See Figure 19 40 μs VCC_GH Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs See Figure 20 1.2 V VCC_GW Glitch width that will not cause a functional disruption when VCC_GH = 0.5 × VCC See Figure 20 10 μs VPORF Voltage trip point of POR on falling VCC See Figure 21 0.8 1.25 V VPORR Voltage trip point of POR on rising VCC See Figure 21 1.05 1.5 V (1) All supply sequencing and ramp rate values are measured at TA = 25°C Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 19 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 20 and Table 3 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 20. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 21 and Table 3 provide more details on this specification. VCC VPORR VPORF Time POR Time Figure 21. VPOR 20 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A TCA9544A www.ti.com SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 11 Layout 11.1 Layout Guidelines For PCB layout of the TCA9544A, common PCB layout practices should be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the same layer of the board with split planes to isolate different voltage potentials. To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight). 11.2 Layout Example LEGEND Partial Power Plane Polygonal Copper Pour To I2C Master VIA to Power Plane VIA to GND Plane (Inner Layer) VDPUM Bypass/Decoupling Capacitors VCC A1 SDA A2 SCL INT0 SD0 SC0 VDPU3 INT SC3 SD3 INT3 SD1 SC2 SC1 SD2 GND INT2 GND VDPU2 To Slave Channel 2 To Slave Channel 1 INT1 VDPU1 VCC A0 TCA9544A VDPU0 To Slave Channel 3 To Slave Channel 1 GND Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A 21 TCA9544A SCPS209C – MAY 2014 – REVISED NOVEMBER 2019 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9544A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TCA9544APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW544A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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TCA9544APWR
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