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TCA9546APWR

TCA9546APWR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP16_5X4.4MM

  • 描述:

    集成电路 总线开关 TSSOP16 1.65~5.5V

  • 数据手册
  • 价格&库存
TCA9546APWR 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 TCA9546A Low Voltage 4-Channel I2C and SMBus Switch with Reset Function 1 Features 2 Applications • • • • • • • • 1 • • • • • • • • • • • • 1-of-4 Bidirectional translating switches I2C Bus and SMBus compatible Active-low reset input Three address pins, allowing up to eight TCA9546A devices on the I2C bus Channel selection via I2C Bus, in any combination Power-up with all switch channels deselected Low RON switches Allows voltage-level translation between 1.8-V, 2.5-V, 3.3-V, and 5-V buses No glitch on power-up Supports hot insertion Low standby current Operating power-supply voltage range of 1.65 V to 5.5 V 5.5 V Tolerant inputs 0 to 400-kHz Clock frequency Latch-up performance exceeds 100 mA Per JESD 78 ESD Protection exceeds JESD 22 – 4000-V Human-body model (A114-A) – 1500-V Charged-device model (C101) Servers Routers (telecom switching equipment) Factory automation Products with I2C slave address conflicts (multiple, identical temp sensors) 3 Description The TCA9546A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. An active-low reset (RESET) input allows the TCA9546A to recover from a situation in which one of the downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the channels to be deselected, as does the internal power-on reset function. The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage, which will be passed by the TCA9546A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant. Device Information (1) DEVICE NAME TCA9546A (1) PACKAGE BODY SIZE (NOM) TSSOP (16) 5.00 mm x 4.40 mm SOIC (16) 9.90 mm x 3.91 mm For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application Diagram I2C or SMBus Master (e.g. Processor) SDA SCL RESET VCC SD0 SC0 SD1 SC1 Channel 0 Slaves A0, A1...AN Channel 1 Slaves B0, B1...BN TCA9546A Channel 2 A0 A1 A2 GND SD2 SC2 Slaves C0, C1...CN Channel 3 SD3 SC3 Slaves D0, D1...DN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 Absolute Maximum Ratings .................................... 6.2 ESD Ratings.............................................................. 6.3 Recommended Operating Conditions ..................... 6.4 Thermal Information .................................................. 6.5 Electrical Characteristics.......................................... 6.6 I2C Interface Timing Requirements.......................... 6.7 Switching Characteristics......................................... 6.8 Interrupt and Reset Timing Requirements............... 6.9 Typical Characteristics .............................................. 4 4 4 4 5 6 6 7 7 Parameter Measurement Information .................. 8 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Control Register ...................................................... 11 11 11 14 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application .................................................. 16 10 Power Supply Recommendations ..................... 19 10.1 Power-On Reset Requirements ........................... 19 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History Changes from Revision A (February 2015) to Revision B Page • Changed the Pin Configuration image appearance ............................................................................................................... 3 • Changed VCC = 3.3 V to VCC = 2.5 V in Figure 15................................................................................................................ 16 Changes from Original (April 2014) to Revision A Page • Added D package to the datasheet. ...................................................................................................................................... 1 • Changed Handling Ratings table to ESD Ratings. ................................................................................................................ 4 • Added D package to the Thermal Information table. ............................................................................................................. 4 2 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 5 Pin Configuration and Functions D or PW Package TSSOP and SOIC 16 Pins Top View A0 1 16 VCC A1 2 15 SDA RE SET 3 14 SCL SD0 4 13 A2 SC0 5 12 SC3 SD1 6 11 SD3 SC1 7 10 SC2 GND 8 9 SD2 No t to scale Pin Functions PIN (1) DESCRIPTION NAME NO. A0 1 Address input 0. Connect directly to VCC or ground. A1 2 Address input 1. Connect directly to VCC or ground. RESET 3 Active low reset input. Connect to VCC or VDPUM (1) through a pull-up resistor, if not used. SD0 4 Serial data 0. Connect to VDPU0 (1) through a pull-up resistor. SC0 5 Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor. SD1 6 Serial data 1. Connect to VDPU1 (1) through a pull-up resistor. SC1 7 Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor. GND 8 Ground SD2 9 Serial data 2. Connect to VDPU2 (1) through a pull-up resistor. SC2 10 Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor. SD3 11 Serial data 3. Connect to VDPU3 (1) through a pull-up resistor. SC3 12 Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor. A2 13 Address input 2. Connect directly to VCC or ground. SCL 14 Serial clock line. Connect to VDPUM (1) through a pull-up resistor. SDA 15 Serial data line. Connect to VDPUM (1) through a pull-up resistor. VCC 16 Supply power VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C master reference voltage and VDPU0-VDPU3 are the slave channel reference voltages. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 3 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com 6 Specifications Absolute Maximum Ratings (1) 6.1 over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 7 (2) –0.5 UNIT V VI Input voltage range II Input current ±20 7 mA V IO Output current ±25 mA Continuous current through VCC ±100 mA Continuous current through GND ±100 mA 400 mW Ptot Total power dissipation TA Operating free-air temperature range –40 85 °C Tstg Storage temperature range -65 150 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Recommended Operating Conditions (1) 6.3 VCC MIN MAX 1.65 5.5 SCL, SDA 0.7 × VCC 6 A2–A0, RESET 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A2–A0, RESET –0.5 0.3 × VCC –40 85 Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) UNIT UNIT V V V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.4 Thermal Information TCA9546A THERMAL METRIC (1) D PW 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 92.3 122.3 RθJCtop Junction-to-case (top) thermal resistance 52.3 56.6 RθJB Junction-to-board thermal resistance 50.1 57.4 ψJT Junction-to-top characterization parameter 17.7 10.9 ψJB Junction-to-board characterization parameter 49.8 66.8 (1) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 Electrical Characteristics (1) 6.5 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VPORR Power-on reset voltage, VCC rising No load, VI = VCC or GND (3) VPORF Power-on reset voltage, VCC falling (4) No load, VI = VCC or GND (3) VCC MIN TYP (2) MAX 1.2 1.5 0.8 5V VSWin = VCC, ISWout = –100 μA 3 V to 3.6 V 1.6 IOL SDA 1.65 V to 5.5 V VOL = 0.6 V 2.8 1.4 1.0 1.8 V 1.65 V to 1.95 V 4.5 1.9 2.5 V 2.3 V to 2.7 V VOL = 0.4 V 1 2.6 3.3 V Switch output voltage 1.8 0.5 1.1 3 7 6 10 A2–A0 VI = VCC or GND (3) ±1 1.65 V to 5.5 V ±1 RESET VI = VCC or GND (3) IO = 0 tr,max = 300 ns Operating mode fSCL = 100 kHz VI = VCC or GND (3) IO = 0 tr,max = 1 µs ICC Low inputs VI = GND (3) IO = 0 Standby mode High inputs RESET Cio(OFF) (5) (1) (2) (3) (4) (5) SCL, SDA A2–A0 Ci μA ±1 fSCL = 400 kHz ΔICC mA ±1 SC3–SC0, SD3–SD0 Supply-current change V 0.8 SCL, SDA II V 3.6 4.5 V to 5.5 V Vpass UNIT SCL, SDA SC3–SC0, SD3–SD0 VI = VCC IO = 0 5.5 V 50 3.6 V 20 2.7 V 11 1.65 V 6 5.5 V 35 3.6 V 14 2.7 V 5 1.65 V 2 5.5 V 1.6 2 3.6 V 1.0 1.3 2.7 V 0.7 1.1 1.65 V 0.4 0.55 5.5 V 1.6 2 3.6 V 1.0 1.3 2.7 V 0.7 1.1 1.65 V 0.4 0.55 SCL or SDA input at 0.6 V, Other inputs at VCC or GND (3) 1.65 V to 5.5 V 2 15 SCL or SDA input at VCC – 0.6 V, Other inputs at VCC or GND (3) 1.65 V to 5.5 V 2 15 VI = VCC or GND (3) 1.65 V to 5.5 V VI = VCC or GND (3) Switch OFF μA μA 4.5 6 4.5 5.5 15 19 6 8 1.65 V to 5.5 V pF pF For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges. All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA = 25°C. RESET = VCC (held high) when all other input voltages, VI = GND. The power-on reset circuit resets the I2C bus logic with VCC < VPORF. Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 5 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com Electrical Characteristics(1) (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VO = 0.4 V RON IO = 15 mA Switch on-state resistance VO = 0.4 V MIN TYP (2) VCC IO = 10 mA MAX 4.5 V to 5.5 V 4 10 16 3 V to 3.6 V 5 13 20 2.3 V to 2.7 V 7 16 45 1.65 V to 1.95 V 10 25 70 UNIT Ω I2C Interface Timing Requirements 6.6 over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5) STANDARD MODE I2C BUS MIN MAX 100 fscl I2C clock frequency 0 tsch I2C clock high time 4 2 FAST MODE I2C BUS UNIT MIN MAX 0 400 0.6 4.7 kHz μs tscl I C clock low time tsp I2C spike time 1.3 tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0 (1) 0 (1) μs 50 2 μs 50 ns ticr I C input rise time 1000 20 + 0.1Cb (2) 300 ns ticf I2C input fall time 300 20 + 0.1Cb (2) 300 ns tocf I2C output fall time 300 20 + 0.1Cb (2) 300 ns 10-pF to 400-pF bus 2 tbuf I C bus free time between stop and start 4.7 1.3 μs tsts I2C start or repeated start condition setup 4.7 0.6 μs tsth I2C start or repeated start condition hold 4 0.6 μs 2 tsps I C stop condition setup tvdL(Data) Valid-data time (high to low) (3) SCL low to SDA output low valid tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid Valid-data time of ACK condition ACK signal from SCL low to SDA output low tvd(ack) 4 2 Cb I C bus capacitive load (1) 0.6 μs 1 1 μs 0.6 0.6 μs 1 1 μs 400 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5) (2) (3) 6.7 Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 5) PARAMETER tpd (1) 6 (1) Propagation delay time RON = 20 Ω, CL = 15 pF RON = 20 Ω, CL = 50 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn MIN MAX 0.3 1 UNIT ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com 6.8 SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tWL trst Pulse duration, RESET low (1) MAX UNIT 6 RESET time (SDA clear) tREC(STA) (1) MIN ns 500 Recovery time from RESET to start ns 0 ns trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. It must be a minimum of tWL. 6.9 Typical Characteristics 800 1.8 VCC = 5.5V VCC = 3.3V VCC = 1.65V 1.6 ICC, Standby Mode (µA) 700 VOL (mV) 600 500 400 300 200 1.2 1 0.8 0.6 25ºC (Room Temperature) 85ºC -40ºC 0.4 100 0.2 1.5 0 0 2 4 IOL 6 (mA) 8 10 12 2 2.5 3 D003 Figure 1. SDA Output Low Voltage (VOL) vs Load Current (IOL) at Three VCC Levels 3.5 VCC (V) 4 4.5 5 5.5 D004 Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at Three Temperature Points 30 6 25ºC (Room Temperature) 85ºC -40º 5.8 5.6 25 5.4 20 RON (Ohm) CIO(OFF) (pF) 1.4 5.2 5 4.8 15 10 4.6 4.4 25ºC (Room Temperature) 85ºC -40ºC 5 4.2 0 4 0 0.5 1 1.5 2 2.5 3 VCC (V) 3.5 4 4.5 5 5.5 0 0.5 D006 Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs. Supply Voltage (VCC) at Three Temperature Points 1 1.5 2 2.5 3 VCC (V) 3.5 4 4.5 5 5.5 D001 Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at Three Temperatures Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 7 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com 7 Parameter Measurement Information VCC RL = 1 kΩ SDn, SCn DUT CL = 50 pF (See Note 1) Copyright © 2016, Texas Instruments Incorporated I2C PORT LOAD CONFIGURATION Two Bytes for Complete Device Programming Stop Start Address Address Condition Condition Bit 7 Bit 6 (P) (S) (MSB) BYTE DESCRIPTION 1 I2C address + R/W 2 Control register data Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) Stop Condition (P) tsch 0.7 × VCC SCL tvd(ACK) or tvdL tvdH ticr ticf tbuf tsp 0.3 × VCC tsts 0.7 × VCC SDA 0.3 × VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 Parameter Measurement Information (continued) Start ACK or Read Cycle SCL SDA 30% trst 50% RESET tREC tWL Figure 6. Reset Timing Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 9 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com 8 Detailed Description 8.1 Overview The TCA9546A is a 4-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well as any combination of the four channels. The device offers an active-low RESET input which resets the state machine and allows the TCA9546A to recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a POR will cause all channels to be deselected. The connections of the I2C data path are controlled by the same I2C master device that is switched to communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected channels. The TCA9546A may also be used for voltage translation, allowing the use of different bus voltages on each SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel. 8.2 Functional Block Diagram SC0 SC1 7 SC2 10 SC3 12 SD0 4 SD1 6 SD2 9 SD3 11 GND 8 VCC 16 RESET SCL SDA 10 TCA9546A 5 3 Switch Control Logic Power-On Reset 14 15 Input Filter I2C Bus Control Submit Documentation Feedback 1 A0 2 A1 13 A2 Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 8.3 Feature Description The TCA9546A is a 4-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100 kHz) and Fast-Mode (400 kHz) operation. The TCA9546A features I2C control using a single 8-bit control register in which the four least significant bits control the enabling and disabling of the 4 switch channels of I2C data flow. Depending on the application, voltage translation of the I2C bus can also be achieved using the TCA9546A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on the I2C bus enters a fault state, the TCA9546A can be reset to resume normal operation using the RESET pin feature or by a power-on reset which results from cycling power to the device. 8.4 Device Functional Modes 8.4.1 RESET Input The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal is asserted low for a minimum of tWL, the TCA9546A resets its registers and I2C state machine and deselects all channels. The RESET input must be connected to VCC through a pull-up resistor. 8.4.2 Power-On Reset When power is applied to VCC, an internal power-on reset holds the TCA9546A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released, and the TCA9546A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below V POR to reset the device. 8.5 Programming 8.5.1 I2C Interface The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7). SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 7. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 8). Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 11 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com Programming (continued) SDA SCL S P Start Condition Stop Condition Figure 8. Definition of Start and Stop Conditions A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master, and the devices that are controlled by the master are the slaves (see Figure 9). SDA SCL Master Transmitter/ Receiver Slave Receiver Slave Transmitter/ Receiver Master Transmitter/ Receiver Master Transmitter I2C Multiplexer Slave Figure 9. System Configuration The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA line before the receiver can send an ACK bit. When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 10). Setup and hold times must be taken into account. 12 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 Programming (continued) Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for ACK Start Condition Figure 10. Acknowledgment on the I2C Bus Data is transmitted to the TCA9546A control register using the write mode shown in Figure 11. Slave Address SDA S 1 1 1 0 Control Register A2 A1 A0 Start Condition 0 A X X X X B3 B2 B1 B0 R/W ACK From Slave A ACK From Slave P Stop Condition Figure 11. Write Control Register Data is read from the TCA9546A control register using the read mode shown in Figure 12. Slave Address SDA S 1 1 1 0 Control Register A2 A1 A0 Start Condition 1 R/W A 0 0 0 0 ACK From Slave B3 B2 B1 B0 NA NACK From Master P Stop Condition Figure 12. Read Control Register Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 13 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com 8.6 Control Register 8.6.1 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the TCA9546A is shown in Figure 13. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. Slave Address 1 1 0 1 A2 A1 A0 R/W Hardware Selectable Fixed Figure 13. TCA9546A Address The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected, while a logic 0 selects a write operation. 8.6.2 Control Register Description Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9546A, which is stored in the control register (see Figure 14). If multiple bytes are received by the TCA9546A, it will save the last byte received. This register can be written and read via the I2C bus. Channel Selection Bits (Read/Write) 7 6 X X 5 X 4 3 2 1 0 X B3 B2 B1 B0 Channel 0 Channel 1 Channel 2 Channel 3 Figure 14. Control Register 8.6.3 Control Register Definition One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 1). This register is written after the TCA9546A has been addressed. The four LSBs of the control byte are used to determine which channel or channels are to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur right after the acknowledge cycle. 14 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 Control Register (continued) Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1) B7 (1) B6 B5 B4 B3 B2 X X X X X X X X X X X X X X X X X X X X 0 0 0 0 X 0 1 0 0 B1 X 0 1 B0 Channel 0 disabled 1 Channel 0 enabled X X X X X X 0 0 0 1 COMMAND 0 Channel 1 disabled Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled No channel selected, power-up/reset default state Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are disabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 15 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com 9 Application and Implementation 9.1 Application Information Applications of the TCA9546A contains an I2C (or SMBus) master device and up to four I2C slave devices. The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next channel. In an application where the I2C bus contain many additional slave devices that do not result in I2C slave address conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design requirements must be considered (See Design Requirements and Detailed Design Procedure). 9.2 Typical Application A typical application of the TCA9546A contains anywhere from 1 to 5 separate data pull-up voltages, VDPUX , one for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the event where the master device and all slave devices operate at the same voltage, then the pass voltage, Vpass = VDPUX. Once the maximum Vpass is known, Vcc can be selected easily using Figure 16. In an application where voltage translation is necessary, additional design requirements must be considered (See Design Requirements). Figure 15 shows an application in which the TCA9546A can be used. VDPUM = 1.65 V to 5.5 V VCC = 2.5 V VDPU0 = 1.65 V to 5.5 V 16 VCC SDA I2C/SMBus Master SCL 15 14 3 4 SDA SD0 SCL SC0 Channel 0 5 VDPU1 = 1.65 V to 5.5 V RESET SD1 6 SC1 7 VDPU2 = 1.65 V to 5.5 V TCA9546A SD2 SC2 Channel 1 9 Channel 2 10 VDPU3 = 1.65 V to 5.5 V 13 2 1 8 A2 A1 A0 SD3 GND SC3 11 Channel 3 12 Figure 15. TCA9546A Typical Application Schematic 16 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 Typical Application (continued) 9.2.1 Design Requirements The A0, A1, and A2 pins are hardware selectable to control the slave address of the TCA9546A. These pins may be tied directly to GND or VCC in the application. If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to GND on the master side will be the sum of the currents through all pull-up resistors, Rp. The pass-gate transistors of the TCA9546A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. Figure 16 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9546A to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 16, Vpass(max) is 2.7 V when the TCA9546A supply voltage is 4 V or lower, so the TCA9546A supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 15). 9.2.2 Detailed Design Procedure Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a function of VDPUX, VOL,(max), and IOL: VDPUX - VOL(max) Rp(min) = IOL (1) The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL = 400 kHz) and bus capacitance, Cb: tr Rp(max) = 0.8473 ´ Cb (2) The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9546A, Cio(OFF), the capacitance of wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance. Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 17 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com Typical Application (continued) 9.2.3 TCA9546A Application Curves 25 5 20 Rp(max) (kOhm) 4 Vpass (V) Standard-mode Fast-mode 25ºC (Room Temperature) 85ºC -40ºC 3 2 15 10 5 1 0 0 0 0.5 1 Standard-mode (fSCL kHz, tr 1.5 2 2.5 3 VCC (V) 3.5 4 4.5 5 0 5.5 50 100 150 200 250 Cb (pF) D007 SPACE (fSCL kHz, tr) Standard-mode (fSCL= 100 kHz, tr = 1 µs) Figure 16. Pass-Gate Voltage (Vpass) vs Supply Voltage (VCC) at Three Temperature Points 300 350 400 450 D008 Fast-mode (fSCL= 400 kHz, tr= 300 ns) Figure 17. Maximum Pull-Up resistance (Rp(max)) vs Bus Capacitance (Cb) 1.8 1.6 Rp(min) (kOhm) 1.4 1.2 1 0.8 0.6 0.4 VDPUX > 2V VDPUX 2 V Figure 18. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX) 18 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 10 Power Supply Recommendations The operating power-supply voltage range of the TCA9546A is 1.65 V to 5.5 V applied at the VCC pin. When the TCA9546A is powered on for the first time or anytime the device needs to be reset by cycling the power supply, the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly. 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, TCA9546A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. A power-on reset is shown in Figure 19. VCC Ramp-Up Ramp-Down VCC_TRR VCC drops below VPORF – 50 mV Time Time to Re-Ramp VCC_FT VCC_RT Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 2 specifies the performance of the power-on reset feature for TCA9546A for both types of power-on reset. Table 2. Recommended Supply Sequencing And Ramp Rates (1) MAX UNIT VCC_FT Fall time PARAMETER See Figure 19 1 100 ms VCC_RT Rise time See Figure 19 0.1 100 ms VCC_TRR Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND) See Figure 19 40 VCC_GH Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs See Figure 20 1.2 V VCC_GW Glitch width that will not cause a functional disruption when VCC_GH = 0.5 × VCC See Figure 20 10 μs VPORF Voltage trip point of POR on falling VCC See Figure 21 0.8 1.25 V VPORR Voltage trip point of POR on rising VCC See Figure 21 1.05 1.5 V (1) MIN TYP μs All supply sequencing and ramp rate values are measured at TA = 25°C Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 19 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 20 and Table 2 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 20. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 21 and Table 2 provide more details on this specification. VCC VPORR VPORF Time POR Time Figure 21. VPOR 20 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A TCA9546A www.ti.com SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 11 Layout 11.1 Layout Guidelines For PCB layout of the TCA9546A, common PCB layout practices should be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the same layer of the board with split planes to isolate different voltage potentials. To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) should be a short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight). 11.2 Layout Example LEGEND Partial Power Plane VIA to Power Plane Polygonal Copper Pour To I2C Master VIA to GND Plane (Inner Layer) VDPUM By-pass/De-coupling capacitors GND VCC A1 SDA RESET SCL SD0 SD1 SC1 VDPU3 A2 SC3 SD3 SC2 SD2 GND VDPU1 VDPU2 To Slave Channel 2 GND TCA9546A A0 SC0 To Slave Channel 1 VCC To Slave Channel 3 To Slave Channel 0 VDPU0 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A 21 TCA9546A SCPS205B – APRIL 2014 – REVISED NOVEMBER 2019 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation 22 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Product Folder Links: TCA9546A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TCA9546ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9546A TCA9546APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW546A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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TCA9546APWR
    •  国内价格
    • 1+6.01880
    • 10+5.02080
    • 30+4.53220
    • 100+4.03330
    • 500+3.47190

    库存:765

    TCA9546APWR
    •  国内价格
    • 1+22.72148
    • 10+19.87388
    • 50+16.48049
    • 100+14.77193
    • 250+13.63289
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    • 1000+12.04298
    • 2500+11.59211

    库存:329

    TCA9546APWR
    •  国内价格
    • 1+22.72148
    • 10+19.87388
    • 50+16.48049
    • 100+14.77193
    • 250+13.63289
    • 500+12.73115
    • 1000+12.04298
    • 2500+11.59211

    库存:329

    TCA9546APWR
    •  国内价格 香港价格
    • 1+10.050571+1.24677
    • 10+7.0156910+0.87030
    • 25+6.2577025+0.77627
    • 100+5.41839100+0.67215
    • 250+5.01852250+0.62255
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    • 1000+4.578781000+0.56800

    库存:11295

    TCA9546APWR
    •  国内价格
    • 1+2.82847

    库存:1