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TCAN1044V
SLLSFG2 – DECEMBER 2019 – REVISED DECEMBER 2019
TCAN1044V Fault-Protected CAN FD Transceiver with Standby Mode and 1.8-V IO Support
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
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Meets the requirements of ISO 11898-2:2016 and
ISO 11898-5:2007 physical layer standards
Support of classical CAN and optimized CAN FD
performance at 2, 5, and 8 Mbps
– Short and symmetrical propagation delays and
fast loop times for enhanced timing margin
– Higher data rates in loaded CAN networks
IO voltage range supports 1.7 V to 5.5 V
– Support for 1.8-V, 2.5-V, 3.3-V, and 5-V
applications
Total loop delay ≤ 210 ns
Small footprint SOT-23 package (2.9 mm x 1.60
mm)
Receiver common mode input voltage: ±12 V
Protection features:
– Bus fault protection: ±58 V
– Under-voltage protection
– Current limiting on bus pins
– TXD-dominant time-out (DTO)
– Data rates down to 9.2 kbps
– Thermal-shutdown protection (TSD)
Operating modes:
– Normal mode
– Low power standby mode supporting remote
wake-up request
Optimized behavior when unpowered
– Bus and logic pins are high impedance (no
load to operating bus or application)
– Hot-plug capable: power up/down glitch free
operation on bus and RXD output
Junction temperatures from: –40°C to 150°C
Grid infrastructure
Industrial transport (non-car & non-light truck)
Factory automation & control
Appliances
3 Description
The TCAN1044V is a high speed controller area
network (CAN) transceiver that meets the physical
layer requirements of the ISO 11898-2:2016 highspeed CAN specification.
The TCAN1044V transceiver supports both classical
CAN and CAN FD networks up to 8 megabits per
second (Mbps). The TCAN1044V includes internal
logic level translation via the VIO terminal to allow for
interfacing the transceiver IOs directly to 1.8-V, 2.5-V,
3.3-V, or 5-V logic IOs. The transceiver has a lowpower standby mode which supports remote wake-up
via the ISO 11898-2:2016 defined wake-up pattern
(WUP). The TCAN1044V transceiver also include
many protection and diagnostic features including
thermal-shutdown (TSD), TXD-dominant time-out
(DTO), supply under-voltage detection, and bus fault
protection up to ±58 V.
Device Information(1)
PART NUMBER
TCAN1044V
PACKAGE
BODY SIZE (NOM)
SOT (8)
2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
VIN
VOUT
5V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VDD
3
Port x
7
STB 8
CANH
TCAN1044V
CAN FD Controller
RXD
RXD
TXD
TXD 1
4
CANL
5
VIO
6
2
GND
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN1044V
SLLSFG2 – DECEMBER 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
4
4
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Characteristics ............................................
Supply Characteristics ..............................................
Dissipation Ratings ...................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ............................................
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
9.3 System Examples ................................................... 25
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
8.1 Overview ................................................................. 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2019
*
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5 Pin Configuration and Functions
DDF Package
8-Pin SOT
Top View
TX D
1
8
STB
GND
2
7
CA NH
VCC
3
6
CA NL
RX D
4
5
VIO
No t to scale
Pin Functions
Pins
Name
No.
Type
Description
TXD
1
Digital Input
GND
2
GND
CAN transmit data input, integrated pull-up
Ground connection
VCC
3
Supply
5-V supply voltage
RXD
4
VIO
5
Supply
IO supply voltage
CANL
6
Bus IO
Low-level CAN bus input/output line
CANH
7
Bus IO
High-level CAN bus input/output line
STB
8
Digital Input
Digital Output CAN receive data output, tri-state when powered off
Standby input for mode control, integrated pull-up
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VCC
Supply voltage
–0.3
6
V
VIO
Supply voltage IO level shifter
–0.3
6
V
VBUS
CAN Bus IO voltage CANH and CANL
–58
58
V
VDIFF
Max differential voltage between CANH and CANL
–45
45
V
VLogic_Input
Logic input terminal voltage
–0.3
6
V
VRXD
RXD output terminal voltage range
–0.3
6
V
IO(RXD)
RXD output current
–8
8
mA
TJ
Operating virtual junction temperature range
–40
150
°C
TSTG
Storage temperature
–65
150
°C
(1)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential IO bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
Human-body model (HBM), per AEC Q100-002 (1)
Electrostatic
discharge
VESD
VALUE
UNIT
HBM classification level 3A for
all pins
±3000
V
HBM classififation level 3B for
global pins CANH & CANL
±10000
V
±750
V
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings
System Level Electro-Static Discharge
(ESD) (1)
VESD
ISO 7637 ISO Pulse Transients (2)
VTran
ISO 7637 Slow transients pulse (3)
(1)
(2)
(3)
CAN bus terminals (CANH, CANL) to GND
CAN bus terminals (CANH, CANL)
CAN bus terminals (CANH, CANL) to GND
VALUE
UNIT
SAE J2962-2 per ISO 10650
Powered Contact Discharge
±8000
V
SAE J2962-2 per ISO 10650
Powered Air Discharge
±15000
V
Pulse 1
–100
V
Pulse 2a
75
V
Pulse 3a
–150
V
Pulse 3b
100
V
DCC slow transient pulse
±85
V
Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed
by OEM approved independent 3rd party, EMC report available upon request.
Tested according to IEC 62228-3:2019 CAN Transcievers, Section 6.3; standard pulses parameters defined in ISO 7637-2 (2011)
Tested according to ISO 7637-3 (2017); Electrical transient transmission by capacitive and inductive coupling via lines other than supply
lines
6.4 Recommended Operating Conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIO
Supply voltage for IO level shifter
1.7
IOH(RXD)
RXD terminal high level output current
–2
IOL(RXD)
RXD terminal low level output current
TA
Operating ambient temperature
4
–40
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5.5
UNIT
V
V
mA
2
mA
125
℃
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6.5 Thermal Characteristics
TCAN1044V
THERMAL METRIC
UNIT
DDF (SOT)
RθJA
Junction-to-ambient thermal resistance
128.1
℃/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.3
℃/W
RθJB
Junction-to-board thermal resistance
71.6
℃/W
ΨJT
Junction-to-top characterization parameter
19.7
℃/W
ΨJB
Junction-to-board characterization parameter
70.8
℃/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
℃/W
6.6 Supply Characteristics
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TYP
MAX
See Figure 5,TXD = 0 V, STB = 0 V, RL =
60 Ω, CL = open
TEST CONDITIONS
45
70
mA
See Figure 5, TXD = 0 V, STB = 0 V, RL
= 50 Ω, CL = open
49
80
mA
Recessive
See Figure 5, TXD = VCC, STB = 0 V, RL
= 50 Ω, CL = open, RCM = open
4.5
7.5
mA
Dominant with
bus fault
See Figure 5, TXD = 0 V, STB = 0 V,
CANH = CANL = ±25 V, RL = open, CL =
open
130
mA
Dominant
ICC
Supply current normal
mode
MIN
UNIT
ICC
Supply current standby mode
TXD = STB = VIO
RL = 50 Ω, CL = open
See Figure 5
0.2
1
µA
IIO
IO supply current normal
mode
Dominant
TXD = 0 V, STB= 0 V
RXD floating
125
300
µA
IIO
IO supply current normal
mode
Recessive
TXD = 0 V, STB = 0 V
RXD floating
25
48
µA
IIO
IO supply current standby mode
TXD = 0 V, STB = VIO
RXD floating
8.5
13.5
µA
UVVCC
Rising under voltage detection on VCC for protected mode
4.2
4.4
V
UVVCC
Falling under voltage detection on VCC for protected mode
4
4.25
V
UVVIO
Rising under voltage detection on VIO
1.56
1.65
V
UVVIO
Falling under voltage detection on VIO
1.51
1.59
V
3.5
1.4
6.7 Dissipation Ratings
PARAMETER
PD
Average power dissipation
Normal mode
TTSD
Thermal shutdown temperature
TTSD_HYS
Thermal shutdown hysteresis
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 5 V, VIO = 1.8 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle
squarewave, CL_RXD = 15 pF
110
mW
VCC = 5 V, VIO = 3.3 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle
squarewave, CL_RXD = 15 pF
110
mW
VCC = 5 V, VIO = 5 V, TJ= 27°C, RL = 60Ω, TXD
input = 250 kHz 50% duty cycle squarewave,
CL_RXD = 15 pF
110
mW
VCC = 5.5 V, VIO = 1.8 V, TA= 125°C, RL =
60Ω, TXD input = 2.5 MHz 50% duty cycle
squarewave, CL_RXD = 15 pF
120
mW
VCC = 5.5 V, VIO = 3.3 V, TA= 125°C, RL =
60Ω, TXD input = 2.5 MHz 50% duty cycle
squarewave, CL_RXD = 15 pF
120
mW
192
10
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6.8 Electrical Characteristics
Over recomended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver Electrical Characteristics
Dominant output voltage
normal mode
VO(DOM)
CANH
See Figure 6 and Figure 13, TXD = 0 V,
STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open,
RCM = open
CANL
See Figure 6 and Figure 13, TXD = VIO,
STB = 0 V, RL = open (no load), RCM =
open
2.75
4.5
V
0.5
2.25
V
3
V
VO(REC)
Recessive output voltage
normal mode
VSYM
Driver symmetry
(VO(CANH) + VO(CANL))/VCC
See Figure 6 and Figure 17, STB = 0 V, RL
= 60 Ω, CSPLIT = 4.7 nF, CL = open, RCM =
open, TXD = 250 kHz, 1 MHz, 2.5 MHz
0.9
1.1
V/V
VSYM_DC
DC output symmetry
(VCC - VO(CANH) - VO(CANL))
See Figure 6 and Figure 13, STB = 0 V, RL
= 60 Ω, CL = open
–400
400
mV
See Figure 6 and Figure 13, TXD = 0 V,
STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
1.5
3
V
VOD(DOM)
Differential output voltage
normal mode
Dominant
See Figure 6 and Figure 13, TXD = 0 V,
STB = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open
1.4
3.3
V
See Figure 6 and Figure 13, TXD = 0 V,
STB = 0 V, RL = 2240 Ω, CL = open
1.5
5
V
See Figure 6 and Figure 13, TXD = VIO,
STB = 0 V, RL = 60 Ω, CL = open
–120
12
mV
See Figure 6 and Figure 13, TXD = VIO,
STB = 0 V, RL = open, CL = open
–50
50
mV
-0.1
0.1
V
-0.1
0.1
V
-0.2
0.2
V
Differential output voltage
normal mode
Recessive
VOD(REC)
CANH and CANL
CANH - CANL
CANH - CANL
CANH
Bus output voltage
standby mode
VO(STB)
See Figure 6 and Figure 13, STB = VIO, RL
= open (no load), RCM = open
CANL
CANH - CANL
IOS(SS_DOM)
IOS(SS_REC)
See Figure 11 and Figure 13, STB = 0 V,
V(CANH) = -15 V to 40 V, CANL = open,
TXD = 0 V
Short-circuit steady-state output current,
dominant, normal mode
2
0.5 VCC
–115
mA
See Figure 11 and Figure 13, STB = 0 V,
V(CAN_L) = -15 V to 40 V, CANH = open,
TXD = 0 V
See Figure 11 and Figure 13, STB = 0 V,
–27 V ≤ VBUS ≤ 32 V,
Where VBUS = CANH = CANL, TXD = VIO
Short-circuit steady-state output current,
recessive, normal mode
115
mA
–6
6
mA
Receiver Electrical Characteristics
VIT
Input threshold voltage normal mode
See Figure 7, Table 1, and Table 6
STB = 0 V, -12 V ≤ VCM ≤ 12 V
500
900
mV
VIT(STB)
Input threshold standby mode
See Figure 7, Table 1, and Table 6
STB = VIO, -12 V ≤ VCM ≤ 12 V
400
1150
mV
VDOM
Normal mode dominant state differential input
voltage range
See Figure 7, Table 1, and Table 6
STB = 0 V, -12 V ≤ VCM ≤ 12 V
0.9
9
V
VREC
Normal mode recessive state differential input
voltage range
See Figure 7, Table 1, and Table 6
STB = 0 V, -12 V ≤ VCM ≤ 12 V
-4
0.5
V
VDOM(STB)
Standby mode dominant state differential input
voltage range
See Figure 7, Table 1, and Table 6
STB = VIO, -12 V ≤ VCM ≤ 12 V
1.15
9
V
VREC(STB)
Standby mode recessive state differential input
voltage range
See Figure 7, Table 1, and Table 6
STB = VIO, -12 V ≤ VCM ≤ 12 V
-4
0.4
V
VHYS
Hysteresis voltage for input threshold normal
mode
See Figure 7, Table 1, and Table 6
STB = 0 V, -12 V ≤ VCM ≤ 12 V
VCM
Common mode range normal and standby
modes
See Figure 7 and Table 6
ILKG(IOFF)
Unpowered bus input leakage current
CANH = CANL = 5 V, VCC = VIO = GND
CI
Input capacitance to ground (CANH or CANL)
CID
Differential input capacitance
RID
Differential input resistance
RIN
Single ended input resistance
(CANH or CANL)
RIN(M)
Input resistance matching
[1 – (RIN(CANH) / RIN(CANL))] × 100 %
6
100
–12
TXD = VIO
mV
12
V
5
µA
20
pF
10
pF
40
90
kΩ
TXD = VIO
STB = 0 V, -12 V ≤ VCM ≤ 12 V
20
45
kΩ
V(CAN_H) = V(CAN_L) = 5 V
–1
1
%
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Electrical Characteristics (continued)
Over recomended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXD Terminal (CAN Transmit Data Input)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input leakage current
TXD = VCC = VIO = 5.5 V
–2.5
IIL
Low-level input leakage current
TXD = 0 V, VCC= VIO = 5.5 V
ILKG(OFF)
Unpowered leakage current
TXD = 5.5 V, VCC= VIO = 0 V
CI
0.7 VIO
V
0.3 VIO
V
0
1
µA
–200
-100
–20
µA
–1
0
1
µA
6
Input Capacitance
5
VIN = 0.4×sin(2×π×2×10 ×t)+2.5 V
pF
RXD Terminal (CAN Receive Data Output)
VOH
High-level input voltage
See Figure 7, IO = –2 mA
VOL
Low-level input voltage
See Figure 7, IO = 2 mA
ILKG(OFF)
Unpowered leakage current
RXD = 5.5 V, VCC= VIO = 0 V
0.8 VIO
V
–1
0.2 VIO
V
1
µA
0
STB Terminal (Standby Mode Input)
VIH
High-level input voltage
VIL
Low-level input voltage
0.7 VIO
IIH
High-level input leakage current STB
VCC = VIO = STB = 5.5 V
IIL
Low-level input leakage current STB
VCC = VIO = 5.5 V, STB = 0 V
–20
ILKG(OFF)
Unpowered leakage current
STB = 5.5V, VCC= VIO = 0 V
–1
V
0.3 VIO
V
2
µA
–2
µA
1
µA
–2
0
6.9 Switching Characteristics
Over recomended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 8, normal mode, VIO = 2.8 V
to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD)
= 15 pF
125
210
ns
See Figure 8, normal mode, VIO = 1.7 V,
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
165
255
ns
See Figure 8, normal mode, VIO = 2.8 V
to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD)
= 15 pF
150
210
ns
See Figure 8, normal mode, VIO = 1.7 V,
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
180
255
ns
20
µs
Device Switching Characteristics
tPROP(LOOP1)
tPROP(LOOP2)
Total loop delay, driver input (TXD) to receiver
output (RXD), recessive to dominant
Total loop delay, driver input (TXD) to receiver
output (RXD), dominant to recessive
tMODE
Mode change time, from normal to standby or from
See Figure 9
standby to normal
tWK_FILTER
Filter time for a valid wake-up pattern
See Figure 15
0.5
1.8
µs
tWK_TIMEOUT
Bus wake-up timeout value
See Figure 15
0.8
6
ms
Driver Switching Characteristics
tpHR
Propagation delay time, high TXD to driver
recessive (dominant to recessive)
tpLD
Propagation delay time, low TXD to driver
dominant (recessive to dominant)
tsk(p)
Pulse skew (|tpHR - tpLD|)
tR
Differential output signal rise time
tF
Differential output signal fall time
tTXD_DTO
See Figure 6, STB = 0 V, RL = 60 Ω, CL
= 100 pF, RCM = open
See Figure 10, RL = 60 Ω, CL = 100 pF,
STB = 0 V
Dominant timeout
80
ns
70
ns
20
ns
30
ns
50
ns
1.2
4.0
ms
Receiver Switching Characteristics
tpRH
Propagation delay time, bus recessive input to
high output (dominant to recessive)
tpDL
Propagation delay time, bus dominant input to low
output (recessive to dominant)
tR
RXD output signal rise time
tF
RXD output signal fall time
See Figure 7
STB = 0 V,
CL(RXD) = 15 pF
90
ns
65
ns
10
ns
10
ns
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Switching Characteristics (continued)
Over recomended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
450
530
ns
155
210
ns
FD Timing Characteristics
tBIT(BUS)
Bit time on CAN bus output pins with tBIT(TXD) =
500 ns
tBIT(BUS)
Bit time on CAN bus output pins with tBIT(TXD) =
200 ns
tBIT(RXD)
Bit time on RXD output pins with tBIT(TXD) = 500 ns
400
550
ns
tBIT(RXD)
Bit time on RXD output pins with tBIT(TXD) = 200 ns
120
220
ns
tREC
Receiver timing symmetry with tBIT(TXD) = 500 ns
-50
20
ns
tREC
Receiver timing symmetry with tBIT(TXD) = 200 ns
-45
15
ns
8
See Figure 8, STB = 0 V, RL = 60 Ω, CL
= 100 pF, CL(RXD) = 15 pF
STB = 0 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
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6.10 Typical Characteristics
4
3
3.5
2.5
3
VOD(DOM) (V)
VOD(DOM) (V)
2
2.5
2
1.5
1.5
1
1
0.5
0.5
0
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature (qC)
VCC = 5 V
0
4.5
125
4.6
4.7
4.8
4.9
VIO = 3.3 V
5
5.1
5.2
5.3
5.4
VCC (V)
VOD(
VOD(
Temp = 25°C
RL = 60 Ω
5.5
RL = 60 Ω
Figure 2. VOD(DOM) vs VCC
Figure 1. VOD(DOM) vs Temperature
1
15
0.9
0.8
13
0.7
11
IIO (PA)
ICC (PA)
0.6
0.5
0.4
9
0.3
0.2
7
0.1
0
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature (qC)
VCC = 5 V
VIO = 3.3 V
125
5
-40
-25
-10
RL = 60 Ω
5
20
35
50
65
80
95
110
Temperature (qC)
D_IC
VCC = 5 V
Figure 3. ICC Standby vs Temperature
VIO = 3.3 V
D_II
RL = 60 Ω
Figure 4. IIO Standby vs Temperature
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7 Parameter Measurement Information
CANH
TXD
CL
RL
CANL
Figure 5. ICC Test Circuit
RCM
CANH
50%
TXD
50%
TXD
RL
CL
VOD
VCM
VCC
VO(CANH)
tpHR
tpLD
CANL
90%
RCM
0V
0.9V
VO(CANL)
VOD
0.5V
10%
tR
tF
Figure 6. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
CANL
CL_RXD
VOH
VO
90%
VO(RXD)
50%
10%
VOL
tF
tR
Figure 7. Receiver Test Circuit and Measurement
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Parameter Measurement Information (continued)
Table 1. Receiver Differential Input Voltage Threshold Test (See Figure 7)
Input
Output
VCANH
VCANL
|VID|
-11.5 V
-12.5 V
1000 mV
12.5 V
11.5 V
1000 mV
-8.55 V
-9.45 V
900 mV
9.45 V
8.55 V
900 mV
-8.25 V
-9.25 V
500 mV
9.25 V
8.25 V
500 mV
-11.8 V
-12.2 V
400 mV
12.2 V
11.8 V
400 mV
Open
Open
X
RXD
L
VOL
H
VOH
TXD
VI
70%
tLOOP2
30%
30%
CANH
0V
VI
TXD
RL
5 x tBIT(TXD)
CL
tBIT(TXD)
CANL
0V
STB
tBIT(BUS)
900mV
500mV
RXD
VDIFF
VO
CL_RXD
RXD
VOH
70%
30%
tBIT(RXD)
VOL
tLOOP1
Figure 8. Transmitter and Receiver Timing Test Circuit and Measurement
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CANH
0V
VIH
TXD
CL
RL
CANL
VI
STB
50%
STB
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
Figure 9. tMODE Test Circuit and Measurement
VIH
CANH
TXD
TXD
RL
CL
0V
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Figure 10. TXD Dominant Timeout Test Circuit and Measurement
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CANH
200 s
IOS
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 11. Driver Short-Circuit Current Test and Measurement
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8 Detailed Description
8.1 Overview
The TCAN1044V meets or exceeds the specifications of the ISO 11898-2:2016 high speed CAN (Controller Area
Network) physical layer standard. The device has been certified to the requirements of ISO 11898-2:2016 and
ISO 11898-5:2007 physical layer requirements according to the GIFT/ICT high speed CAN test specification. The
transceiver provides a number of different protection features making it ideal for the stringent industrial system
requirements while also supporting CAN FD data rates up to 8 Mbps.
8.2 Functional Block Diagram
NC or VIO
VCC
5
3
VCC or VIO
TSD
TXD
7
CANH
6
CANL
Dominant
time-out
1
VCC or VIO
STB
8
Mode Sele ct
UVP
VCC or VIO
RXD
4
Log ic Output
MUX
WUP Mon itor
Low Power Rece iver
2
GND
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8.3 Feature Description
8.3.1 Pin Description
8.3.1.1 TXD
TXD is the logic-level signal, referenced to from a CAN controller to the device.
8.3.1.2 GND
GND is the ground pin of the transceiver, it must be connected to the PCB ground.
8.3.1.3 VCC
VCC provides the 5-V nominal power supply to the CAN transceiver.
8.3.1.4 RXD
RXD is the logic-level signal, referenced to , from the TCAN1044V to a CAN controller. This pin is only driven
once VIO is present.
8.3.1.5 VIO
The VIO pin provides the digital IO voltage to match the CAN controller voltage thus avoiding the requirement for
a level shifter. It supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.
8.3.1.6 CANH and CANL
These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transceiver
and the low-voltage WUP CAN receiver.
8.3.1.7 STB (Standby)
The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either
the system processor or from a static system voltage source. If normal mode is the only intended mode of
operation than the STB pin can be tied directly to GND.
8.3.2 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 12 and Figure 13.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and
RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input
resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than
the differential voltage of a single driver.
The TCAN1044V transceiver implements a low-power standby (STB) mode which enables a third bus state
where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See
Figure 12 and Figure 13.
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Feature Description (continued)
Normal Mode
Standby Mode
Typical Bus Voltage
CANH
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
Figure 12. Bus States
CANH
2.5V
A
RXD
Bias
Unit
B
GND
CANL
A.
Normal Mode
B.
Standby Mode
Figure 13. Simplified Recessive Common Mode Bias Unit and Receiver
8.3.3 TXD Dominant Timeout (DTO)
During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising
edge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for
communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is
seen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to VCC/2 and
the RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimum
transmitted data rate may be calculated using Equation 1.
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
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Feature Description (continued)
Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Normal CAN communication
CAN Bus Signal
Driver disabled freeing bus for other nodes
%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH ZKROH QHWZRUN EXW 7;' '72
prevents this and frees the bus for communication after the time tTXD_DTO.
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
Figure 14. Example Timing Diagram for TXD Dominant Timeout
8.3.4 CAN Bus Short Circuit Current Limiting
The TCAN1044V has several protection features that limit the short circuit current when a CAN bus line is
shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant state
timeout which prevents permanently having the higher short circuit current of a dominant state in case of a
system fault. During CAN communication the bus switches between the dominant and recessive states, thus the
short circuit current may be viewed as either the current during each bus state or as a DC average current.
When selecting termination resistors or a common mode choke for the CAN design the average power rating,
IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has
forced state changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure
there is a minimum amount of recessive time on the bus even if the data field contains a high percentage of
dominant bits.
The average short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated using Equation 2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC]
(2)
Where:
• IOS(AVG) is the average short circuit current
• % Transmit is the percentage the node is transmitting CAN messages
• % Receive is the percentage the node is receiving CAN messages
• % REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• % DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
This short circuit current and the possible fault cases of the network should be taken into consideration when
sizing the power supply used to generate the transceivers VCC supply.
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Feature Description (continued)
8.3.5 Thermal Shutdown (TSD)
If the junction temperature of the TCAN1044V exceeds the thermal shutdown threshold, TTSD, the device turns
off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared
when the junction temperature of the device drops below TTSD. The CAN bus pins are biased to VCC/2 during a
TSD fault and the receiver to RXD path remains operational. If the fault condition that caused the TSD fault is still
present, the junction temperature may rise again and the device enters a TSD fault again. The TCAN1044V TSD
circuit includes hysteresis which prevents the CAN driver output from oscillating during a TSD fault. If there is
prolonged exposure to a TSD fault condition the device reliability could be affected.
8.3.6 Undervoltage Lockout
The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
Table 2. Undervoltage Lockout - TCAN1044V
(1)
VCC
VIO
> UVVCC
> UVVIO
Device State
Bus
RXD Pin
Normal
Per TXD
Mirrors bus
STB = VIO: Standby mode
Biased to GND
VIO: Remote wake request (1)
STB = GND: Protected mode
High impedance
Recessive
< UVVCC
> UVVIO
> UVVCC
< UVVIO
Protected
High impedance
High impedance
< UVVCC
< UVVIO
Protected
High impedance
High impedance
See Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
Once an undervoltage condition is cleared and the supply has returned to a valid level the TCAN1044V
transitions to normal mode after the tMODE time has expired. The host controller should not attempt to send or
receive messages until the tMODE time has expired.
8.3.7 Unpowered Device
The TCAN1044V is designed to be an ideal passive or no load to the CAN bus if the device is unpowered. The
bus pins were designed to have low leakage currents when the device is unpowered, so they do not load the
bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational.
The logic pins also have low leakage currents when the device is unpowered, so they do not load other circuits
which may remain powered.
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8.3.8 Floating pins
The TCAN1044V has internal pull-ups on critical pins which place the device into known states if the pin floats.
This internal bias should not be relied upon by design though, especially in noisy environments, but instead
should be considered a failsafe protection feature.
When a CAN controller supporting open drain outputs are used an adequate external pull-up resistor must be
used to ensure that the TXD output of the CAN controller maintains adequate bit timing to the input of the CAN
transceiver. See Table 3 for details on pin bias conditions.
Table 3. Pin Bias
Pin
Pull-up or Pull-down
Comment
TXD
Pull-up
Weakly biases TXD towards recessive to prevent bus blockage or
TXD DTO triggering
STB
Pull-up
Weakly biases STB towards low-power standby mode to prevent
excessive system power
8.4 Device Functional Modes
8.4.1 Operating Modes
The TCAN1044V has two main operating modes; normal mode and standby mode. Operating mode selection is
made by applying a high or low level to the STB pin on the TCAN1044 device.
Table 4. Operating Modes
8.4.2
STB
Device Mode
Driver
Receiver
RXD Pin
High
Low current standby mode with
bus wake-up
Disabled
Low-power receiver and bus
monitor enable
High (recessive) until valid WUP
is received
See section 8.3.3.1
Low
Normal Mode
Enabled
Enabled
Mirrors bus state
Normal Mode
This is the normal operating mode of the TCAN1044V. The CAN driver and receiver are fully operational and
CAN communication is bi-directional. The driver is translating a digital input on the TXD input to a differential
output on the bus pins. The receiver is translating the differential signal from to a digital output on the RXD
output.
8.4.3 Standby Mode
This is the low-power mode of the TCAN1044V. The CAN driver and main receiver are switched off and bidirectional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled to
allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Figure 15.
The local CAN protocol controller should monitor RXD for transitions (high-to-low) and reactivate the device to
normal mode by pulling the STB pin low. The CAN bus pins are weakly pulled to GND in this mode; see
Figure 12 and Figure 13.
In standby mode, only the VIO supply is required therefore the VCC may be switched off for additional system
level current savings.
8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
The TCAN1044V supports a remote wake-up request that is used to indicate to the host controller that the bus is
active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to
qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a
falling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN1044V.
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The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
For a dominant or recessive to be considered filtered, the bus must be in that state for more than the tWK_FILTER
time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be
generated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is always generated. See Figure 15 for the timing diagram of the wake-up pattern.
The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
The ISO 11898-2:2016 standard has defined times for a short and long wake up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the
filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implement a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this
section. See Figure 15 for the timing diagram of the wake up pattern with wake timeout feature.
Bus Wake via RXD
Request
Wake Up Pattern (WUP) received in t < tWK_Timeout
Filtered
Dominant
Waiting for
Filtered
Recessive
Filtered
Recessive
Waiting for
Filtered
Dominant
Filtered
Dominant
Bus
Bus VDiff
• tWK_FILTER
• tWK_FILTER
• tWK_FILTER
RXD
• tWK_FILTER
Filtered Dominant RXD Output
Bus Wake Via RXD Requests
Figure 15. Wake-Up Pattern (WUP) with tWK_TIMEOUT
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8.4.4 Driver and Receiver Function
The digital logic input and output levels for the TCAN1044V are CMOS levels with respect to VIO for compatibility
with protocol controllers having 1.8 V, 2.5 V, 3.3 V, or 5 V IO levels.
Table 5. Driver Function Table
Device Mode
Normal
Standby
(1)
(2)
Bus Outputs
TXD Input (1)
CANH
Driven Bus State (2)
CANL
Low
High
Low
Dominant
High or open
Hi-Z
Hi-Z
Biased recessive
X
Hi-Z
Hi-Z
Weak pull-down to
ground
X = irrelevant
For bus state and bias see Figure 12
Table 6. Receiver Function Table Normal and Standby Mode
Device Mode
CAN Differential Inputs
VID = VCANH – VCANL
VID ≥ 0.9 V
Dominant
Low
Normal
0.5 V < VID < 0.9 V
Undefined
Undefined
Bus State
RXD Pin
VID ≤ 0.5 V
Recessive
High
VID ≥ 1.15 V
Dominant
Standby
0.4 V < VID < 1.15 V
Undefined
VID ≤ 0.4 V
Recessive
High
Low if a remote wake event
occurred
See Figure 15
Any
Open (VID ≈ 0 V)
Open
High
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
The TCAN1044V transceiver can be used in applications with a host controller or FPGA that includes the link
layer portion of the CAN protocol. shows a typical application configuration for 5 V controller applications. The
bus termination is shown for illustrative purposes.
VIN
VIN
VOUT
5V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VDD
3
Port x
7
STB 8
CANH
TCAN1044V
CAN FD Controller
RXD
RXD
TXD
TXD 1
4
CANL
5
6
2
VIO
GND
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
Figure 16. Transceiver Application Using 5 V IO Connections
9.2.1 Design Requirements
9.2.1.1 CAN Termination
Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common mode voltage of the bus is desired then split termination may be used,
see Figure 17. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines.
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Typical Application (continued)
Standard Termination
Split Termination
CANH
CANH
RTERM/2
CAN
Transceiver
RTERM
CAN
Transceiver
RTERM/2
CANL
CSPLIT
CANL
Figure 17. CAN Bus Termination Concepts
9.2.2 Detailed Design Procedures
9.2.2.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A high number of nodes requires a transceiver with high input impedance such as the TCAN1044V.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading of
the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, and NMEA
2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output must
be greater than 1.5 V. The TCAN1044V is specified to meet the 1.5-V requirement down to 50 Ω and is specified
to meet 1.4-V differential output at 45Ω bus load. The differential input resistance of the TCAN1044V is a
minimum of 40 kΩ. If 100 TCAN1044V transceivers are in parallel on a bus, this is equivalent to a 400-Ω
differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of approximately 52
Ω. Therefore, the TCAN1044V theoretically supports over 100 transceivers on a single bus segment. However,
for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings,
timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is
often lower. Bus length may also be extended beyond 40 meters by careful system design and data rate
tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with changes in
the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
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Typical Application (continued)
Node 1
Node 2
Node 2
System Controller
System Controller
System Controller
CAN FD
Controller
CAN FD
Controller
CAN FD
Controller
TCAN1046V-Q1
TCAN1044V
TCAN1044V
Node n
(with termination)
System Contoller
CAN FD
Controller
TCAN1048V-Q1
RTERM
RTERM
RTERM
RTERM
Figure 18. Typical CAN Bus
9.2.3 Application Curves
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
VCC = 5 V
Figure 19. tPROP(LOOP1)
24
VIO = 3.3 V
RL = 60 Ω
Figure 20. tPROP(LOOP2)
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9.3 System Examples
The TCAN1044V CAN transceiver is typically used in applications with a host controller or FPGA that includes
the link layer portion of the CAN protocol. A 1.8 V, 2.5 V, or 3.3 V application is shown in . The bus termination is
shown for illustrative purposes.
VIN
VIN
VOUT
5V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VDD
3
Port x
VOUT
1.8 V / 2.5 V / 3.3 V
Regulator
(e.g. TPSxxxx)
CANH
TCAN1044V
CAN FD Controller
VIN
7
STB 8
RXD
RXD
TXD
TXD 1
4
CANL
5
6
2
VIO
GND
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
Figure 21. Typical Transceiver Application Using 1.8 V, 2.5 V, 3.3 V IO Connections
10 Power Supply Recommendations
The TCAN1044V transceiver is designed to operate with a main VCC input voltage supply range between 4.5 V
and 5.5 V. The TCAN1044V implements an IO level shifting supply input, VIO, designed for a range between 1.8
V and 5.5 V. Both supply inputs must be well regulated. A decoupling capacitance, typically 100 nF, should be
placed near the CAN transceiver's main VCC supply pin in addition to bypass capacitors. A decoupling capacitor,
typically 100 nF, should be placed near the CAN transceiver's VIO supply pin in addition to bypass capacitors.
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11 Layout
Robust and reliable CAN node design may require special layout techniques depending on the application and
industrial design requirements. Since transient disturbances have high frequency content and a wide bandwidth,
high-frequency layout techniques should be applied during PCB design.
11.1 Layout Guidelines
•
•
•
•
•
•
Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and
noise from propagating onto the board. This layout example shows a optional transient voltage suppression
(TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of
the transceiver. This example also shows optional bus filter capacitors C4 and C5.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
Use VCC and GND planes to provide low inductance. Note that high frequency current follows the path of
least impedance and not the path of least resistance.
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize trace and via inductance.
This layout example shows how split termination could be implemented on the CAN node. The termination is
split into two resistors, R2 and R3, with the center or split tap of the termination connected to ground via
capacitor C3. Split termination provides common mode filtering for the bus. See CAN Termination, CAN Bus
Short Circuit Current Limiting, and Equation 2 for information on termination concepts and power ratings
needed for the termination resistor(s).
11.2 Layout Example
µC V
TXD
R1
STB
C4
STB
GND
CANH
VCC
CANL
R2
GND
C3
C1
VCC
RXD
GND
Choke
VIO
µC V
C2
D1
J1
R3
C5
Figure 22. Layout Example
26
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TCAN1044V
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 7. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TCAN1044V
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCAN1044VDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
27RF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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