THS3095DDAG4

THS3091, THS3095 SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 THS309x High-Voltage, Low-Distortion, Current-Feedback Operational Amplifiers 1 Features 3 Description • The THS3091 and THS3095 are high-voltage, lowdistortion, high-speed, current-feedback amplifiers designed to operate over a wide supply range of ±5 V to ±15 V for applications requiring large, linear output signals such as pin drivers, power FET drivers & arbitrary waveform generators. • • • • • The THS3095 features a power-down pin (PD) that puts the amplifier in low power standby mode, and lowers the quiescent current from 9.5 mA to 500 μA. The wide supply range, combined with total harmonic distortion as low as –69 dBc at 10 MHz, in addition to the high slew rate of 7300 V/μs makes the THS309x ideally suited for high-voltage arbitrary waveform driver applications. Moreover, having the ability to handle large voltage swings driving into high-resistance and high-capacitance loads while maintaining good settling time performance makes the devices ideal for Pin driver and Power FET driver applications. 2 Applications • • • • High-voltage arbitrary waveform generators Power FET drivers Pin drivers VDSL line drivers The THS3091 and THS3095 are offered in an 8-pin SOIC (D), and the 8-pin SOIC (DDA) packages with PowerPAD™. The THS3091 is also offered in an additional 8-pin HVSSOP (DGN) package. Package Information(1)(3) PART NUMBER PACKAGE THS309x BODY SIZE (NOM) D (SOIC, 8) 4.90 mm × 3.91 mm DDA (SO PowerPAD, 8) 4.89 mm × 3.90 mm DGN (HVSSOP, 8)(2) 3.00 mm × 3.00 mm (1) (2) (3) For all available packages, see the orderable addendum at the end of the data sheet. Preview package See Device Comparison Table −20 − + THS3091 VOUT IOUT1 DAC5686 IOUT2 − + − + THS3091 THS4271 − + THS3091 Typical Arbitrary Waveform Generator Output Drive Circuit Total Harmonic Distortion − dBc • Low distortion: – 77-dBc HD2 at 10 MHz, RL = 1 kΩ – 69-dBc HD3 at 10 MHz, RL = 1 kΩ Low noise: – 14-pA/√ Hz noninverting current noise – 17-pA/√ Hz inverting current noise – 2-nV/√ Hz voltage noise High slew rate: 7300 V/μs (G = 5, VO = 20 VPP) Wide bandwidth: 210 MHz (G = 2, RL = 100 Ω) High output current drive: ±250 mA Wide supply range: ±5 V to ±15 V Power-down feature: THS3095 only −30 −40 G = 5, RF = 1 kW, RL = 100 W, VS = ±15 V VO = 20 VPP VO = 10 VPP −50 −60 VO = 5 VPP −70 −80 VO = 2 VPP −90 100 k 1M 10 M 100 M f − Frequency − Hz Total Harmonic Distortion vs Frequency An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics THS3091............................ 6 7.6 Electrical Characteristics THS3095............................ 8 7.7 Dissipation Ratings Table..........................................12 7.8 Typical Characteristics (±15 V)................................. 13 7.9 Typical Characteristics (±5 V)................................... 20 8 Detailed Description......................................................24 8.1 Overview................................................................... 24 8.2 Feature Description...................................................24 8.3 Device Functional Modes..........................................25 9 Application and Implementation.................................. 28 9.1 Application Information............................................. 28 9.2 Typical Application.................................................... 31 10 Power Supply Recommendations..............................34 11 Layout........................................................................... 34 11.1 Layout Guidelines................................................... 34 11.2 Layout Example...................................................... 35 11.3 PowerPAD Design Considerations..........................37 11.4 PowerPAD Layout Considerations.......................... 38 11.5 Power Dissipation and Thermal Considerations..... 39 12 Device and Documentation Support..........................40 12.1 Device Support....................................................... 40 12.2 Documentation Support.......................................... 40 12.3 Receiving Notification of Documentation Updates..40 12.4 Support Resources................................................. 40 12.5 Trademarks............................................................. 40 12.6 Electrostatic Discharge Caution..............................40 12.7 Glossary..................................................................41 13 Mechanical, Packaging, and Orderable Information.................................................................... 41 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (October 2015) to Revision I (December 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added the DGN package information to the data sheet..................................................................................... 1 • Added the Device Comparison Table section..................................................................................................... 3 • Updated Thermal Information table.................................................................................................................... 5 Changes from Revision G (February, 2007) to Revision H (October 2015) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 Changes from Revision F (February, 2007) to Revision G (February, 2007) Page • Changed common-mode rejection ratio specifications from 78 dB (typ) to 69 dB (typ); from 68 dB at +25°C to 62 dB; from 65 dB at (0°C to +70°C) and (–40°C to +85°C) to 59 dB................................................................ 6 • Corrected load resistor value for output current specification (sourcing and sinking) from RL = 40 Ω to RL = 10 Ω......................................................................................................................................................................... 8 • Changed output current (sourcing) specifications from 200 mA (typ) to 180 mA (typ); from 160 mA at +25°C to 140 mA; from 140 mA at (0°C to +70°C) and (–40°C to +85°C) to 120 mA................................................... 8 • Corrected output current (sinking) specifications from 180 mA (typ) to –160 mA (typ); from 150 mA at +25°C to –140 mA; from 125 mA at (0°C to +70°C) and (–40°C to +85°C) to –120 mA............................................... 8 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 5 Device Comparison Table LINEAR OUTPUT CURRENT (mA) SUPPLY, VS (V) SSBW, AV = 5 (MHz) MAXIMUM ICC AT 25°C (mA) INPUT NOISE Vn (nV/√ Hz) THS3491 ±15 900 17.3 1.7 –76/–75 7100(1) ±420 THS3095 ±15 190 9.5 1.6 –40/–42 1200(2) ±250 THS3001 ±15 350 9 1.6 N/A 1400(3) ±120 N/A 1060(4) ±140 THS3061 (1) (2) (3) (4) HD2/3, 10 VPP AT 50 MHz, SLEW RATE G = 5 V/V (V/µs) (dBc) DEVICE ±15 260 8.3 2.6 Slew rate from FPBW of 320 MHz, 10 VPP Slew rate from FPBW of 135 MHz, 4 VPP Slew rate from FPBW of 32 MHz, 20 VPP Slew rate from FPBW of 120 MHz, 4 VPP Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 3 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 6 Pin Configuration and Functions NC VIN− VIN+ VS− 1 8 NC 2 7 3 6 4 5 VS+ VOUT NC REF VIN− VIN+ VS− Figure 6-1. D, DGN, or DDA Package, 8-Pin SOIC, HVSSOP, or SO-PowerPAD THS3091 (Top View) 1 8 2 7 3 6 4 5 PD VS+ VOUT NC Figure 6-2. D or DDA Package, 8-Pin SOIC or SO-PowerPAD THS3095 (Top View) Table 6-1. Pin Functions PIN NAME DESCRIPTION THS3091 THS3095 NC 1, 5, 8 5 — PD — 8 I Amplifier power down, LOW – Amplifier disabled, HIGH (default) – Amplifier enabled REF — 1 I Voltage reference input to set PD threshold level VOUT 6 6 O Output of amplifier VIN- 2 2 I Inverting input VIN+ 3 3 I Noninverting input VS– 4 4 POW Negative power supply VS+ 7 7 POW Positive power supply (1) 4 TYPE(1) NO. No connection I= input, O = output, POW= power, and NC = no internal connection Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN VS- to VS+ Supply voltage VI Input voltage VID Differential input voltage IO Output current MAX UNIT 33 V ±VS Continuous power dissipation 4 ±V 350 mA See Section 7.2 TJ Maximum junction temperature 150 °C TJ (2) Maximum junction temperature, continuous operation, long-term reliability 125 °C Tstg Storage temperature 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Supply voltage TA MIN NOM MAX Dual supply ±5 ±15 ±16 Single supply 10 30 32 Operating free-air temperature –40 UNIT 85 V °C 7.4 Thermal Information THS309x THERMAL METRIC(1) D (SOIC) DDA (SO PowerPAD) DGN (HVSSOP) 8 PINS 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 113.5 51.8 60.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 57.7 58.3 87.2 °C/W RθJB Junction-to-board thermal resistance 54.2 32.3 32.6 °C/W ψJT Junction-to-top characterization parameter 11.5 12.2 7.8 °C/W ψJB Junction-to-board characterization parameter 53.7 32.2 32.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 7.8 17.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 5 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.5 Electrical Characteristics THS3091 VS = ±15 V, RF = 1.21 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE G = 1, RF = 1.78 kΩ, VO = 200 mVPP TA = 25°C 235 G = 2, RF = 1.21 kΩ, VO = 200 mVPP TA = 25°C 210 G = 5, RF = 1 kΩ, VO = 200 mVPP TA = 25°C 190 G = 10, RF = 866 Ω, VO = 200 mVPP TA = 25°C 180 0.1-dB Bandwidth flatness G = 2, RF = 1.21 kΩ, VO = 200 mVPP TA = 25°C 95 Large-signal bandwidth G = 5, RF = 1 kΩ , VO = 4 VPP TA = 25°C 135 G = 2, VO = 10-V step, RF = 1.21 kΩ TA = 25°C 5000 G = 5, VO = 20-V step, RF = 1 kΩ TA = 25°C 7300 Small-signal bandwidth, –3 dB Slew rate (25% to 75% level) Rise and fall time G = 2, VO = 5-VPP, RF = 1.21 kΩ TA = 25°C 5 Settling time to 0.1% G = –2, VO = 2 VPP step TA = 25°C 42 Settling time to 0.01% G = –2, VO = 2 VPP step TA = 25°C 72 MHz V/μs ns ns HARMONIC DISTORTION 2nd Harmonic distortion 3rd Harmonic distortion G = 2, RF = 1.21 kΩ, VO = 2 VPP, f = 10 MHz RL = 100 Ω TA = 25°C 66 RL = 1 kΩ TA = 25°C 77 RL = 100 Ω TA = 25°C 74 RL = 1 kΩ dBc TA = 25°C 69 Input voltage noise f > 10 kHz TA = 25°C 2 nV / √ Hz Noninverting input current noise f > 10 kHz TA = 25°C 14 pA / √ Hz Inverting input current noise f > 10 kHz pA / √ Hz Differential gain G = 2, RL = 150 Ω, RF = 1.21 kΩ Differential phase TA = 25°C 17 NTSC TA = 25°C 0.013% PAL TA = 25°C 0.011% NTSC TA = 25°C 0.020° PAL TA = 25°C 0.026° DC PERFORMANCE TA = 25°C Transimpedance VO = ±7.5 V, Gain = 1 350 TA = 0°C to 70°C 300 TA = –40°C to 85°C 300 TA = 25°C Input offset voltage VCM = 0 V 850 TA = 25°C kΩ 0.9 TA= 25°C 3 TA = 0°C to 70°C 4 TA = –40°C to 85°C Average offset voltage drift VCM = 0 V Noninverting input bias current VCM = 0 V 4 TA = 0°C to 70°C ±10 TA = –40°C to 85°C ±10 TA = 25°C Inverting input bias current Average bias current drift 6 VCM = 0 V VCM = 0 V VCM = 0 V μV/°C 4 TA= 25°C 15 TA = 0°C to 70°C 20 TA = –40°C to 85°C Average bias current drift μA 20 TA = 0°C to 70°C ±20 TA = –40°C to 85°C ±20 TA = 25°C 3.5 nA/°C TA= 25°C 15 TA = 0°C to 70°C 20 –40°C to 85°C 20 TA = 0°C to 70°C ±20 TA = –40°C to 85°C ±20 Submit Document Feedback mV μA nA/°C Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.5 Electrical Characteristics THS3091 (continued) VS = ±15 V, RF = 1.21 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TA = 25°C Input offset current Average offset current drift VCM = 0 V VCM = 0 V TYP MAX UNIT 1.7 TA= 25°C 10 TA = 0°C to 70°C 15 TA = –40°C to 85°C 15 TA = 0°C to 70°C ±20 TA = –40°C to 85°C ±20 μA nA/°C INPUT CHARACTERISTICS TA = 25°C TA= 25°C Common-mode input range ±13.6 ±13.3 TA = 0°C to 70°C ±13 TA = –40°C to 85°C ±13 TA = 25°C Common-mode rejection ratio VCM = ±10 V V 69 TA= 25°C 62 TA = 0°C to 70°C 59 TA = –40°C to 85°C 59 dB Noninverting input resistance TA = 25°C 1.3 MΩ Noninverting input capacitance TA = 25°C 0.1 pF Inverting input resistance TA = 25°C 30 Ω Inverting input capacitance TA = 25°C 1.4 pF OUTPUT CHARACTERISTICS TA = 25°C RL = 1 kΩ Output voltage swing ±13.2 TA = 25°C ±12.8 TA = 0°C to 70°C ±12.5 TA = –40°C to 85°C ±12.5 TA = 25°C RL = 100 Ω TA= 25°C ±12.1 TA = 0°C to 70°C ±11.8 TA = –40°C to 85°C ±11.8 TA= 25°C Output current (sourcing) RL = 40 Ω 280 TA = 25°C 225 TA = 0°C to 70°C 200 TA = –40°C to 85°C 200 TA = 25°C Output current (sinking) Output impedance RL = 40 Ω f = 1 MHz, Closed loop V ±12.5 mA 250 TA= 25°C 200 TA = 0°C to 70°C 175 TA = –40°C to 85°C 175 mA TA = 25°C 0.06 TA = 25°C ±15 Ω POWER SUPPLY Specified operating voltage TA= 25°C ±16 TA = 0°C to 70°C ±16 TA = –40°C to 85°C TA = 25°C Maximum quiescent current TA= 25°C V ±16 9.5 10.5 TA = 0°C to 70°C 11 TA = –40°C to 85°C 11 mA Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 7 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.5 Electrical Characteristics THS3091 (continued) VS = ±15 V, RF = 1.21 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TA = 25°C VS+ = 15.5 V to 14.5 V, VS– = 15 V 8 TA = –40°C to 85°C 8 VS+ = 15 V, VS– = –15.5 V to –14.5 V mA 75 TA= 25°C 70 TA = 0°C to 70°C 65 TA = –40°C to 85°C 65 TA = 25°C Power supply rejection (– PSRR) UNIT 8.5 TA = 0°C to 70°C TA = 25°C Power supply rejection (+PSRR) MAX 9.5 TA= 25°C Minimum quiescent current TYP dB 73 TA= 25°C 68 TA = 0°C to 70°C 65 TA = –40°C to 85°C 65 dB POWER-DOWN CHARACTERISTICS (THS3091 ONLY) TA = 25°C VS+ –4 TA = 25°C VS– Enable TA = 25°C PD ≥ REF +2 Disable TA = 25°C PD ≤ REF +.8 TA = 25°C 500 REF voltage range(1) Power-down voltage level(1) Power-down quiescent current PD = 0V 700 TA = 0°C to 70°C 800 11 TA= 25°C 15 TA = 0°C to 70°C 20 TA = –40°C to 85°C 20 TA = 25°C VPD = 3.3 V, REF = 0 V μA 11 TA= 25°C 15 TA = 0°C to 70°C 20 TA = –40°C to 85°C 20 Turnon time delay 90% of final value TA = 25°C 60 Turnoff time delay 10% of final value TA = 25°C 150 (1) μA 800 TA = 25°C VPD quiescent current V TA= 25°C TA = –40°C to 85°C VPD = 0 V, REF = 0 V, V μs For detailed information on the behavior of the power-down circuit, see the power-down functionality and power-down reference sections in the Application Information section of this data sheet. 7.6 Electrical Characteristics THS3095 VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE G = 1, RF = 1.78 kΩ, VO = 200 mVPP TA= 25°C 190 G = 2, RF = 1.15 kΩ, VO = 200 mVPP TA= 25°C 180 G = 5, RF = 1 kΩ, VO = 200 mVPP TA= 25°C 160 G = 10, RF = 866 Ω, VO = 200 mVPP TA= 25°C 150 0.1-dB Bandwidth flatness G = 2, RF = 1.15 kΩ, VO = 200 mVPP TA= 25°C 65 Large-signal bandwidth G = 2, RF = 1.15 kΩ , VO = 4 VPP TA= 25°C 160 G = 2, VO= 5-V step, RF = 1.21 kΩ TA= 25°C 1400 G = 5, VO= 5-V step, RF = 1 kΩ TA= 25°C 1900 G = 2, VO = 5-V step, RF = 1.21 kΩ TA= 25°C 5 Small-signal bandwidth, –3 dB Slew rate (25% to 75% level) Rise and fall time 8 Submit Document Feedback MHz V/μs ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.6 Electrical Characteristics THS3095 (continued) VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Settling time to 0.1% G = –2, VO = 2 VPP step TA= 25°C 35 Settling time to 0.01% G = –2, VO = 2 VPP step TA= 25°C 73 MAX UNIT ns HARMONIC DISTORTION 2nd Harmonic distortion 3rd Harmonic distortion G = 2, RF = 1.15 kΩ, VO = 2 VPP, f = 10 MHz RL = 100 Ω TA = 25°C 77 RL = 1 kΩ TA = 25°C 73 RL = 100 Ω TA = 25°C 70 RL = 1 kΩ TA = 25°C 68 dBc Input voltage noise f > 10 kHz TA = 25°C 2 nV / √ Hz Noninverting input current noise f > 10 kHz TA = 25°C 14 pA / √ Hz Inverting input current noise f > 10 kHz pA / √ Hz Differential gain Differential phase G = 2, RL = 150 Ω, RF = 1.15 kΩ TA = 25°C 17 NTSC TA = 25°C 0.027% PAL TA = 25°C 0.025% NTSC TA = 25°C 0.04° PAL TA = 25°C 0.05° DC PERFORMANCE TA = 25°C Transimpedance VO = ±2.5 V, Gain = 1 700 TA= 25°C 250 TA= 0°C to 70°C 200 TA= –40°C to 85°C 200 TA = 25°C Input offset voltage Average offset voltage drift VCM = 0 V VCM = 0 V Average bias current drift VCM = 0 V VCM = 0 V 2 TA= 0°C to 70°C 3 TA= –40°C to 85°C 3 TA= 0°C to 70°C ±10 TA= –40°C to 85°C ±10 Average bias current drift VCM = 0 V VCM = 0 V mV μV/°C 2 TA= 25°C 15 TA= 0°C to 70°C 20 TA= –40°C to 85°C 20 TA= 0°C to 70°C ±20 TA= –40°C to 85°C ±20 TA = 25°C Inverting input bias current 0.3 TA= 25°C TA = 25°C Noninverting input bias current kΩ μA nA/°C 5 TA= 25°C 15 TA= 0°C to 70°C 20 TA= –40°C to 85°C 20 TA= 0°C to 70°C ±20 TA= –40°C to 85°C ±20 μA nA/°C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 9 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.6 Electrical Characteristics THS3095 (continued) VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TA = 25°C Input offset current Average offset current drift VCM = 0 V VCM = 0 V TYP MAX UNIT 1 TA= 25°C 10 TA= 0°C to 70°C 15 TA= –40°C to 85°C 15 TA= 0°C to 70°C ±20 TA= –40°C to 85°C ±20 μA nA/°C INPUT CHARACTERISTICS TA = 25°C TA= 25°C Common-mode input range ±3.6 ±3.3 TA= 0°C to 70°C ±3 TA= –40°C to 85°C ±3 TA = 25°C Common-mode rejection ratio VCM = ±2.0 V, VO = 0 V V 66 TA= 25°C 60 TA= 0°C to 70°C 57 TA= –40°C to 85°C 57 dB Noninverting input resistance TA = 25°C 1.1 MΩ Noninverting input capacitance TA = 25°C 1.2 pF Inverting input resistance TA = 25°C 32 Ω Inverting input capacitance TA = 25°C 1.5 pF 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.6 Electrical Characteristics THS3095 (continued) VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT CHARACTERISTICS TA = 25°C RL = 1 kΩ Output voltage swing ±3.4 TA= 25°C ±3.1 TA= 0°C to 70°C ±2.8 TA= –40°C to 85°C ±2.8 TA = 25°C RL = 100 Ω TA= 25°C ±2.7 TA= 0°C to 70°C ±2.5 TA= –40°C to 85°C ±2.5 TA = 25°C Output current (sourcing) RL = 10 Ω 180 TA= 25°C 140 TA= 0°C to 70°C 120 TA= –40°C to 85°C 120 TA = 25°C Output current (sinking) Output impedance RL = 10 Ω f = 1 MHz, Closed loop V ±3.1 mA –160 TA= 25°C –140 TA= 0°C to 70°C –120 TA= –40°C to 85°C –120 TA = 25°C mA 0.09 Ω POWER SUPPLY TA = 25°C Specified operating voltage ±5 TA= 25°C ±4.5 TA= 0°C to 70°C ±4.5 TA= –40°C to 85°C ±4.5 TA = 25°C Maximum quiescent current 8.2 TA= 25°C 9 TA= 0°C to 70°C 9.5 TA= –40°C to 85°C 8.2 TA= 25°C 7 TA= 0°C to 70°C 6.5 TA = 25°C VS+ = 5.5 V to 4.5 V, VS– = 5 V 73 TA= 25°C 68 TA= 0°C to 70°C 63 TA= –40°C to 85°C 63 TA = 25°C Power supply rejection (–PSRR) mA 6.5 TA= –40°C to 85°C Power supply rejection (+PSRR) mA 9.5 TA = 25°C Minimum quiescent current V VS+ = 5 V, VS– = –4.5 V to –5.5 V dB 71 TA= 25°C 65 TA= 0°C to 70°C 60 TA= –40°C to 85°C 60 dB Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 11 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.6 Electrical Characteristics THS3095 (continued) VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-DOWN CHARACTERISTICS (THS3095 ONLY) REF voltage range(1) Power-down voltage level(1) Power-down quiescent current TA = 25°C VS+ –4 TA = 25°C VS– Enable TA = 25°C PD ≥ REF 2 Disable TA = 25°C PD ≤ REF 0.8 TA = 25°C 300 PD = 0V VPD quiescent current 500 TA= 0°C to 70°C 600 TA= –40°C to 85°C 600 15 TA= 0°C to 70°C 20 TA–40°C to 85°C 20 μA 11 TA= 25°C 15 TA= 0°C to 70°C 20 TA= –40°C to 85°C 20 Turnon time delay 90% of final value TA = 25°C 60 Turnoff time delay 10% of final value TA = 25°C 150 (1) μA 11 TA= 25°C TA = 25°C VPD = 3.3 V, REF = 0 V V TA= 25°C TA = 25°C VPD = 0 V, REF = 0 V, V μs For detailed information on the behavior of the power-down circuit, see the power-down functionality and power-down reference sections in the Application Information section of this data sheet. 7.7 Dissipation Ratings Table PACKAGE (1) (2) 12 θJC (°C/W) θJA POWER RATING (2) TJ = 125°C (°C/W)(1) TA = 25°C TA = 85°C D-8 38.3 97.5 1.02 W 410 mW DDA-8 9.2 45.8 2.18 W 873 mW This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.8 Typical Characteristics (±15 V) 24 22 9 RF = 750 Ω G = 10, RF = 866 Ω 20 18 7 Noninverting Gain − dB Noninverting Gain − dB 8 6 RRFF==1.21 1.21kkΩ Ω 5 4 RF = 1.5 kΩ 3 Gain = 2, RL =100 Ω, VO = 200 mVPP, VS = ±15 V 2 1 0 1M 10 M 100 M 1G 16 14 G = 5, RF = 1 kΩ 12 10 8 6 4 RL = 100 Ω, VO = 200 mVPP, VS = ±15 V G = 2, RF = 1.21 kΩ 2 0 −2 −4 G = 1, RF = 1.78 kΩ 10 M 1M f − Frequency − Hz 6.3 Gain = 2, RF = 1.21 kΩ, RL = 100 Ω, VO = 200 mVPP, VS = ±15 V G = −10, RF = 866 Ω 6.2 G = −5, RF = 909 Ω 12 10 8 6 4 2 0 −2 −4 RL = 100 Ω, VO = 200 mVPP, VS = ±15 V G = −2, RF = 1 kΩ 6.1 6 5.9 5.8 G = −1, RF = 1.05 kΩ 5.7 1M 10 M 100 M 1G 100 k f − Frequency − Hz Figure 7-3. Inverting Small-Signal Frequency Response 16 G = 5, RF = 1 kΩ 1G G = −5, RF = 909 Ω 14 14 12 12 Inverting Gain − dB Noninverting Gain − dB 1M 10 M 100 M f - Frequency - Hz Figure 7-4. 0.1-db Gain Flatness Frequency Response 16 10 8 G = 2, RF = 1.21 kΩ 6 10 8 G = −2, RF = 1 kΩ 6 4 2 4 2 1G Figure 7-2. Noninverting Small-Signal Frequency Response Noninverting Gain - dB Inverting Gain − dB Figure 7-1. Noninverting Small-Signal Frequency Response 24 22 20 18 16 14 100 M f − Frequency − Hz −2 −4 0 1M 10 M VO = 4 VPP, RL = 100 Ω, VS = ±15 V 0 VO = 4 VPP, RL = 100 Ω, VS = ±15 V 100 M 1G 1M 10 M 100 M 1G f − Frequency − Hz f − Frequency − Hz Figure 7-5. Noninverting Large-Signal Frequency Response Figure 7-6. Inverting Large-Signal Frequency Response Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 13 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.8 Typical Characteristics (±15 V) (continued) 16 R(ISO) = 30.9 Ω CL = 22 pF 10 8 R(ISO) = 22.1 Ω CL = 47 pF 6 4 R(ISO) = 15.8 Ω CL = 100 pF 2 0 Gain = 5, RL = 100 Ω, VS =±15 V 10 M 25 20 15 10 1G 10 100 CL − Capacitive Load − pF Figure 7-8. Recommended RISO vs Capacitive Load -40 VO = 2 VPP, RL = 100 Ω, VS = ±15 V 3rd Harmonic Distortion - dBc 2nd Harmonic Distortion − dBc 30 0 100 M f − Frequency − Hz −40 −50 35 5 Figure 7-7. Capacitive Load Frequency Response −45 Gain = 5, RL = 100 Ω, VS = ±15 V 40 Recommended R −Ω ISO Signal Gain − dB 12 −2 45 R(ISO) = 38.3 Ω CL = 10 pF 14 −55 −60 G = 1, RF = 1.78 kΩ −65 −70 −75 G = 2, RF = 1.21 kΩ −80 VO = 2 VPP, RL = 100 Ω, VS = ±15 V -50 -60 G = 1, RF = 1.78 kΩ -70 -80 G = 2, RF = 1.21 kΩ -90 −85 -100 −90 100 k 1M 10 M 100 M 100 k f − Frequency − Hz 100 M Figure 7-10. 3rd Harmonic Distortion vs Frequency −40 −40 VO = 2 VPP, RL = 1 kΩ, VS = ±15 V −60 −70 VO = 2 VPP, RL = 1 kΩ, VS = ±15 V −45 3rd Harmonic Distortion − dBc 2nd Harmonic Distortion − dBc 10 M f - Frequency - Hz Figure 7-9. 2nd Harmonic Distortion vs Frequency −50 1M G = 1, RF = 1.78 kΩ −80 G = 2, RF = 1.21 kΩ −90 −50 −55 −60 G = 1, RF = 1.78 kΩ −65 −70 −75 G = 2, RF = 1.21 kΩ −80 −85 −100 100 k −90 1M 10 M 100 M 100 k Figure 7-11. 2nd Harmonic Distortion vs Frequency 14 1M 10 M 100 M f − Frequency − Hz f − Frequency − Hz Figure 7-12. 3rd Harmonic Distortion vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.8 Typical Characteristics (±15 V) (continued) −30 G = 5, RF = 1 kΩ, RL = 100 Ω, VS = ±15 V −40 −50 −60 VO = 10 VPP −70 −80 G = 5, RF = 1 kΩ, RL = 100 Ω, VS = ±15 V VO = 20 VPP 3rd Harmonic Distortion − dBc 2nd Harmonic Distortion − dBc −30 VO = 2 VPP −40 −50 VO = 20 VPP −60 −70 VO = 10 VPP −80 VO = 2 VPP −90 −90 1M 10 M 100 M 1M 10 M f − Frequency − Hz Figure 7-13. 2nd Harmonic Distortion vs Frequency Figure 7-14. 3rd Harmonic Distortion vs Frequency -40 -60 Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 8 MHz VS = ±15 V -65 -70 Harmonic Distortion - dBc Harmonic Distortion - dBc -50 HD2 -75 -80 HD3 -85 Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 1 MHz VS = ±15 V -90 -95 HD2 -60 -70 -80 HD3 -90 -100 -100 0 2 4 6 8 10 12 14 16 0 18 20 2 4 6 8 10 12 14 16 18 20 VO - Output Voltage Swing - VPP VO - Output Voltage Swing - VPP Figure 7-15. Harmonic Distortion vs Output Voltage Swing Figure 7-16. Harmonic Distortion vs Output Voltage Swing 2000 6000 1600 Gain = 2 RL = 100 Ω RF = 1.21 kΩ VS = ±15 V 5000 Rise SR - Slew Rate - V/ µ s Gain = 1 RL = 100 Ω RF = 1.78 kΩ VS = ±15 V 1800 SR − Slew Rate − V/ µ s 100 M f − Frequency − Hz 1400 1200 Fall 1000 800 600 4000 3000 2000 Rise 400 Fall 1000 200 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VO − Output Voltage − VPP 4.5 5 0 0 1 2 3 4 5 6 7 8 9 10 VO - Output Voltage - VPP Figure 7-17. Slew Rate vs Output Voltage Step Figure 7-18. Slew Rate vs Output Voltage Step Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 15 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.8 Typical Characteristics (±15 V) (continued) 8000 Hz Vn − Voltage Noise − nV/ SR - Slew Rate - V/ µ s 6000 5000 Rise 4000 Fall 3000 2000 I n − Current Noise − pA/ Hz 1000 Gain = 5 RL = 100 Ω RF = 1 kΩ VS = ±15 V 7000 100 In− In+ 10 Vn 1000 1 0 0 2 4 6 8 10 12 14 16 18 20 VO - Output Voltage - VPP 10 1 VO - Output Voltage - V VO - Output Voltage - V Rising Edge 0.5 Gain = -2 RL = 100 Ω RF =1 kΩ VS = ±15 V 0 -0.25 -0.5 -0.75 Falling Edge -1 -1.25 0 1 2 3 4 5 6 7 8 9 10 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 Gain = -2 RL = 100 Ω RF = 1 kΩ VS = ±15 V Falling Edge 0 2 4 6 8 10 12 100 M 10 M 1M f − Frequency − Hz 1G t - Time - ns Figure 7-21. Settling Time Figure 7-22. Settling Time 10 22 TA = 85 °C 9.5 20 TA = 25 °C 9 8.5 TA = −40 °C 8 7.5 7 6.5 I Q − Quiescent Current − mA I Q− Quiescent Current − mA 100 k Rising Edge t - Time - ns 18 16 VO = 4VPP 14 12 10 VO = 2VPP 8 6 Gain = 5 RF = 1 kΩ, RL = 100 Ω, VS = ±15 V 4 2 6 3 4 5 6 7 8 9 10 11 12 13 14 15 0 100 k VS − Supply Voltage − ±V Figure 7-23. Quiescent Current vs Supply Voltage 16 10 k Figure 7-20. Noise vs Frequency 1.25 0.25 1k f − Frequency − Hz Figure 7-19. Slew Rate vs Output Voltage Step 0.75 100 Figure 7-24. Quiescent Current vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 16 7 12 6.5 6 I IB - Input Bias Currents - µ A I OS - Input Offset Currents - µ A VO - Output Voltage - V 7.8 Typical Characteristics (±15 V) (continued) 8 4 VS = ±15 V TA = -40 to 85°C 0 -4 -8 -12 -16 10 100 1000 5.5 5 4.5 4 IIB+ 3.5 3 2.5 2 1.5 1 IOS 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 RL - Load Resistance - Ω Figure 7-25. Output Voltage vs Load Resistance TC - Case Temperature - °C Figure 7-26. Input Bias and Offset Current vs Case Temperature 3 Transimpedance Gain − dB Ohms 100 VOS - Input Offset Voltage - mV 2.5 2 VS = ±15 V 1.5 1 VS = ±5 V 0.5 90 VS = ±15 V and ±5 V 80 70 60 50 40 30 20 10 0 100 k 0 -40 -30 -20-10 0 10 20 30 40 50 60 70 80 90 1M 10 M 100 M 1G f − Frequency − Hz TC - Case Temperature - °C Figure 7-27. Input Offset Voltage vs Case Temperature Figure 7-28. Transimpedance vs Frequency 70 0.3 VS = ±15 V 60 0.25 50 CMRR 40 30 PSRR+ 20 Output 0.2 PSRR− VO - Output Voltage - V Rejection Ratio − dB VS = ±15 V IIB- 0.15 Input 0.1 0.05 0 -0.05 Gain = 2 RL = 100 Ω RF = 1 kΩ VS = ±15 V -0.1 -0.15 -0.2 10 -0.25 0 100 k 1M 10 M 100 M 1G -0.3 0 10 20 30 40 50 60 70 t - Time - ns f − Frequency − Hz Figure 7-29. Rejection Ratio vs Frequency Figure 7-30. Noninverting Small-Signal Transient Response Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 17 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.8 Typical Characteristics (±15 V) (continued) 12 6 10 5 Output 3 2 1 0 Input −1 −2 Gain = −5 RL = 100 Ω RF = 909 Ω VS = ±15 V −3 −4 −5 Gain = -5 RL = 100 Ω RF =909 Ω VS = ±15 V 8 VO - Output Voltage - V VO − Output Voltage − V 4 6 4 2 Input 0 -2 -4 -6 -8 Output -10 -12 −6 0 5 10 15 20 25 30 35 0 40 10 Figure 7-31. Inverting Large-Signal Transient Response 20 Differential Gain - % 0.08 2 0.07 1 0 0 −5 −1 −10 −2 −15 −3 0.01 −4 0 −20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 70 PAL 0.05 0.04 0.03 0.02 NTSC 0 1 1 2 3 4 5 6 7 8 Number of Loads - 150 Ω Figure 7-34. Differential Gain vs Number of Loads Figure 7-33. Overdrive Recovery Time 0.05 100 0.04 Closed-Loop Output Impedance − Ω Gain = 2 RF = 1.21 kΩ VS = ±15 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp ° Differential Phase − 60 0.06 t − Time − µs 0.03 PAL 0.02 NTSC 0.01 Gain = 2, RISO = 5.11 Ω, RF = 1.21 KΩ, VS = ±15 V 10 1 1.21 kΩ 1.21 kΩ 0.1 5.11 Ω VO − + 0.01 0 1 2 3 4 5 6 7 8 1M Number of Loads − 150 Ω 10 M 100 M 1G f − Frequency − Hz Figure 7-35. Differential Phase vs Number of Loads 18 50 Gain = 2 RF = 1.21 kΩ VS = ±15 V 40 IRE - NTSC and Pal Worst Case ±100 IRE Ramp 0.09 3 5 0 40 0.10 VI − Input Voltage − V VO − Output Voltage − V 10 30 Figure 7-32. Inverting Large-Signal Transient Response 4 Gain = 5, RL = 100 Ω, RF = 1 kΩ, VS = ±15 V 15 20 t - Time - ns t − Time − ns Figure 7-36. Closed-Loop Output Impedance vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.8 Typical Characteristics (±15 V) (continued) 600 6 TA = 85°C 400 TA = -40°C 300 TA = 25°C 200 100 5 4 Gain = 2, VI = 0.1 Vdc RL = 100 Ω VS = ±15 V and ±5 V 3 2 1 0 0.3 0.2 0.1 Power-on Pulse − V 500 VO − Output Voltage Level − V Powerdown Quiescent Current - µ A Power-on Pulse Output Voltage 0 −0.1 0 3 4 5 6 7 8 9 0 10 11 12 13 14 15 1 2 3 4 5 6 7 t − Time − ms VS - Supply Voltage - ±V Figure 7-37. Power-Down Quiescent Current vs Supply Voltage Figure 7-38. Turnon and Turnoff Time Delay Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 19 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 24 22 20 18 16 14 12 10 8 6 4 2 0 -2 -4 24 22 20 18 16 14 12 10 G = 10, RF = 909 Ω G = 5, RF = 1 kΩ Inverting Gain − dB Noninverting Gain - dB 7.9 Typical Characteristics (±5 V) RL = 100 Ω, VO = 200 mVPP. VS = ±5 V G = 2, RF = 1.15 kΩ 10 M 100 M G = −5, RF = 909 Ω RL = 100 Ω, VO = 200 mVPP. VS = ±5 V 8 6 4 2 0 −2 −4 G =1, RF = 1.5 kΩ 1M G = −10, RF = 866 Ω 1G G = −2, RF = 1 kΩ G = −1, RF = 1.05 Ω 1M 10 M 100 M f − Frequency − Hz f - Frequency - Hz Figure 7-39. Noninverting Small-Signal Frequency Response Figure 7-40. Inverting Small-Signal Frequency Response 16 6.3 6.1 Gain = 2, RF = 1.21 kΩ, RL = 100 Ω, VO = 200 mVPP, VS = ±5 V G = 5, RF = 1 kΩ 14 12 Noninverting Gain − dB Noninverting Gain - dB 6.2 6 5.9 10 8 G = 2, RF = 1.15 kΩ 6 4 5.8 RL = 100 Ω, VO = 4 VPP, VS = ±5 V 2 0 5.7 1M 10 M 1M 100 M 10 M Figure 7-41. 0.1-db Gain Flatness Frequency Response 1G Figure 7-42. Noninverting Large-Signal Frequency Response 16 1.25 G = −5, RF = 909 Ω 14 1 12 0.75 VO - Output Voltage - V Inverting Gain − dB 100 M f − Frequency − Hz f - Frequency - Hz 10 8 6 G = −2, RF = 1 kΩ 4 0.5 0.25 Gain = -2 RL = 100 Ω RF = 1 kΩ VS = ±5 V 0 -0.5 -0.75 RL = 100 Ω, VO = 4 VPP, VS = ±5 V −2 Rising Edge -0.25 2 0 Falling Edge -1 −4 -1.25 1M 10 M 100 M f − Frequency − Hz 1G 0 1 2 3 4 5 6 7 8 9 10 t - Time - ns Figure 7-43. Inverting Large-Signal Frequency Response 20 1G Submit Document Feedback Figure 7-44. Settling Time Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.9 Typical Characteristics (±5 V) (continued) -40 VO = 2 VPP, RL = 100 Ω, VS = ±5 V −50 3rd Harmonic Distortion - dBc 2nd Harmonic Distortion − dBc −40 −60 G = 1, RF = 1.78 kΩ −70 −80 G = 2, RF = 1.15 kΩ −90 −100 100 k VO = 2 VPP, RL = 100 Ω, VS = ±5 V -50 -60 -70 G = 1, RF = 1.78 kΩ -80 G = 2, RF = 1.15 kΩ -90 -100 1M 10 M 100 k 100 M 1M f − Frequency − Hz Figure 7-45. 2nd Harmonic Distortion vs Frequency −40 VO = 2 VPP, RL = 1 kΩ, VS = ±5 V −50 3rd Harmonic Distortion − dBc 2nd Harmonic Distortion − dBc 100 M Figure 7-46. 3rd Harmonic Distortion vs Frequency −40 −60 G = 1, RF = 1.78 kΩ −70 −80 G = 2, RF = 1.15 kΩ −90 −100 100 k 1M 10 M VO = 2 VPP, RL = 1 kΩ, VS = ±5 V −50 −60 G = 1, RF = 1.78 kΩ −70 −80 G = 2, RF = 1.15 kΩ −90 −100 100 k 100 M 1M f − Frequency − Hz 10 M 100 M f − Frequency − Hz Figure 7-47. 2nd Harmonic Distortion vs Frequency Figure 7-48. 3rd Harmonic Distortion vs Frequency -20 −20 Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 1 MHz VS = ±5 V -40 -50 -60 Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 8 MHz VS = ±5 V −30 Harmonic Distortion − dBc -30 Harmonic Distortion - dBc 10 M f - Frequency - Hz HD3 -70 -80 HD2 -90 −40 −50 HD3 −60 HD2 −70 −80 −90 -100 −100 0 1 2 3 4 5 6 0 VO - Output Voltage Swing - VPP Figure 7-49. Harmonic Distortion vs Output Voltage Swing 1 2 3 4 5 6 VO − Output Voltage Swing − VPP Figure 7-50. Harmonic Distortion vs Output Voltage Swing Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 21 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.9 Typical Characteristics (±5 V) (continued) 1600 1600 Gain = 1 RL = 100 Ω RF = 1.78 kΩ VS = ±5 V 1200 Gain = 1 RL = 100 Ω RF = 1.21 kΩ VS = ±5 V 1400 SR − Slew Rate − V/µ s SR − Slew Rate − V/ µs 1400 1000 Fall 800 600 1200 1000 Rise 800 600 Rise 400 400 200 200 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 VO − Output Voltage −VPP Figure 7-51. Slew Rate vs Output Voltage Step 1600 1400 20 Fall I Q− Quiescent Current − mA SR - Slew Rate - V/ µ s 5 22 Gain = 5 RL = 100 Ω RF = 1 kΩ VS = ±5 V 1800 Rise 1200 1000 800 600 400 18 16 14 Gain = 5 RF = 1 kΩ, RL = 100 Ω, VS = ±5 V VO = 4 VPP 12 10 8 VO = 2 VPP 6 4 200 2 0 100 k 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VO - Output Voltage -VPP 4.5 5 1M 10 M 100 M 1G f − Frequency − Hz Figure 7-53. Slew Rate vs Output Voltage Step Figure 7-54. Quiescent Current vs Frequency 3.5 8 3 2.5 7 VS = ±5 V 2 1.5 1 0.5 I IB - Input Bias Current - µ A I OS - Input Offset Current - µ A VO - Output Voltage - V 1 2 3 4 VO − Output Voltage −VPP Figure 7-52. Slew Rate vs Output Voltage Step 2000 VS = ±5 V TA = -40 to 85°C 0 -0.5 -1 -1.5 -2 -2.5 -3 IIB- 6 5 IOS 4 3 2 IIB+ 1 -3.5 10 100 1000 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - °C RL - Load Resistance - Ω Figure 7-55. Output Voltage vs Load Resistance 22 Fall Figure 7-56. Input Bias and Offset Current vs Case Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 7.9 Typical Characteristics (±5 V) (continued) 5 2 60 0.6 0.4 1 0.2 0 0 -1 -0.2 -2 -0.4 -3 -0.6 -4 -0.8 PSRRRejection Ratio - dB 3 VS = ±5 V 0.8 VI - Input Voltage - V 4 VO - Output Voltage - A 70 1 Gain = 5, RL = 100 Ω, RF = 1 kΩ, VS = ±5 V 50 40 CMRR 30 20 PSRR+ 10 -1 -5 0 0.2 0.4 0.6 0.8 1 0 100 k t - Time - µs Figure 7-57. Overdrive Recovery Time 1M 10 M f - Frequency - Hz 100 M Figure 7-58. Rejection Ratio vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 23 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview The THS3091 and THS3095 are high-voltage, low-distortion, high-speed, current feedback amplifiers designed to operate over a wide supply range of ±5 V to ±16 V for applications requiring large, linear output swings such as Arbitrary Waveform Generators. The THS3095 features a power-down pin that puts the amplifier in low power standby mode, and lowers the quiescent current from 9.5 mA to 500 µA. 8.2 Feature Description 8.2.1 Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin The THS3095 features a power-down pin (PD) which lowers the quiescent current from 9.5 mA down to 500 μA, ideal for reducing system power. The power-down pin of the amplifier defaults to the positive supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the negative rail. For information about the threshold voltages for power on and power down are relative to the supply rails, see Section 7.8 and Section 7.9. Above the enable threshold voltage, the device is on. Below the disable threshold voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in Power-Down mode. The Power-Down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in Power-Down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. Figure 8-1 shows the total system output impedance which includes the amplifier output impedance in parallel with the feedback plus gain resistors, which cumulates to 2380 Ω. Figure 8-2 shows this circuit configuration for reference. ZOPD − Powerdown Output Impedance − Ω 2500 VS = ±15 V and ±5 V 2000 1500 1000 1.21 kΩ 500 1.21 kΩ − + 50 Ω VO 1M 10 M 0 100 k 100 M 1G f − Frequency − Hz Figure 8-1. Power-Down Output Impedance vs Frequency As with most current feedback amplifiers, the internal architecture places some limitations on the system when in Power-Down mode. Most notably is the fact that the amplifier actually turns ON if there is a ±0.7 V or greater difference between the two input nodes (V+ and V–) of the amplifier. If this difference exceeds ±0.7 V, then the output of the amplifier creates an output voltage equal to approximately [(V+ – V–) –0.7 V] × Gain. This also implies that if a voltage is applied to the output while in Power-Down mode, the V– node voltage is equal to VO(applied) × RG/(RF + RG). For low gain configurations and a large applied voltage at the output, the amplifier may actually turn ON due to the aforementioned behavior. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 8.2.2 Power-Down Reference Pin Operation In addition to the power-down pin, the THS3095 features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. In most split-supply applications, the reference pin is connected to ground. In either case, the user needs to be aware of voltage-level thresholds that apply to the power-down pin. The following tables provide examples and illustrate the relationship between the reference voltage and the power-down thresholds. In the table, the threshold levels are derived by the following equations: PD ≤ REF + 0.8 V for disable (1) PD ≥ REF + 2.0 V for enable (2) where the usable range at the REF pin is: VS– ≤  VREF ≤ (VS+  – 4 V) (3) The recommended mode of operation is to tie the REF pin to midrail, thus setting the enable or disable thresholds to Vmidrail + 2 V and Vmidrail + 0.8 V respectively. Table 8-1. Power-Down Threshold Voltage Levels SUPPLY VOLTAGE (V) REFERENCE PIN VOLTAGE (V) ENABLE LEVEL (V) DISABLE LEVEL (V) ±15, ±5 0 2 0.8 ±15 2 4 2.8 ±15 –2 0 –1.2 ±5 1 3 1.8 ±5 –1 1 –0.2 30 15 17 15.8 10 5 7 5.8 Note that if the REF pin is left unterminated, it will float to the positive rail and will fall outside recommended operating range shown in Equation 3 (VS– ≤  VREF ≤  VS+ – 4 V). As a result, it will no serve as a reliable reference for the PD pin and the enable or disable thresholds provided in Table 8-1 longer apply. If the PD pin is also left unterminated, it will also float to the positive rail and the device enabled. If balanced, split supplies are used (±Vs) and the REF and PD pins are grounded, the device disabled. of the longer will no will be will be 8.3 Device Functional Modes 8.3.1 Wideband, Noninverting Operation The THS309x are unity gain stable 235-MHz current-feedback operational amplifiers, designed to operate from a ±5-V to ±15-V power supply. Figure 8-2 shows the THS3091 in a noninverting gain of 2-V/V configuration typically used to generate the performance curves. Most of the curves were characterized using signal sources with 50-Ω source impedance, and with measurement equipment presenting a 50-Ω load impedance. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 25 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 15 V +VS + 0.1 µF 50-Ω Source + VI 6.8 µF 49.9 Ω THS3091 49.9 Ω _ 50-Ω LOAD RF 1.21 kΩ RG 1.21 kΩ 0.1 µF 6.8 µF + −VS −15 V Figure 8-2. Wideband, Noninverting Gain Configuration Current-feedback amplifiers are highly dependent on the feedback resistor RF for maximum performance and stability. Table 8-2 shows the optimal gain-setting resistors RF and RG at different gains to give maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for RF. Conversely, increasing RF decreases the bandwidth, but stability is improved. Table 8-2. Recommended Resistor Values for Optimum Frequency Response THS3091 and THS3095 RF and RG values for minimal peaking with RL = 100 Ω GAIN (V/V) SUPPLY VOLTAGE (V) RG (Ω) RF (Ω) ±15 — 1.78 k ±5 — 1.78 k ±15 1.21 k 1.21 k ±5 1.15 k 1.15 k ±15 249 1k ±5 249 1k ±15 95.3 866 ±5 95.3 866 –1 ±15 and ±5 1.05 k 1.05 k –2 ±15 and ±5 499 1k –5 ±15 and ±5 182 909 –10 ±15 and ±5 86.6 866 1 2 5 10 8.3.2 Wideband, Inverting Operation Figure 8-3 shows the THS3091 in a typical inverting gain configuration where the input and output impedances and signal gain from Figure 8-2 are retained in an inverting circuit configuration. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 15 V +VS + 0.1 µF + 6.8 µF 49.9 Ω THS3091 _ 50-Ω LOAD 50-Ω Source VI RG RF 499 Ω RM 56.2 Ω 1 kΩ 0.1 µF 6.8 µF + −15 V −VS Figure 8-3. Wideband, Inverting Gain Configuration 8.3.3 Single-Supply Operation The THS309x have the capability to operate from a single-supply voltage ranging from 10 V to 30 V. When operating from a single power supply, biasing the input and output at mid-supply allows for the maximum output voltage swing. The circuits shown in Figure 8-4 show inverting and noninverting amplifiers configured for single-supply operations. +VS 50-Ω Source + VI 49.9 Ω RT 49.9 Ω THS3091 _ 50-Ω LOAD +VS 2 RF 1.21 kΩ RG 1.21 kΩ +VS 2 RF 1 kΩ 50-Ω Source VI 56.2 Ω +VS 2 VS RG 499 Ω RT _ 49.9 Ω THS3091 + 50-Ω LOAD +VS 2 Figure 8-4. DC-Coupled, Single-Supply Operation Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 27 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Video Distribution The wide bandwidth, high slew rate, and high output drive current of the THS309x matches the demands for video distribution for delivering video signals down multiple cables. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes distortion of the video signal, and supports component video and RGB video signals that require fast transition times and fast settling times for high signal quality. 1.21 kΩ 1.21 kΩ 15 V VI 75-Ω Transmission Line 75 Ω − + −15 V 75 Ω n Lines 75 Ω VO(1) VO(n) 75 Ω 75 Ω Figure 9-1. Video Distribution Amplifier Application 9.1.2 Driving Capacitive Loads Applications such as FET line drivers can be highly capacitive and cause stability problems for high-speed amplifiers. Figure 9-2 through Figure 9-7 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier’s feedback path. For recommended resistor values versus capacitive load, see Effect of Parasitic Capacitance in Op Amp Circuits application note. 45 Gain = 5, RL = 100 Ω, VS = ±15 V Recommended R −Ω ISO 40 35 30 25 20 15 10 5 0 10 100 CL − Capacitive Load − pF Figure 9-2. Recommended RISO vs Capacitive Load 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 1 kΩ VS 249 Ω _ 5.11 Ω + RISO 100-Ω LOAD 1 µF −VS 49.9 Ω VS Figure 9-3. Driving a Large Capacitive Load Using an Output Series Isolation Resistor 1 kΩ VS 249 Ω Ferrite Bead _ + 1 µF −VS 100-Ω LOAD 49.9 Ω VS Figure 9-4. Driving a Large Capacitive Load Using an Output Series Ferrite Bead As shown in Figure 9-3, placing a small series resistor, RISO, between the amplifier’s output and the capacitive load is an easy way of isolating the load capacitance. As shown in Figure 9-4 using a ferrite chip in place of RISO is another approach of isolating the output of the amplifier. The ferrite's impedance characteristic versus frequency is useful to maintain the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. Use a ferrite with similar impedance to RISO, 20 Ω to 50 Ω, at 100 MHz and low-impedance at DC. Figure 9-5 shows another method used to maintain the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from the load side of RISO. At high frequency, the feedback is mainly via the 27-pF capacitor. The resistor RIN in series with the negative input is used to stabilize the amplifier and should be equal to the recommended value of RF at unity gain. As shown in Figure 9-6, replacing RIN with a ferrite of similar impedance at about 100 MHz gives similar results with reduced DC offset and low-frequency noise (for more information, see Expanding the Usability of Current-Feedback Amplifiers analog journal). RF 1 kΩ 27 pF RIN RG 249 Ω 1 kΩ VS _ + −VS VS 100-Ω LOAD 5.11 Ω 1 µF 49.9 Ω Figure 9-5. Driving a Large Capacitive Load Using a Multiple Feedback Loop With Stabilizing Input Resistor (RIN) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 29 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 RF 1 kΩ 27 pF FIN RG FB 249 Ω VS _ 100-Ω LOAD 5.11 Ω + 1 µF −VS 49.9 Ω VS Figure 9-6. Driving a Large Capacitive Load Using a Multiple Feedback Loop With Stabilizing Input Ferrite Bead (FIN) Figure 9-7 is shown using two amplifiers in parallel to double the output drive current to larger capacitive loads. This technique is used when more output current is needed to charge and discharge the load faster like when driving large FET transistors. 1 kΩ VS 249 Ω _ 5.11 Ω + 24.9 Ω −VS 1 kΩ VS VS 249 Ω 1 nF _ 5.11 Ω + 24.9 Ω −VS Figure 9-7. Driving a Large Capacitive Load Using 2 Parallel Amplifier Channels Figure 9-8 shows a push-pull FET driver circuit typical of ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier. VS VS 5.11 Ω + _ −VS 866 Ω 191 Ω 866 Ω VS _ 5.11 Ω + −VS −VS Figure 9-8. PowerFET Drive Circuit 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 9.2 Typical Application The fundamental concept of load sharing is to drive a load using two or more of the same operational amplifiers. Each amplifier is driven by the same source. Figure 9-9 shows two THS3091 amplifiers sharing the same load. This concept effectively reduces the curernt load of each amplifier by 1/N, where N is the number of amplifiers. RG 250 W RF 1 kW V- RS 50 W RSOURCE 50 W VIN VOUT THS3091 U3 RT 50 W RF1 1 kW V+ V1 15 V V- VIN RLOAD 50 W V+ RG1 250 W RSOURCE 50 W TL2 Characteristic Impedance 50 W V+ RG2 250 W RF2 1 kW V2 -15 V TL1 Characteristic Impedance 50 W VOUT RLOAD 50 W V- RT2 100 W + RS1 100 W THS3091 U1 RT1 100 W V- + RS2 100 W THS3091 U2 V+ Figure 9-9. Reference THS3091 and THS3091 Load Sharing Test Configurations 9.2.1 Design Requirements Use two THS3091 amplifiers in a parallel load-sharing circuit to improve distortion performance. Table 9-1. Design Parameters DESIGN PARAMETER VALUE VOPP 20 V RLOAD 100 Ω 9.2.2 Detailed Design Procedure In addition to providing higher output current drive to the load, the load sharing configuration can also provide improved distortion performance. In many cases, an operational amplifier shows better distortion performance as the load current decreases (that is, for higher resistive loads) until the feedback resistor starts to dominate the current load. In a load sharing configuration of N amplifiers in parallel, the equivalent current load that each amplifier drives is 1/N times the total load current. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 31 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 As shown in Figure 9-9 for example, in a two-amplifier load sharing configuration with matching resistance driving a resistive load (RL), each series resistance is 2*RL and each amplifier drives 2*RL. A convenient indicator of whether an op amp will function well in a load sharing configuration is the characteristic performance graph of harmonic distortion versus load resistance. Such graphs can be found in most of TI’s high-speed amplifier data sheets. These graphs can be used to obtain a general sense of whether or not an amplifier will show improved distortion performance in load sharing configurations. Figure 9-9 shows two test circuits: one for a single THS3091 amplifier driving a double-terminated (50-Ω cable), and one with two THS3091 amplifiers in a load sharing configuration. In the load sharing configuration, the two 100-Ω series output resistors act in parallel to provide 50-Ω back-matching to the 50-Ω cable. Figure 9-10 and Figure 9-11 show the 32-MHz, 18-VPP sine wave output amplitudes for the single THS3091 configuration and the load sharing configuration, respectively, measured using an oscilloscope. An ideal sine wave is also included as a visual reference (the dashed red line). Figure 72 shows visible distortion in the single THS3091 output. In the load sharing configuration of Figure 73, however, no obvious degradation is visible. Figure 9-12 and Figure 9-13 show the 64-MHz sine wave outputs of the two configurations from Figure 8. While the single THS3091 output is clearly distorted in Figure 74, the output of the load sharing configuration in Figure 75 shows only minor deviations from the ideal sine wave. The improved output waveform as a result of load sharing is quantified in the harmonic distortion versus frequency graphs shown in Figure 9-14 and Figure 9-15 for the single amplifier and load sharing configurations, respectively. While second-harmonic distortion remains largely the same between the single and load sharing cases, third-harmonic distortion is improved by approximately 8 dB in the frequency range between 20 MHz to 64 MHz. Table 9-2. Bill of Materials THS3091DDA and THS3095DDA EVM(1) ITEM SMD SIZE 1206 REFERENCE DESIGNATOR PCB QTY MANUFACTURER'S PART NUMBER DISTRIBUTOR'S PART NUMBER 1 Bead, Ferrite, 3 A, 80 Ω FB1, FB2 2 (Steward) HI1206N800R-00 (Digi-Key) 240-1010-1-ND 2 Cap, 6.8 μF, Tantalum, 50 V, 10% D C3, C6 2 (AVX) TAJD685K050R (Garrett) TAJD685K050R 3 Cap, 0.1 μF, ceramic, X7R, 50 V 0805 C9, C10 2(2) (AVX) 08055C104KAT2A (Garrett) 08055C104KAT2A 4 Cap, 0.1 μF, ceramic, X7R, 50 V 0805 C4, C7 2 (AVX) 08055C104KAT2A (Garrett) 08055C104KAT2A 5 Resistor, 0 Ω, 1/8 W, 1% 0805 R9 1(2) (KOA) RK73Z2ALTD (Garrett) RK73Z2ALTD 6 Resistor, 249 Ω, 1/8 W, 1% 0805 R3 1 (KOA) RK73H2ALTD2490F (Garrett) RK73H2ALTD2490F 7 Resistor, 1 kΩ, 1/8 W, 1% 0805 R4 1 (KOA) RK73H2ALTD1001F (Garrett) RK73H2ALTD1001F 8 Open 1206 R8 1 9 Resistor, 0 Ω, 1/4 W, 1% 1206 R1 1 (KOA) RK73Z2BLTD (Garrett) RK73Z2BLTD 10 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R2, R7 2 (KOA) RK73Z2BLTD49R9F (Garrett) RK73Z2BLTD49R9F 11 Open 2512 R5, R6 2 12 Header, 0.1-inch (2,54 mm) centers, 0.025-inch (6,35 mm) square pins JP1, JP2 2 (2) (Sullins) PZC36SAAN (Digi-Key) S1011-36-ND 13 Connector, SMA PCB Jack J1, J2, J3 3 (Amphenol) 901-144-8RFX (Newark) 01F2208 14 Jack, banana receptacle, 0.25-inch (6,35 mm) dia. hole J4, J5, J6 3 (SPC) 813 (Newark) 39N867 15 Test point, black TP1, TP2 2 (Keystone) 5001 (Digi-Key) 5001K-ND 16 Standoff, 4-40 hex, 0.625-inch (15,9 mm) length 4 (Keystone) 1808 (Newark) 89F1934 17 Screw, Phillips, 4-40, 0.25-inch (6,35 mm) 4 SHR-0440-016-SN 18 IC, THS3091(3) IC, THS3095(2) 1 (TI) THS3091DDA(3) (TI) THS3095DDA(2) 19 Board, printed-circuit 1 (TI) EDGE # 6446289 Rev. A(3) (TI) EDGE # 6446290 Rev. A(2) (1) (2) (3) 32 DESCRIPTION U1 All items are designated for both the THS3091DDA and THS3095 EVMs unless otherwise noted. THS3095 EVM only. THS3091 EVM only. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 15 15 10 10 Output Voltage (V) Output Voltage (V) 9.2.3 Application Curves 5 0 –5 –10 5 0 –5 –10 –15 –15 0 10 20 30 40 0 50 10 20 Time (ns) 40 50 Figure 9-11. 32-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Two THS3091 Amplifiers in Load Sharing Configuration 15 15 10 10 Output Voltage (V) Output Voltage (V) Figure 9-10. 32-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Single THS3091 Circuit Configuration 5 0 –5 –10 5 0 –5 –10 –15 –15 0 5 10 15 20 25 0 5 10 Time (ns) 15 20 25 Time (ns) Figure 9-12. 64-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Single THS3091 Circuit Configuration Figure 9-13. 64-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Two THS3091 Amplifiers in Load Sharing Configuration –10 –10 VO = 20 VPP (at amplifier output) –20 RS = 50 Ω –30 RL = 50 Ω –40 –50 –60 –70 –80 1 10 VO = 10 VPP (at load) RS (Each Amplifier) = 100 Ω –30 RL (Shared) = 50 Ω –40 –50 –60 –70 –80 Second Harmonic Third Harmonic –90 VO = 20 VPP (at amplifier output) –20 VO = 10 VPP (at load) Harmonic Distortion (dBc) Harmonic Distortion (dBc) 30 Time (ns) Second Harmonic Third Harmonic –90 100 1 10 100 Frequency (MHz) Frequency (MHz) Figure 9-14. Harmonic Distortion vs Frequency, Single THS3091 Circuit Configuration Figure 9-15. Harmonic Distortion vs Frequency, Two THS3091 Amplifiers in Load Sharing Configuration Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 33 THS3091, THS3095 SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 www.ti.com 10 Power Supply Recommendations The THS3091 can operate off a single supply or with dual supplies as long as the input CM voltage range (CMIR) has the required headroom to either supply rail. Operating from a single supply can have numerous advantages. With the negative supply at ground, the DC errors due to the –PSRR term can be minimized. Supplies should be decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to device sensitive pins such as the inputs. An optional supply decoupling capacitor across the two power supplies (for split supply operation) improves second harmonic distortion performance. 11 Layout 11.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier, like the THS309x, requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include the following: • • • • 34 Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Minimize the distance [< 0.25 inch (6.35 mm)] from the power supply pins to high-frequency 0.1-μF and 100-pF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 μF or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. Careful selection and placement of external components preserve the high-frequency performance of the THS309x. Resistors should be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use wire-bound type resistors in a high-frequency application. Because the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2 kΩ, this parasitic capacitance can add a pole or a zero (or both) that can effect circuit operation. Keep resistor values as low as possible, consistent with load-driving considerations. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces [0.05 inch (1.3 mm) to 0.1 inch (2.54 mm)] should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an RS because the THS309x are nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 www.ti.com • THS3091, THS3095 SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 If a long trace is required, and the 6-dB signal loss intrinsic to a doubly terminated transmission line is acceptable, then implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS309x is used as well as a terminating shunt resistor at the input of the destination device. Also remember that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, then a long trace can be series- terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, then there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. Socketing a high-speed part like the THS309x is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS309x parts directly onto the board. 11.2 Layout Example Figure 11-1. Layout Recommendation Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 35 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 PIN8 (2) REF (2) JP1 (2) C9 J4 VS− FB1 C3 6.8 µF TP2 (2) JP2 (2) THS3095 EVM Only FB2 VS− VS+ + C4 0.1 µF + (2) C10 J6 VS+ J5 GND TP1 R9 C7 0.1 µF C6 6.8 µF J1 R3 R4 1 kΩ R1 249 Ω 0Ω PIN8 VS+ J2 R5 REF 2 Open R7 7 8 1 6 3 49.9 Ω 4 5 R2 49.9 Ω VS− J3 R8 Open R6 Open THS3091DDA or THS3095DDA Figure 11-2. THS3091 EVM Circuit Configuration Figure 11-3. THS3091 EVM Board Layout (Top Layer) 36 Figure 11-4. THS3091 EVM Board Layout (Second and Third Layers) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 Figure 11-5. THS3091 EVM Board Layout (Bottom Layer) 11.3 PowerPAD Design Considerations The THS309x are available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe on which the die is mounted [see Figure 11-6(a) and Figure 11-6(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 11-6(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that devices such as the THS309x have no electrical connection between the PowerPAD and the die. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 11-6. Views of Thermal Enhanced Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 37 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 0.300 (7,62) 0.100 (2,54) 0.035 (0,89) 0.010 (0,254) 0.026 (0,66) 0.030 (0,732) 0.060 (1,52) 0.140 (3,56) 0.176 (4,47) 0.050 (1,27) 0.060 (1,52) 0.010 (0.254) vias 0.035 (0,89) 0.080 (2,03) All Units in inches (millimeters) Figure 11-7. DDA PowerPAD PCB Etch and Via Pattern 11.4 PowerPAD Layout Considerations 1. PCB with a top-side etch pattern is shown in Figure 11-7. There should be etch for the leads as well as etch for the thermal pad. 2. Place 13 holes in the area of the thermal pad. These holes should be 0.01 inch (0.254 mm) in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS309x IC. These additional vias may be larger than the 0.01-inch (0.254 mm) diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. Note that the PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any potential voltage such as VS– is acceptable as there is no electrical connection to the silicon. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS309x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its 13 holes exposed. The bottom-side solder mask should cover the 13 holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 11.5 Power Dissipation and Thermal Considerations The THS309x incorporates automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately 160°C. When the junction temperature reduces to approximately 140°C, the amplifier turns on again. But, for maximum performance and reliability, the designer must ensure that the design does not exceed a junction temperature of 125°C. Between 125°C and 150°C, damage does not occur, but the performance of the amplifier begins to degrade and long-term reliability suffers. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. P Dmax + T max * T A q JA where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (°C). TA is the ambient temperature (°C). θJA = θJC + θCA θJC is the thermal coefficient from the silicon junctions to the case (°C/W). θCA is the thermal coefficient from the case to ambient air (°C/W). (4) For systems where heat dissipation is more critical, the THS3091 and THS3095 are offered in an 8-pin SOIC (DDA) with PowerPAD package. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note (PowerPAD™ Thermally Enhanced Package application note). If the PowerPAD is not soldered to the PCB, then the thermal impedance will increase substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance. When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 39 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.1.1 Evaluation Fixtures, Spice Models, and Application Support Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has been developed for the THS309x operational amplifier. The board is easy to use, allowing for straightforward evaluation of the device. The evaluation board can be ordered through the Texas Instruments Web site, www.ti.com, or through your local Texas Instruments sales representative. Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS309x is available through the Texas Instruments Web site (www.ti.com). The Product Information Center (PIC) is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following: • Texas Instruments, PowerPAD™ Made Easy application brief • Texas Instruments, PowerPAD™ Thermally Enhanced Package technical brief • Texas Instruments, Voltage Feedback vs Current Feedback Amplifiers application note • Texas Instruments, Current Feedback Analysis and Compensation application note • Texas Instruments, Current Feedback Amplifiers: Review, Stability, and Application application note • Texas Instruments, Effect of Parasitic Capacitance in Op Amp Circuits application note • Texas Instruments, Expanding the Usability of Current-Feedback Amplifiers analog journal 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 THS3091, THS3095 www.ti.com SLOS423I – SEPTEMBER 2003 – REVISED DECEMBER 2022 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: THS3091 THS3095 41 PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) THS3091D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3091 Samples THS3091DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3091 Samples THS3091DDAG3 ACTIVE SO PowerPAD DDA 8 75 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3091 Samples THS3091DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3091 Samples THS3091DDARG3 ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3091 Samples THS3091DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3091 Samples THS3095D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3095 Samples THS3095DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3095 Samples THS3095DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3095 Samples ACTIVE DGN 8 2500 TBD Call TI Call TI -40 to 85 XTHS3091IDGNR HVSSOP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of