THS4041IDR


   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 D C-Stable Amplifiers Drive Any Capacitive D D D D D D D THS4041 D AND DGN PACKAGE (TOP VIEW) Load High Speed − 165 MHz Bandwidth (−3 dB); CL = 0 pF − 100 MHz Bandwidth (−3 dB); CL = 100 pF − 35 MHz Bandwidth (−3 dB); CL = 1000 pF − 400 V/µs Slew Rate Unity Gain Stable High Output Drive, IO = 100 mA (typ) Very Low Distortion − THD = −75 dBc (f = 1 MHz, RL = 150 Ω) − THD = −89 dBc (f = 1 MHz, RL = 1 kΩ) Wide Range of Power Supplies − VCC = ±5 V to ±15 V Available in Standard SOIC or MSOP PowerPAD Package Evaluation Module Available NULL IN − IN + VCC− RELATED DEVICES RELATED DEVICES DEVICE DESCRIPTION THS4011/2 290-MHz Low Distortion High-Speed Amplifier THS4031/2 100-MHz Low Noise High-Speed Amplifier THS4081/2 175-MHz Low Power High-Speed Amplifiers 8 2 7 3 6 4 5 NULL VCC+ OUT NC NC − No internal connection THS4042 D AND DGN PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VCC− description 1 8 2 7 3 6 4 5 VCC+ 2OUT 2IN − 2IN+ Cross Section View Showing PowerPAD Option (DGN) OUTPUT AMPLITUDE vs FREQUENCY 10 8 CL = 1000 pF CL = 0.1 µF CL = 0 pF CL = 100 pF 6 Output Amplitude − dB The THS4041 and THS4042 are single/dual, high-speed voltage feedback amplifiers capable of driving any capacitive load. This makes them ideal for a wide range of applications including driving video lines or buffering ADCs. The devices feature high 165-MHz bandwidth and 400-V/µsec slew rate. The THS4041/2 are stable at all gains for both inverting and noninverting configurations. For video applications, the THS4041/2 offer excellent video performance with 0.01% differential gain error and 0.01° differential phase error. These amplifiers can drive up to 100 mA into a 20-Ω load and operate off power supplies ranging from ±5V to ±15V. 1 4 2 0 −2 VCC = ±15 V Gain = 1 −6 RF = 200 Ω RL = 150 Ω −8 VO(PP)=62 mV −10 100k 1M 10M 100M f − Frequency − Hz −4 1G CAUTION: The THS4041 and THS4042 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Insruments Incorporated. Copyright  2000, Texas Instruments Incorporated 
 
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    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 AVAILABLE OPTIONS PACKAGED DEVICES TA NUMBER OF CHANNELS PLASTIC SMALL OUTLINE† (D) PLASTIC MSOP† (DGN) MSOP SYMBOL EVALUATION MODULE 1 THS4041CD THS4041CDGN ACO THS4041EVM 2 THS4042CD THS4042CDGN ACC THS4042EVM 1 THS4041D THS4041IDGN ACP — 0°C to 70°C −40°C to 85°C 2 THS4042ID THS4042IDGN ACD † The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4041CDGNR). — functional block diagram VCC 8 Null 1IN− IN− IN+ 2 1 1IN+ 8 6 3 2 1 3 1OUT OUT 2IN− 6 7 Figure 2. THS4041 − Single Channel 2IN+ 2OUT 5 4 VCC− Figure 1. THS4042 − Dual Channel absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating free-air temperature, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 DISSIPATION RATING TABLE PACKAGE θJA (°C/W) θJC (°C/W) 25°C TA = 25 C POWER RATING D 167† 38.3 740 mW DGN‡ 58.4 4.7 2.14 W † This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC proposed High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W. ‡ This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC. For further information, refer to Application Information section of this data sheet. recommended operating conditions MIN Operating free-air temperature, TA MAX ±4.5 ±16 Single supply 9 32 C-suffix 0 70 −40 85 Dual supply Supply voltage, VCC+ and VCC− NOM I-suffix UNIT V °C electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) dynamic performance TEST CONDITIONS† PARAMETER TYP VCC = ±15 V VCC = ±5 V Rf = 200 Ω VCC = ±15 V VCC = ±5 V Rf = 1.3 kΩ Bandwidth for 0.1 dB flatness VCC = ±15 V VCC = ±5 V Rf = 200 Ω Full power bandwidth§ VO(pp) = 20 V, VO(pp) = 5 V, VCC = ±15 V VCC = ±5 V Slew rate‡ VCC = ±15 V, VCC = ±5 V, 20-V step, Gain = 5 400 5-V step, Gain = −1 325 VCC = ±15 V, VCC = ±5 V, 5-V step Settling time to 0.1% VCC = ±15 V, VCC = ±5 V, 5-V step Settling time to 0.01% Dynamic performance small-signal bandwidth (−3 dB) BW SR MIN ts Rf = 200 Ω Rf = 1.3 kΩ Rf = 200 Ω 2-V step 2-V step MAX UNIT 165 Gain = 1 150 MHz 60 Gain = 2 60 MHz 45 Gain = 1 45 MHz 6.3 20 MHz V/ s V/µs 120 Gain = −1 120 ns 250 Gain = −1 280 ns † Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix ‡ Slew rate is measured from an output level range of 25% to 75%. § Full power bandwidth = slew rate / 2 π VO(Peak). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued) noise/distortion performance TEST CONDITIONS† PARAMETER THD Vn In Total harmonic distortion Input voltage noise Input current noise Differential gain error VO(pp) = 2 V, f = 1 MHz, Gain = 2 MIN VCC = ±15 V VCC = ±5 V TYP RL = 150 Ω −75 RL = 1 kΩ −89 RL = 150 Ω −75 RL = 1 kΩ −86 MAX UNIT dBc VCC = ±5 V or ±15 V, VCC = ±5 V or ±15 V, f = 10 kHz 14 nV/√Hz f = 10 kHz 0.9 pA/√Hz Gain = 2, 40 IRE modulation, NTSC, ±100 IRE ramp VCC = ±15 V VCC = ±5 V 0.01% VCC = ±15 V VCC = ±5 V 0.01° Differential phase error Gain = 2, 40 IRE modulation, NTSC, ±100 IRE ramp Channel-to-channel crosstalk (THS4042 only) VCC = ±5 V or ±15 V, f = 1 MHz 0.01% 0.02° Gain = 2 −64 dB † Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix dc performance TEST CONDITIONS† PARAMETER Open loop gain VCC = ±15 V, RL = 1 k Ω VO = ±10 V, TA = 25°C TA = full range VCC = ±5 V, RL = 250 Ω VO = ±2.5 V, TA = 25°C TA = full range Input offset voltage VCC = ±5 V or ±15 V Offset voltage drift VCC = ±5 V or ±15 V IIB Input bias current VCC = ±5 V or ±15 V IOS Input offset current VCC = ±5 V or ±15 V VOS MIN TYP 74 80 69 MAX UNIT 69 dB 76 66 TA = 25°C TA = full range 2.5 TA = full range TA = 25°C 10 10 13 2.5 TA = full range TA = 25°C µV/°C 6 8 35 TA = full range µA A 250 400 Offset current drift TA = full range † Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix mV 0.3 nA nA/°C input characteristics TEST CONDITIONS† PARAMETER VICR Common-mode input voltage range VCC = ±15 V VCC = ±5 V CMRR Common mode rejection ratio VCC = ±15 V, VCC = ±5 V, ri Input resistance VICR = ±12 V VICR = ±2.5 V Ci Input capacitance † Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = full range MIN TYP ±13.8 ±14.3 ± 3.8 ± 4.3 70 90 80 100 MAX UNIT V dB 1 MΩ 1.5 pF 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued) output characteristics TEST CONDITIONS† PARAMETER VO IO Output voltage swing Output current‡ VCC = ±15 V VCC = ±5 V VCC = ±15 V VCC = ±5 V VCC = ±15 V MIN TYP RL = 250 Ω ±11.5 ±13 RL = 150 Ω ±3.2 ±3.5 RL = 1 kΩ ±13 ±13.6 ±3.5 ±3.8 80 100 50 65 RL = 20 Ω VCC = ±5 V VCC = ±15 V MAX UNIT V V mA ISC Short-circuit current‡ 150 mA RO Output resistance Open loop 13 Ω † Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix ‡ Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. power supply TEST CONDITIONS† PARAMETER MIN Dual supply VCC ICC PSRR Supply voltage operating range Single supply MAX ±16.5 9 33 VCC = ±15 V TA = 25°C TA = full range 8 VCC = ±5 V TA = 25°C TA = full range 7 VCC = ±5 V or ±15 V TA = 25°C TA = full range Supply current (per amplifier) Power supply rejection ratio TYP ±4.5 UNIT V 9.5 11 8.5 mA 10 75 70 84 dB † Full range = 0°C to 70°C for C suffix and − 40°C to 85°C for I suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS 2 0 VCC = ±15 V and ±5 V −60 60 −90 40 Phase −120 20 Output Amplitude − dB Gain RL = 1 kΩ Phase − Degrees Open Loop Gain − dB 0.3 1 −30 80 −150 0 −20 1k 10k 10M 100k 1M f − Frequency − Hz 100M 0 −2 −3 −4 −5 −6 100k −180 1G CL = 0 pF CL = 100 pF Output Amplitude − dB 2 0 −2 VCC = ±15 V Gain = 1 −6 RF = 200 Ω RL = 150 Ω −8 VO(PP)=62 mV −10 100k 1M 10M 100M f − Frequency − Hz −4 4 1M 10M 100M f − Frequency − Hz 1G −4 −8 −10 100k 1G 1 CL = 0.01 µF CL = 10 pF VCC = ±15 V Gain = 1 RF = 200 Ω RL = 150 Ω VO(PP)=62 mV 1M 10M 100M f − Frequency − Hz −4 OUTPUT AMPLITUDE vs FREQUENCY 8 0.1 −0.0 RL = 150 Ω VCC = ±5 V Gain = 1 RF = 200 Ω VO = 0.2 Vrms CL = 0 pF CL = 100 pF 1G 6 0 −2 −8 −10 100k 1G 8 2 −6 1M 10M 100M f − Frequency − Hz 10 CL = 1000 pF CL = 0.1 µF 4 −4 VCC = ±5 V Gain = 1 RF = 200 Ω VO = 0.2 Vrms OUTPUT AMPLITUDE vs FREQUENCY Output Amplitude − dB Output Amplitude − dB 0.2 Figure 9 −3 Figure 8 10 1M 10M 100M f − Frequency − Hz −2 −6 100k 1G RL = 150 Ω −1 −5 6 Output Amplitude − dB RL = 1 kΩ 0 Figure 7 RL = 1 kΩ 1G 2 0 −6 0.4 6 1M 10M 100M f - Frequency - Hz OUTPUT AMPLITUDE vs FREQUENCY −2 OUTPUT AMPLITUDE vs FREQUENCY −0.4 100k RL = 150 Ω VCC = ±15 V Gain = 1 RF = 200 Ω VO = 0.2 Vrms Figure 5 2 Figure 6 −0.3 −0.2 6 4 −0.2 −0.1 −0.3 8 6 −0.1 −0.0 −0.4 100k 10 CL = 1000 pF CL = 0.1 µF 0.1 OUTPUT AMPLITUDE vs FREQUENCY 10 0.3 VCC = ±15 V Gain = 1 RF = 200 Ω VO = 0.2 Vrms RL = 1 kΩ 0.2 Figure 4 OUTPUT AMPLITUDE vs FREQUENCY 8 RL = 150 Ω −1 Figure 3 Output Amplitude − dB 0.4 Output Amplitude − dB 100 OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY Output Amplitude − dB OPEN LOOP GAIN AND PHASE RESPONSE vs FREQUENCY VCC = ±5 V Gain = 1 RF = 200 Ω RL = 150 Ω VO(PP)=62 mV Figure 10 • DALLAS, TEXAS 75265 CL = 10 pF 0 −2 −4 −8 1G CL = 0.01 µF 2 −6 1M 10M 100M f − Frequency − Hz POST OFFICE BOX 655303 4 −10 100k VCC = ±5 V Gain = 1 RF = 200 Ω RL = 150 Ω VO(PP)=62 mV 1M 10M 100M f − Frequency − Hz Figure 11 1G 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 16 7 14 6 RL = 150 Ω 4 3 1 0 100k VCC = ±15 V Gain = 2 RF = 1.3 kΩ VO = 0.4 Vrms 8 CL = 10 pF 6 4 2 0 −2 1M 10M f − Frequency − Hz VCC = ±15 V Gain = 2 −4 100k 100M 16 1 14 0 RL = 150 Ω −2 −3 VCC = ±5 V Gain = 2 RF = 1.3 kΩ VO = 0.4 Vrms 1M 10M f − Frequency − Hz 10 8 100M 4 2 −4 100k 1G RL = 1 kΩ CL = 0.1 µF 0 RL = 150 Ω −2 −3 VCC = ±15 V Gain = −1 RF = 2 kΩ VO = 0.2 Vrms 1M 10M f − Frequency − Hz 4 2 8 6 0 CL = 10 pF −4 −6 100M 1G Figure 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 100 pF 2 0 −2 −4 −8 1M 10M 100M f − Frequency − Hz CL = 0.01 µF 4 −6 −8 −10 100k 1G 10 CL = 1000 pF −2 1M 10M 100M f − Frequency − Hz OUTPUT AMPLITUDE vs FREQUENCY VCC = ±15 V Gain = −1 RF = 2 kΩ RL = 150 Ω VO(PP)=62 mV 6 VCC = ±5 V Gain = 2 RF = 1.3 kΩ RL = 150 Ω VO(PP) = 125 mV Figure 17 OUTPUT AMPLITUDE vs FREQUENCY 1 Figure 18 6 −2 1M 10M 100M f − Frequency − Hz CL = 100 pF 8 Figure 16 Output Amplitude − dB Output Amplitude − dB CL = 10 pF CL = 0.01 µF 10 −2 8 −6 100k 12 0 10 −5 14 0 2 1G 16 2 −4 100k 1M 10M 100M f − Frequency − Hz OUTPUT AMPLITUDE vs FREQUENCY CL = 1000 pF 4 OUTPUT AMPLITUDE vs FREQUENCY −4 VCC = ±15 V Gain = 2 RF = 1.3 kΩ RL = 150 Ω VO(PP) = 125 mV Figure 14 6 Figure 15 −1 2 −4 100k 1G VCC = ±5 V Gain = 2 RF = 1.3 kΩ RL = 150 Ω VO(PP)=125 mV CL = 0.1 µF 12 Output Amplitude − dB Output Amplitude − dB RL = 1 kΩ −6 100k 4 OUTPUT AMPLITUDE vs FREQUENCY 2 −5 6 Figure 13 OUTPUT AMPLITUDE vs FREQUENCY −4 CL = 100 pF 8 −2 1M 10M 100M f − Frequency − Hz CL = 0.01 µF 10 0 Figure 12 −1 12 CL = 1000 pF 10 Output Amplitude − dB 2 14 Output Amplitude − dB 5 RF = 1.3 kΩ RL = 150 Ω VO(PP) = 125 mV 12 Output Amplitude − dB Output Amplitude − dB RL = 1 kΩ 16 CL = 0.1 µF Output Amplitude − dB 8 OUTPUT AMPLITUDE vs FREQUENCY VCC = ±15 V Gain = −1 RF = 2 kΩ RL = 150 Ω VO(PP)=62 mV −10 100k 1M 10M 100M f − Frequency − Hz 1G Figure 20 7 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS 1 8 RL = 1 kΩ RL = 150 Ω −2 −3 VCC = ±5 V Gain = −1 RF = 2 kΩ VO = 0.2 Vrms −5 −6 100k 4 2 CL = 10 pF −4 −6 −8 1M 10M f − Frequency − Hz 100M 1M 10M 100M f − Frequency − Hz 1G −40 THD − Total Harmonic Distortion − dB 40 RL = 150 Ω 30 20 5 V Step 1 V Step RF = 2 kΩ RL = 150 Ω 30 20 10 10 5 V Step 0 0 1k 1 10k −70 −80 RL = 1 kΩ −90 −100 100k 10k RL = 150 Ω 1M f − Frequency − Hz Figure 25 Figure 26 DISTORTION vs FREQUENCY DISTORTION vs FREQUENCY DISTORTION vs FREQUENCY −40 −50 Distortion − dB 2nd Harmonic −70 −80 3rd Harmonic 1M 10M f − Frequency − Hz Figure 27 −50 −60 2nd Harmonic −70 −80 3rd Harmonic −90 20M −100 100k 10M 20M −40 VCC = ±15 V Gain = 2 RL = 1 kΩ VO(pp) = 2 V Distortion − dB VCC = ±15 V Gain = 2 RL = 150 Ω VO(pp) = 2 V −60 −100 100k 1k −60 Figure 24 −40 −90 100 −50 VCC = ±15 V Gain = 2 VO(pp) = 2 V Capacitive Load − pF Capacitive Load − pF −50 10 1G TOTAL HARMONIC DISTORTION vs FREQUENCY Gain = −1 Output Overshoot − % RF = 200 Ω 100 1M 10M 100M f − Frequency − Hz Figure 23 OUTPUT OVERSHOOT vs CAPACITIVE LOAD 1 V Step 10 VCC = ±5 V Gain = −1 RF = 2 kΩ RL = 150 Ω VO(PP)=62 mV −4 −8 VCC = ±15 V & ±5 V Gain = 1 1 0 −2 −10 100k 50 40 CL = 100 pF 2 Figure 22 VCC = ±15 V & ±5 V 50 CL = 0.01 µF 4 −6 −10 100k 60 Output Overshoot − % 6 0 −2 OUTPUT OVERSHOOT vs CAPACITIVE LOAD Distortion − dB 8 CL = 1000 pF Figure 21 8 VCC = ±5 V Gain = −1 RF = 2 kΩ RL = 150 Ω VO(PP)=62 mV 6 0 −4 10 CL = 0.1 µF Output Amplitude − dB 10 Output Amplitude − dB Output Amplitude − dB 2 −1 OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY −60 2nd Harmonic −70 −80 −90 1M f − Frequency − Hz 10M 20M Figure 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = ±5 V Gain = 2 RL = 150 Ω VO(pp) = 2 V −100 100k 3rd Harmonic 1M f − Frequency − Hz Figure 29 10M 20M 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS DISTORTION vs OUTPUT VOLTAGE DISTORTION vs FREQUENCY −40 −50 −40 VCC = ±15 V Gain = 5 RL = 150 Ω f = 1 MHz −50 Distortion (dB) −60 2nd Harmonic −70 −80 2nd Harmonic −60 VCC = ±15 V Gain = 5 RL = 1 kΩ f = 1 MHz −60 Distortion (dB) VCC = ±5 V Gain = 2 RL = 1 kΩ VO(pp) = 2 V −50 Distortion − dB DISTORTION vs OUTPUT VOLTAGE 3rd Harmonic −70 2nd Harmonic −70 −80 3rd Harmonic 3rd Harmonic −90 −100 100k −90 −80 −100 −90 1M f − Frequency − Hz 10M 20M 0 5 10 15 VO − Output Voltage − V Figure 30 DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS DIFFERENTIAL GAIN vs NUMBER OF 150-Ω LOADS 0.35° 0.3° Differential Phase 0.4 0.6 Gain = 2 RF = 1.3 kΩ 40 IRE-NTSC Modulation Worst Case ±100 IRE Ramp 0.3 VCC = ±15 V 0.2 Gain = 2 RF = 1.3 kΩ 40 IRE-PAL Modulation Worst Case ±100 IRE Ramp 0.5 Differential Gain − % Gain = 2 RF = 1.3 kΩ 40 IRE-NTSC Modulation Worst Case ±100 IRE Ramp 20 Figure 32 0.4° 0.5 5 10 15 VO − Output Voltage − V Figure 31 DIFFERENTIAL GAIN vs NUMBER OF 150-Ω LOADS Differential Gain − % 0 20 0.25° 0.2° 0.15° 0.4 VCC = ±15 V 0.3 0.2 0.1° 0.1 VCC = ±5 V 0.1 VCC = ±5 V 0.05° VCC = ±5 V VCC = ±15 V 0 0 0° 1 2 1 3 Figure 33 Figure 34 Figure 35 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY VCC = ±5 V VCC = ±15 V PSRR − Power Supply Rejection Ratio − dB Z O − Output Impedance − Ω Differential Phase 0.2° 0.15° VCC = ±5 V & ±15 V Gain = 2 RF = 1 kΩ 10 1 0.05° 0° 2 Number of 150-Ω Loads Figure 36 3 0.1 100k 1M 10M 100M f − Frequency − Hz 1G Figure 37 POST OFFICE BOX 655303 3 PSRR vs FREQUENCY 100 0.25° 1 2 Number of 150-Ω Loads Gain = 2 RF = 1.3 kΩ 40 IRE-PAL Modulation Worst Case ±100 IRE Ramp 0.1° 1 Number of 150-Ω Loads 0.4° 0.3° 3 Number of 150-Ω Loads DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS 0.35° 2 • DALLAS, TEXAS 75265 80 70 VCC = ±15 V & ±5 V +VCC & −VCC Responses 60 50 40 30 20 10 0 100k 1M 10M f − Frequency − Hz 100M Figure 38 9 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY 90 −40 60 50 40 30 −60 −70 20 −90 100k 100M 1M 10M f − Frequency − Hz 300 RL = 150 Ω VCC = ±15 V VO(PP) = 20 V 0.0 260 350 VCC = ±5 V VO(PP) = 5 V VCC = ±15 V 0.01% 240 220 Gain = −1 RF = 360 Ω 200 180 160 VCC = ±15 V & ±5 V 0.1% 140 250 120 200 −40 100 −20 0 20 40 60 80 TA − Free-Air Temperature − °C 1 100 2.40 2.35 −20 0 20 40 60 80 TA − Free-Air Temperature − °C Figure 45 10 VCC = ±15 V −2.0 −2.5 −40 5 100 −20 0 20 40 60 80 TA − Free-Air Temperature − °C 100 Figure 44 OUTPUT VOLTAGE vs SUPPLY VOLTAGE 15 14 TA = 25°C TA = 25°C V 13 VO - Output Voltage - VCC = ±5 V & ±15 V 2.45 2.25 −40 −1.5 COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE V ICR - Common-Mode Input Voltage − ± V − Input Bias Current −µA I IB 2.30 4 VCC = ±5 V −1.0 Figure 43 INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 2.50 3 −0.5 VO − Output Step Voltage − V Figure 42 2.55 2 100k INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE VCC = ±5 V 0.01% 280 100 1k 10k f − Frequency − Hz Figure 41 SETTING TIME vs OUTPUT STEP 400 300 IN 1 Figure 40 Settling Time − ns 450 10 0.10 10 100M V IO − Input Offset Voltage − mV 1M 10M f − Frequency − Hz SLEW RATE vs FREE-AIR TEMPERATURE 500 VN −80 10 0 100k Hz Hz −50 VCC = ±15 V & ±5 V TA = 25°C 100 I n − Current Noise − pA/ 70 −30 V n − Voltage Noise − nV/ 80 1k VCC = ±15 V & ±5 V Gain = 2 RF = 2.7 kΩ RL = 150 Ω Figure 39 SR − Slew Rate − V/µ s VOLTAGE & CURRENT NOISE vs FREQUENCY −20 VCC = ±15 V & ±5 V RF = 1 kΩ VI(pp) = 2 V Crosstalk − dB CMRR − Common Mode Rejection Ratio − dB CMRR vs FREQUENCY 11 9 7 5 12 RL = 1 kΩ 10 8 RL = 150 Ω 6 4 3 2 5 7 9 11 13 ±VCC − Supply Voltage − V 15 Figure 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 7 11 13 9 ±VCC − Supply Voltage − V Figure 47 15 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 15 1-V FALLING EDGE RESPONSE 10 VCC = ±15 V Gain = 1 RF = 200 Ω RL = 150 Ω CL = 0.01 µF 9 7 VCC = ±5 V RL = 1 kΩ 3 VCC = ±15 V RL = 150 Ω 1 −40 9 TA = 85°C 8 TA = 25°C 7 TA = −40°C CL = 10 pF 6 100 0 5 7 9 11 13 ± VCC − Supply Voltage − V 1-V FALLING EDGE RESPONSE VO − Output Voltage − V (1 V/Div) VO − Output Voltage − V (0.5 V / Div) VCC = ±5 V Gain = 1 RF = 200 Ω RL = 150 Ω CL = 100 pF 150 200 250 300 50 Gain = 1 RF = 200 Ω RF = 200 Ω 100 150 200 250 0 0 VCC = ±15 V Gain = −1 RF = 2 kΩ −2 1 1−V Step 0 VCC = ±5 V −1 Gain = −1 RF = 2 kΩ −2 RL = 150 Ω −4 100 200 t − Time − ns Figure 54 300 400 0 100 200 300 400 500 t − Time − ns Figure 55 POST OFFICE BOX 655303 2 VCC = ±15 V 1 RL = 150 Ω 0 CL = 0.01 µF −1 −2 −3 CL = 1000 pF −4 0 250 Gain = −1 3 2 −3 CL = 1000 pF 200 4 RL = 150 Ω −3 150 CAPACITIVE LOAD RESPONSE VO − Output Voltage − V VO − Output Voltage − V 1−V Step 100 Figure 53 5−V Step 3 2 −1 50 t − Time − ns 4 5−V Step 1 CL = 100 pF CL = 10 pF 5-V AND 1-V STEP RESPONSE 4 3 CL = 1000 pF Figure 52 5-V AND 1-V STEP RESPONSE 300 RL = 150 Ω t − Time − ns Figure 51 VO − Output Voltage − V VCC = ±5 V Gain = 1 CL = 100 pF 0 250 VCC = ±15 V CL = 10 pF 350 200 5-V FALLING EDGE RESPONSE CL = 1000 pF t − Time − ns 150 Figure 50 RL = 150 Ω CL = 10 pF 100 100 t − Time − ns 5-V FALLING EDGE RESPONSE CL = 1000 pF 50 50 15 Figure 49 Figure 48 0 CL = 100 pF 5 −20 0 20 40 60 80 TA − Free-Air Temperature − °C CL = 0.01 µF CL = 1000 pF VO − Output Voltage − V (1 V/Div) 5 VO − Output Voltage − V (0.5 V / Div) VCC = ±15 V RL = 250 Ω VCC = ±15 V RL = 1 kΩ 11 I CC − Supply Current − mA VO - Output Voltage - V 13 • DALLAS, TEXAS 75265 −4 0.0 Gain = 1 0.5 1.0 1.5 2.0 2.5 3.0 t − Time − µs Figure 56 11 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS CAPACITIVE LOAD RESPONSE 1-VOLT STEP RESPONSE 0.8 4 VCC = ±5 V RL = 150 Ω 0 CL = 0.01 µF −1 −2 −3 0.6 Gain = 1 0.4 RF = 200 Ω VCC = ±5 V RL = 150 Ω 0.2 0.0 −0.2 −0.4 −0.8 0.5 1.0 1.5 2.0 2.5 3.0 200 100 0.0 −0.2 300 400 0 100 t − Time − ns Figure 57 200 t − Time − ns Figure 58 Figure 59 20-VOLT STEP RESPONSE 5-V STEP RESPONSE 15 3 10 Gain = 5 5 RF = 1.3 kΩ RL = 150 Ω 0 VCC = ±5 V 2 VCC = ±15 V VO − Output Voltage − V VO − Output Voltage − V RL = 150 Ω −0.6 0 t − Time − µs −5 Gain = 1 RF = 200 Ω 1 RL = 150 Ω 0 −1 −2 −10 −15 −3 0 200 400 600 800 1000 0 Figure 60 POST OFFICE BOX 655303 100 200 300 t − Time − ns t − Time − ns 12 RF = 200 Ω 0.2 −0.4 −0.6 Gain = 1 Gain = 1 0.4 VO − Output Voltage − V VO − Output Voltage − V VO − Output Voltage − V 2 1 0.6 VCC = ±15 V Gain = −1 3 −4 0.0 1-VOLT STEP RESPONSE Figure 61 • DALLAS, TEXAS 75265 400 500 300 400 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION theory of operation The THS404x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 62. (7) VCC + (6) OUT IN − (2) IN + (3) (4) VCC − NULL (1) NULL (8) Figure 62. THS4041 Simplified Schematic noise calculations and noise figure Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise ration (SNR) is very important. The noise model for the THS404x is shown in Figure 63. This model includes all of the noise sources as follows: • • • • en = Amplifier internal voltage noise (nV/√Hz) IN+ = Noninverting current noise (pA/√Hz) IN− = Inverting current noise (pA/√Hz) eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx ) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) eRs RS en Noiseless + _ eni IN+ eno eRf RF eRg IN− RG Figure 63. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + Ǹǒ ǒ 2 e nǓ ) IN ) R Ǔ S 2 ǒ ) IN– ǒRF ø RGǓǓ 2 ǒ Ǔ ) 4 kTR s ) 4 kT R ø R F G Where: k = Boltzmann’s constant = 1.380658 × 10−23 T = Temperature in degrees Kelvin (273 +°C) RF || RG = Parallel resistance of RF and RG To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier gain (AV). e no + e ǒ Ǔ R A + e ni 1 ) F (noninverting case) ni V RG As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier Circuits Applications Report (literature number SLVA043). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications. NF + ȱ e 2ȳ 10logȧ ni ȧ 2 ǒ Ǔ e Ȳ Rs ȴ Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: NF + ȱ ȡǒ Ǔ2 ǒ ȧ en ) IN ) ȧ Ȣ ȧ 10logȧ1 ) 4 kTR ȧ S ȧ Ȳ Ǔ ȣȳ S ȧ 2 R Ȥȧ ȧ ȧ ȧ ȧ ȴ Figure 64 shows the noise figure graph for the THS404x. NOISE FIGURE vs SOURCE RESISTANCE 40 f = 10 kHz TA = 25°C 35 Noise Figure (dB) 30 25 20 15 10 5 0 10 100 1k 10k Source Resistance − Ω 100k Figure 64. Noise Figure vs Source Resistance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS404x has been internally compensated to maximize its bandwidth and slew rate performance. Typically when the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin, leading to high frequency ringing or oscillations. However, the THS404x has added internal circuitry that senses a capacitive load and adds extra compensation to the internal dominant pole. As the capacitive load increases, the amplifier remains stable. But, it is not uncommon to see a small amount of peaking in the frequency response. There are typically two ways to compensate for this. The first is to simply increase the gain of the amplifier. This helps by increasing the phase margin to keep peaking minimized. The second is to place an isolation resistor in series with the output of the amplifier, as shown in Figure 65. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. For more information about driving capacitive loads, refer to the Output Resistance and Capacitance section of the Parasitic Capacitance in Op Amp Circuits Application Report (literature number: SLOA013). 1.3 kΩ 1.3 kΩ Input _ 20 Ω Output THS404x + CLOAD Figure 65. Driving a Capacitive Load for Extra Stability offset nulling The THS404x has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4041. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This is shown in Figure 66. VCC+ 0.1 µF + THS4041 _ 10 kΩ 0.1 µF VCC − Figure 66. Offset Nulling Schematic 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB− RG + − VI RS IIB+ V OO +V IO ǒ ǒ ǓǓ 1) R R F VO + "I G IB) R S ǒ ǒ ǓǓ 1) R R F "I G IB– R F Figure 67. Output Offset Voltage Model optimizing unity gain response Internal frequency compensation of the THS404x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 200 Ω should be used as shown in Figure 68. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input + THS404x Output _ 200 Ω Figure 68. Noninverting, Unity Gain Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high frequency performance of the THS404x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS404x evaluation board is available to use as a guide for layout or for evaluating the device performance. D Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components − Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. general PowerPAD design considerations The THS404x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 69(a) and Figure 69(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 69(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 69. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach. Thermal pad area (68 mils x 70 mils) with 5 vias (Via diameter = 13 mils) Figure 70. PowerPAD PCB Etch and Via Pattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 70. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS404xDGN IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS404xDGN package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the THS404xDGN IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) The actual thermal performance achieved with the THS404xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches, then the expected thermal coefficient, θJA, is about 58.4_C/W. For comparison, the non-PowerPAD version of the THS404x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 71 and is calculated by the following formula: P Where: D + ǒ T Ǔ –T MAX A q JA PD = Maximum power dissipation of THS404x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case (°C/W) θCA = Thermal coefficient from case to ambient air (°C/W) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE Maximum Power Dissipation − W 3.5 DGN Package θJA = 58.4°C/W 2 oz. Trace And Copper Pad With Solder 3 DGN Package θJA = 158°C/W 2 oz. Trace And Copper Pad Without Solder 2.5 SOIC Package High-K Test PCB θJA = 98°C/W 2 TJ = 150°C 1.5 1 0.5 SOIC Package Low-K Test PCB θJA = 167°C/W 0 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and PCB size = 3”× 3” Figure 71. Maximum Power Dissipation vs Free-Air Temperature More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially mutiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 72 to Figure 75 show this effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result. When using VCC = ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier package (THS4042), the sum of the RMS output currents and voltages should be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical. THS4041 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS VCC = ±5 V Tj = 150°C TA = 50°C 180 1000 Maximum Output Current Limit Line | IO | − Maximum RMS Output Current − mA | IO | − Maximum RMS Output Current − mA 200 160 140 Package With θJA < = 120°C/W 120 100 SO-8 Package θJA = 167°C/W Low-K Test PCB 80 60 40 Safe Operating Area 20 0 0 1 2 3 4 THS4041 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS TJ = 150°C TA = 50°C VCC = ±15 V Maximum Output Current Limit Line DGN Package θJA = 58.4°C/W 100 SO-8 Package θJA = 98°C/W High-K Test PCB SO-8 Package θJA = 167°C/W Low-K Test PCB Safe Operating Area 10 5 0 3 6 9 12 15 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 73 Figure 72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) THS4042 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS | IO | − Maximum RMS Output Current − mA 200 Maximum Output Current Limit Line Package With θJA ≤ 60°C/W 180 160 140 120 100 SO-8 Package θJA = 167°C/W Low-K Test PCB 80 60 Safe Operating Area 40 VCC = ±5 V TJ = 150°C TA = 50°C Both Channels SO-8 Package θJA = 98°C/W High-K Test PCB 20 0 0 1 2 3 4 5 | VO | − RMS Output Voltage − V Figure 74 THS4042 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS | IO | − Maximum RMS Output Current − mA 1000 VCC = ±15 V TJ = 150°C TA = 50°C Both Channels Maximum Output Current Limit Line 100 SO-8 Package θJA = 98°C/W High-K Test PCB 10 DGN Package θJA = 58.4°C/W Safe Operating Area 1 0 3 SO-8 Package θJA = 167°C/W Low-K Test PCB 6 9 12 | VO | − RMS Output Voltage − V Figure 75 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 

   
    SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION evaluation board An evaluation board is available for the THS4041 (literature number SLOP219) and THS4042 (literature number SLOP233). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 76. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For more information, please refer to the THS4041 EVM User’s Guide or the THS4042 EVM User’s Guide. To order the evaluation board, contact your local TI sales office or distributor. VCC+ + C3 0.1 µF R4 1.3 kΩ IN + C2 6.8 µF NULL R5 49.9 Ω + R3 49.9 Ω OUT THS4041 _ NULL R2 1.3 kΩ + C4 0.1 µF C1 6.8 µF IN − VCC − R1 49.9 Ω Figure 76. THS4041 Evaluation Board POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS4041CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4041C THS4041CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ACO THS4041CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4041C THS4041ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4041I THS4041IDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACP THS4042CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4042C THS4042CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4042C THS4042CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM ACC THS4042CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM ACC THS4042ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM THS4042IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM ACD THS4042IDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM ACD -40 to 85 4042I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of