THS4121CDGKR

THS4120 THS4121 www.ti.com SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004 HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS FEATURES KEY APPLICATIONS • • • • High Performance – 100 MHz, –3 dB Bandwidth – 50 V/µs Slew Rate – 75 dB Total Harmonic Distortion at 1 MHz (VO = 2 VPP) – 5.4 nV/√Hz Input-Referred Noise (10 kHz) Differential Input/Differential Output – Balanced Outputs Reject Common-Mode Noise – Differential Reduced Second Harmonic Distortion Power Supply Range – VDD = 3.3 V Simple Single-Ended To Differential Conversion Differential ADC Driver/Differential Antialiasing Differential Transmitter and Receiver Output Level Shifter • • • THS4121 D, DGN, OR DGK PACKAGE (TOP VIEW) THS4120 D, DGN, OR DGK PACKAGE (TOP VIEW) VIN− VOCM VDD VOUT+ 1 8 2 7 3 6 4 5 VIN− VOCM VDD VOUT+ VIN+ PD GND VOUT− 1 8 2 7 3 6 4 5 VIN+ NC GND VOUT− DESCRIPTION The THS412x is one in a family of fully differential-input, differential-output devices fabricated using Texas Instruments' state-of-the-art submicron CMOS process. The THS412x consists of a true, fully differential signal path from input to output. This results in excellent common-mode noise rejection and improved total harmonic distortion. Table 1. HIGH-SPEED DIFFERENTIAL I/O FAMILY (1) DEVICE NUMBER OF CHANNELS POWERDOWN THS4120 (1) 1 Yes THS4121 1 – For proper functiionality, an external 10-kΩ pullup resistor is required between the PD pin and the positive supply. RELATED DEVICES DESCRIPTION SINGLE SUPPLY VOLTAGE RANGE SPLIT SUPPLY VOLTAGE RANGE THS413x 150 MHz, 51 V/µs, 1.3 nV/√Hz 5 V to 30 V ±2.5 to ±15 THS414x 160 MHz, 450 V/µs, 6.5 nV/√Hz 5 V to 30 V ±2.5 to ±15 THS415x 150 MHz, 650 V/µs, 7.6 nV/√Hz 5 V to 30 V ±2.5 to ±15 DEVICE (1) (1) See the TI Web site for additional high-speed amplifier devices. TYPICAL A/D APPLICATION CIRCUIT VDD 3.3 V VIN VOCM − + AIN + − AIN AVDD AVSS DVDD Vref DIGITAL OUTPUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2004, Texas Instruments Incorporated THS4120 THS4121 www.ti.com SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGED DEVICES TA MSOP PowerPAD™ SMALL OUTLINE(D) 0°C to 70°C –40°C to 85°C EVALUATION MODULES MSOP (DGN) SYMBOL (DGK) SYMBOL THS4120CD THS4120CDGN ARL THS4120CDGK ATZ THS4120EVM THS4121CD THS4121CDGN ASB THS4121CDGK ATO THS4121EVM THS4120ID THS4120IDGN ARM THS4120IDGK ARN – THS4121ID THS4121IDGN ASC THS4121IDGK ASN – ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage, GND to VDD 3.6 V ±VDD VI Input voltage IO Output current (sink) VID Differential input voltage (2) 110 mA ±VDD Continuous total power dissipation See Dissipation Rating Table TJ Maximum junction temperature (3) 150°C TJ Maximum junction temperature, continuous operation, long-term reliability (4) TA Operating free-air temperature Tstg Storage Temperature 125°C C suffix 0°C to 70°C I suffix –40°C to 85°C –65°C to 150°C Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds ESD ratings (1) (2) (3) (4) 300°C HBM 4000 V CDM 1500 V MM 200 V Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The THS412x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPad™ thermally enhanced package. The absolute maximum temperature under any condition is limited by the constraints of the silicon process. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATING TABLE (1) (2) 2 POWER RATING (2) PACKAGE θJA (1) (°C/W) θJC (°C/W) TA = 25°C TA = 85°C D 97.5 38.3 1.02 W 410 mW DGN 58.4 4.7 1.71 W 685 mW DGK 260 54.2 385 mW 154 mW This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. Submit Documentation Feedback THS4120 THS4121 www.ti.com SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS Supply voltage TA Operating free-air temperature TYP MAX ±1.5 ±1.65 ±1.75 Single supply 3 3.3 3.5 C suffix 0 70 –40 85 Split supply VDD MIN I suffix UNIT V °C ELECTRICAL CHARACTERISTICS VDD = 3.3 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE BW Small-signal bandwidth (–3 dB) VDD = 3.3 V, Gain = 1, Rf = 200 Ω SR Slew rate (2) VDD = 3.3 V, Gain = 1 Settling time to 0.1% ts MHz 55 V/µs 60 Differential step voltage = 2 VPP, Gain = 1 Settling time to 0.01% 100 ns 292 DISTORTION PERFORMANCE THD Total harmonic distortion Differential input, differential output Gain = 1, Rf = 200 Ω, RL = 800 Ω, VO = 2 VPP VDD = 3.3 V, f = 1 MHz –75 dB THD Total harmonic distortion Differential input, differential output Gain = 1, Rf = 200 Ω, RL = 800 Ω, VO = 4 VPP VDD = 3.3 V, f = 1 MHz –66 dB Spurious free dynamic range (SFDR) Differential input, differential output, VO = 4 VPP Rf = 200 Ω, f = 1 MHz –69 dB Third intermodulation distortion VI = 0.071 VRMS Gain = 1, f = 10 MHz –75 dBc NOISE PERFORMANCE Vn Input voltage noise f = 10 kHz 5.4 nV/√Hz In Input current noise f = 10 kHz 1 fA/√Hz DC PERFORMANCE Open-loop gain Input offset voltage VS Input offset voltage, referred to VOCM Offset voltage drift IIB Input bias current IOS Input offset current Current offset drift (1) (2) TA = 25°C TA = full range 60 66 dB 66 TA = 25°C 3 8 TA = full range 4 9 TA = 25°C 5 13 TA = full range TA = full range TA = full range TA = full range mV 14 25 µV/°C 1.2 pA 100 5 fA fA/°C The full range temperature is 0°C to 70°C for the C suffix, and –40°C to 85°C for the I suffix. Slew rate is measured differentially from an output level range of 25% to 75%. Submit Documentation Feedback 3 THS4120 THS4121 www.ti.com SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (Continued) VDD = 3.3 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS CMRR Common-mode rejection ratio TA = full range 64 96 dB VICR Common-mode input voltage range TA = full range 0.65 to VDD – 0.1 0.35 to VDD V ri Input resistance (dc level) Measured into each input terminal 820 MΩ Ci Input capacitance, closed loop 3 pF ro Output resistance 1 Ω V See Figure 16 OUTPUT CHARACTERISTICS VOH High-level output Voltage VIC = VDD/2, VDD = 3.3 V, TA = 25°C 3.05 3.15 VOL Low-level output Voltage VIC = VDD/2, VDD = 3.3 V, TA = 25°C 0.25 0.15 V IO Output current (sink), RL = 7 Ω VDD = 3.3 V, TA = 25°C 80 100 mA IO Output current (source), RL = 7 Ω VDD = 3.3 V, TA = 25°C 20 25 mA 3.3 V POWER SUPPLY VDD Supply voltage range Single supply IDD Quiescent current (per amplifier) VDD = 3.3 V PSRR Power-supply rejection ratio TA = 25°C TA = 25°C 11 13.5 TA = full range mA 16 68 85 dB POWER-DOWN CHARACTERISTICS (THS4120 ONLY) Power-down voltage level (2) Power-down quiescent current ton Turn-on time delay toff Turn-off time delay zo Output impedance (1) (2) Enable >1.4 Power down