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THS4130, THS4131
SLOS318I – MAY 2000 – REVISED AUGUST 2015
THS413x High-Speed, Low-Noise, Fully-Differential I/O Amplifiers
1 Features
3 Description
•
The THS413x device is one in a family of fullydifferential input/differential output devices fabricated
using Texas Instruments' state-of-the-art BiComI
complementary bipolar process.
1
•
•
•
•
High Performance
– 150 MHz, –3 dB Bandwidth (VCC = ±15 V)
– 51 V/µs Slew Rate
– –100 dB Third Harmonic Distortion at
250 kHz
Low Noise
– 1.3 nV/√Hz Input-Referred Noise
Differential-Input/Differential-Output
– Balanced Outputs Reject Common-Mode
Noise
– Reduced Second-Harmonic Distortion Due to
Differential Output
Wide Power-Supply Range
– VCC = 5 V Single Supply to ±15 V Dual Supply
ICC(SD) = 860 µA in Shutdown Mode (THS4130)
Device Information(1)
PART NUMBER
THS4130
THS4131
BODY SIZE (NOM)
4.90 mm x 3.91 mm
VSSOP (8)
3.00 mm x 3.00 mm
HVSSOP (8)
3.00 mm x 3.00 mm
SOIC (8)
4.90 mm x 3.91 mm
VSSOP (8)
3.00 mm x 3.00 mm
HVSSOP (8)
3.00 mm x 3.00 mm
Single-Ended To Differential Conversion
Differential ADC Driver
Differential Antialiasing
Differential Transmitter And Receiver
Output Level Shifter
Typical A/D Application Circuit
Total Harmonic Distortion vs Frequency
−20
5V
VOCM
+
−
AIN
−
+
AIN
−5 V
AVDD
AVSS
DVDD
Vref
DIGITAL
OUTPUT
THD − Total Harmonic Distortion − dB
VDD
VIN
PACKAGE
SOIC (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
The THS413x is made of a true fully-differential signal
path from input to output. This design leads to an
excellent common-mode noise rejection and
improved total harmonic distortion.
VOUT = 2 VPP
−30
−40
−50
−60
VCC = 5 V to ± 5 V
−70
−80
−90
−100
100 k
VCC = ± 15 V
1M
f − Frequency − Hz
10 M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4130, THS4131
SLOS318I – MAY 2000 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Tables...................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
11.3 General PowerPAD Design Considerations ......... 24
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (May 2011) to Revision I
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Revision G (January 2010) to Revision H
•
Page
Changed footnote A in Figure 45. ........................................................................................................................................ 25
Changes from Revision F (January 2006) to Revision G
•
2
Page
Changed DGK package specifications in the Dissipation Rating table .................................................................................. 7
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SLOS318I – MAY 2000 – REVISED AUGUST 2015
5 Device Comparison Tables
Table 1. Available Device Packages
PACKAGED DEVICES
MSOP PowerPAD™
SMALL OUTLINE
(D)
TA
0°C to +70°C
–40°C to +85°C
(DGN)
MSOP
SYMBOL
(DGK)
SYMBOL
EVALUATION
MODULES
THS4130CD
THS4130CDGN
AOB
THS4130CDGK
ATP
THS4130EVM
THS4131CD
THS4131CDGN
AOD
THS4131CDGK
ATQ
THS4131EVM
THS4130ID
THS4130IDGN
AOC
THS4130IDGK
ASO
—
THS4131ID
THS4131IDGN
AOE
THS4131IDGK
ASP
—
Table 2. Device Description Table
DEVICE
DESCRIPTION
THS412x
100 MHz, 43 V/µs, 3.7 nV/√Hz
THS414x
160 MHz, 450 V/µs, 6.5 nV/√Hz
THS415x
180 MHz, 850 V/µs, 9 nV/√Hz
6 Pin Configuration and Functions
D, DGN, or DGK Package
8-Pin SOIC, VSSOP, or HVSSOP
THS4130 Top View
VINVOCM
VCC+
VOUT+
1
2
3
4
8
7
6
5
D, DGN, or DGK Package
8-Pin SOIC, VSSOP, or HVSSOP
THS4131 Top View
VIN+
PD
VCCVOUT-
VINVOCM
VCC+
VOUT+
1
2
3
4
8
7
6
5
VIN+
NC
VCCVOUT-
Pin Functions
PIN
NAME
THS4130
THS4131
I/O
DESCRIPTION
NC
—
7
—
PD
7
—
I
No connect
Active low powerdown pin
VCC+
3
3
I/O
Positive supply voltage pin
VCC–
6
6
I/O
Negative supply voltage pin
VIN–
1
1
I
Negative input pin
VOCM
2
2
I
Common mode input pin
VOUT+
4
4
O
Positive output pin
VOUT–
5
5
O
Negative output pin
VIN+
8
8
I
Positive input pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
Input voltage
VCC– to VCC+
Supply voltage
IO (2)
Output current
VID
Differential input voltage
MIN
MAX
UNIT
–VCC
+VCC
V
–33
–6
Continuous total power dissipation
33
V
150
mA
6
V
See Dissipation Ratings
TJ (3)
Maximum junction temperature
150
°C
TJ (4)
Maximum junction temperature, continuous operation, long-term reliability
125
°C
TA
Operating free-air temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
C-suffix
0
70
°C
I-suffix
–40
85
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS413x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD
thermally-enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
7.2 ESD Ratings
VALUE
UNIT
THS4130: D, DGN, OR DGK PACKAGES
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (1)
±1500
V
THS4131: D, DGN, OR DGK PACKAGES
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Vcc+ to Vcc–
TA
4
Dual supply
Single supply
C-suffix
I-suffix
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NOM
MAX
±2.5
±15
5
30
0
70
–40
85
UNIT
V
°C
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7.4 Thermal Information
THS413x
THERMAL METRIC
(1)
D (SOIC)
DGN (VSSOP)
DGK
(HVSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
114.5
55.8
182.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60.3
61.6
72.3
°C/W
RθJB
Junction-to-board thermal resistance
54.8
34.5
103.5
°C/W
ψJT
Junction-to-top characterization parameter
14
13.8
11.6
°C/W
ψJB
Junction-to-board characterization parameter
54.3
34.4
101.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics (1)
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MA
UNIT
X
DYNAMIC PERFORMANCE
Small-signal bandwidth (–3 dB),
single-ended input, differential
output, VI = 63 mVPP
VCC = 5
Gain = 1, Rf
= 390 Ω
125
VCC = ±5
Gain = 1, Rf
= 390 Ω
135
VCC = ±15
Gain = 1, Rf
= 390 Ω
150
VCC = 5
Gain = 2, Rf
= 750 Ω
80
VCC = ±5
Gain = 2, Rf
= 750 Ω
85
VCC = ±15
Gain = 2, Rf
= 750 Ω
90
BW
Small-signal bandwidth (–3 dB),
single-ended input, differential
output, VI = 63 mVPP
SR
ts
MHz
Slew rate (2)
Gain = 1
Settling time to 0.1%
Step voltage = 2 V, gain = 1
78
Settling time to 0.01%
Step voltage = 2 V, gain = 1
213
52
V/µs
ns
DISTORTION PERFORMANCE
VCC = 5
TH
D
Total harmonic distortion,
differential input, differential
output, gain = 1, Rf = 390 Ω, RL =
800 Ω, VO= 2 VPP
VCC = ±5
VCC = ±15
VCC = ±5
VO = 4 VPP
VCC = ±15
SF
DR
(1)
(2)
Spurious-free dynamic range,
differential input, differential
output, gain = 1, Rf = 390 Ω,
RL = 800 Ω, f = 250 kHz
VO= 2 VPP
VO = 4 VPP
f = 250 kHz
–95
f = 1 MHz
–81
f = 250 kHz
–96
f = 1 MHz
–80
f = 250 kHz
–97
f = 1 MHz
–80
f = 250 kHz
–91
f = 1 MHz
–75
f = 250 kHz
–91
f = 1 MHz
–75
VCC = ±2.5
97
VCC = ±5
98
VCC = ±15
99
VCC = ±5
93
VCC = ±15
95
dBc
dB
The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
Slew rate is measured from an output level range of 25% to 75%.
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Electrical Characteristics(1) (continued)
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MA
UNIT
X
Third intermodulation distortion
VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz
–53
dBc
Third-order intercept
VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz
41.5
dB
NOISE PERFORMANCE
Vn
Input voltage noise
f = 10 kHz
1.3
nV/√
Hz
In
Input current noise
f = 10 kHz
1
pA/√
Hz
DC PERFORMANCE
Open-loop gain
Input offset voltage
V(O Common-mode input offset
S)
voltage, referred to VOCM
TA = +25°C
71
TA = full range
69
TA = +25°C
78
0.2
TA = full range
dB
2
3
TA = +25°C
0.2
Input offset voltage drift
TA = full range
4.5
IIB
Input bias current
TA = full range
2
IOS
Input offset current
TA = full range
mV
3.5
µV/°
C
6
100 500
µA
nA
2
nA/°
C
95
dB
–3.7
–4 to
7 to
4.5
4.3
V
Offset drift
INPUT CHARACTERISTICS
CM
Common-mode rejection ratio
RR
VIC
R
Common-mode input voltage
range
RI
Input resistance
CI
Input capacitance, closed loop
ro
Output resistance
TA = full range
80
Measured into each input terminal
34
MΩ
4
pF
Open loop
41
Ω
OUTPUT CHARACTERISTICS
TA = +25°C
1.2
to
3.8
0.9
to
4.1
TA = full
range
1.3
to
3.7
±4
VCC = 5 V
Output voltage swing
VCC = ±5 V
VCC = ±15 V
6
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TA = +25°C
±3.7
TA = full
range
±3.6
TA = +25°C
±10.
5
TA = full
range
±10.
2
V
±12.
4
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Electrical Characteristics(1) (continued)
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VCC = 5 V, RL = 7 Ω
IO
VCC = ±5 V, RL = 7 Ω
Output current
VCC = ±15 V, RL = 7 Ω
MIN
TYP
TA = +25°C
25
45
TA = full
range
20
TA = +25°C
30
TA = full
range
28
TA = +25°C
60
TA = full
range
65
MA
UNIT
X
55
mA
85
POWER SUPPLY
VC
Single supply
Supply voltage range
Split supply
C
4
33
±2
±16
.5
TA = +25°C
ICC
Quiescent current
ICC( Quiescent current (shutdown)
(THS4130 only) (3)
SD)
PS
RR
(3)
12.3
VCC = ±5 V
TA = full
range
VCC = ±15 V
TA = +25°C
14
TA = +25°C
0.86
V = –5 V
Power-supply rejection ratio (dc)
15
16
TA = full
range
73
TA = full
range
70
mA
1.4
1.5
TA = +25°C
V
mA
98
dB
For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section.
7.6 Dissipation Ratings
POWER RATING (2)
(1)
(2)
PACKAGE
θJA (1) (°C/W)
θJC (°C/W)
TA= +25°C
TA = +85°C
D
97.5
38.3
1.02 W
410 mW
DGN
58.4
4.7
1.71 W
685 mW
DGK
134
72
750 mW
300 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
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7.7 Typical Characteristics
25
3
RL = 800 W,
VCC = ± 5 V,
VI = 63 mVPP
Gain = 10_Rf = 4 kW
20
1
Gain = 5_Rf = 2 kW
Rf = 620 W
0
Output − dB
Output −dB
15
Gain = 1,
RL = 800 W,
VCC = ± 5 V,
VI = 63 mVPP
2
10
Gain = 2_Rf = 750 W
5
−1
Rf = 390 W
−2
−3
−4
Gain = 1_Rf = 390 W
−5
0
−6
−5
−7
−10
100 k
1M
10 M
100 M
f − Frequency − Hz
−8
100 k
1G
1M
10 M
100 M
f − Frequency − Hz
Figure 2. Small-Signal Frequency Response
Figure 1. Small-Signal Frequency Response
2
3
VCC= ±15
1
2
CF = 0 pF
1
0
0
−1
VCC= 5
Output − dB
Output − dB
−1
−2
−3
−4
−7
1M
−8
−9
10 M
100 M
f − Frequency − Hz
−10
100 k
1G
CL = 10 pF
1G
VO+
Large Signal Transient Response − V
Output − dB
10 M
100 M
f − Frequency − Hz
1
Gain = 1,
RL = 800 W,
VCC = ± 5 V,
VI = 63 mVPP,
Rf = 390 W
1
−0
CL = 0 pF
−1
−2
−3
−4
−5
−6
−7
−8
100 k
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 5. Small-Signal Frequency Response (Various CL)
8
1M
Figure 4. Small-Signal Frequency Response (Various CF)
5
2
CF = 1 pF
−4
−7
Figure 3. Small-Signal Frequency Response (Various
Supplies)
3
−3
−6
Gain = 1,
RL = 800 W,
Rf = 390 W,
VI = 63 mVPP
−8
100 k
4
−2
−5
−5
−6
1G
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0.5
0
VO−
−0.5
0.5
0
VI (Diff)
−0.5
−1
0
0.1
0.2
0.4
0.3
t − Time − ms
0.5
0.6
Figure 6. Large-Signal Transient Response (Differential
In/Single Out)
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Typical Characteristics (continued)
5
CMRR − Common Mode Rejection Ratio − dB
−50
VCC = ± 15 V
0
Output − dB
−5
−10
VCC = ± 5 V
−15
−20
Gain = 1
Rf = 390 W,
RL = 800 W,
CF = 0 pF,
VI = 0.2 VRMS
−25
100 k
VCC = 5 V
1M
10 M
100 M
Rf = 1 kW,
VCC = ± 5 V
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
100 k
1G
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 7. Large-Signal Frequency Response
100 M
Figure 8. Common-Mode Rejection Ratio vs Frequency
940
15
14.5
920
I CC − Supply Current − m A
I CC − Supply Current − mA
14
VCC = ± 15 V
13.5
13
12.5
VCC = ± 5 V
12
11.5
900
880
860
840
11
820
10.5
10
−40
−20
0
20
40
60
80
800
−50
−25
0
25
50
75
100
TA − Free-Air Temperature (Shutdown State) − °C
100
TA − Free-Air Temperature − °C
Figure 10. Supply Current vs Free-Air Temperature
(Shutdown State)
2.4
2.04
2.35
2.02
VO − Output Voltage − V
IIB− Input Bias Current − m A
Figure 9. Supply Current vs Free-Air Temperature
2.3
IIB+
2.25
2.2
2.15
2
RF = 510 W
CF = 1 pF,
VCC = 5 V
VO = 4 VPP
RL = 800 W
1.98
1.96
1.94
IIB−
2.1
2.05
−50
1.92
1.9
−25
0
25
50
75
TA − Free-Air Temperature − °C
100
0
Figure 11. Input Bias Current vs Free-Air Temperature
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25
50
75
100
t − Time − ns
125
150
Figure 12. Settling Time
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Typical Characteristics (continued)
−50
2.5
Gain = 1,
Rf = 330 W,
RL = 400 W
1.5
−60
VCC = 5 V
−70
−80
VCC = −5 V
G = 1,
Rf = 390 W,
RL = 800 W,
CF = 0 pF,
CL = 10 pF,
VI_Peak = 2 V,
VCC = ± 15 V
TA = 25°C
1
5
0
−5
−1
−1.5
−90
−2
VO−
−100
10 k
100 k
1M
10 M
f − Frequency (Differential Out) − Hz
−2.5
100 M
0
80
120
160
200
Figure 14. Large-Signal Transient Response
−20
−30
VOUT = 2 VPP
−40
−50
−60
VO = 2 VPP,
RL = 800 W,
Rf = 390 W,
G=1
−40
Second Harmonic Distortion − dBc
−30
40
t − Time − nS
Figure 13. Power-Supply Rejection Ratio vs Frequency
(Differential Out)
THD − Total Harmonic Distortion − dB
VO+
2
VO − Output Voltage − V
PSRR − Power Supply Rejection Ratio − dB
−40
VCC = 5 V to ± 5 V
−70
−80
VCC = ± 15 V
−90
Single Ended Input
Differential Output
−50
−60
VCC = 5 V
−70
−80
−90
−100
VCC = ±15V, ±5V
−100
100k
1M
f − Frequency − Hz
−110
100 k
10M
Figure 15. Total Harmonic Distortion vs Frequency
−92
−60
VO = 4 VPP,
RL = 800 W,
Rf = 390 W,
G=1
Single Ended Input
Differential Output
VCC = ± 5 V
−70
−80
VCC = ± 15 V
−90
−100
−110
100 k
10 M
Figure 17. Second-Harmonic Distortion vs Frequency
10
−96
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VCC = ± 5 V
VCC = 5 V
−98
VCC = ± 15 V
−100
−102
−104
−106
1M
f − Frequency − Hz
f = 250 KHz
RL = 800 W,
Rf = 390 W,
G=1
−94
Second Harmonic Distortion − dBc
Second Harmonic Distortion − dBc
−50
10 M
Figure 16. Second-Harmonic Distortion vs Frequency
−30
−40
1M
f − Frequency − Hz
Single Ended Input
Differential Output
0
1
2
3
4
5
VO − Output Voltage − V
6
7
Figure 18. Second-Harmonic Distortion vs Output Voltage
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Typical Characteristics (continued)
−88
−30
VO = 4 VPP
RL = 800 W,
Rf = 390 W,
G=1
VCC = ±15 V
−40
−92
−94
Third Harmonic Distortion − dBc
Second Harmonic Distortion − dBc
−90
VCC = ± 5 V
−96
−98
VCC = 5 V
−100
−102
Single Ended Input
Differential Output
−104
−106
0
1
f = 500 KHz
RL = 800 W,
Rf = 390 W,
G=1
2
3
4
5
VO − Output Voltage − V
6
−50
−60
−80
−90
−100
10 M
Figure 20. Third-Harmonic Distortion vs Frequency
−90
Third Harmonic Distortion − dBc
Third Harmonic Distortion − dBc
1M
f − Frequency − Hz
−88
VO = 2 VPP,
RL = 800 W,
Rf = 390 W,
Gain = 1
−40
−50
Single Ended Input
Differential Output
−60
−70
VCC = ± 15 V
−80
VCC = ± 5 V
−90
VCC = 5 V
−100
VCC = ± 15 V
−92
−94
VCC = ± 5 V
−96
VCC = 5 V
−98
f = 500 KHz
RL = 800 W,
Rf = 390 W,
G=1
−100
−102
−104
Single Ended Input
Differential Output
−106
−110
100 k
1M
f − Frequency − Hz
0
10 M
1
2
3
4
5
6
7
VO − Output Voltage − V
Figure 21. Third-Harmonic Distortion vs Frequency
Figure 22. Third-Harmonic Distortion vs Output Voltage
−88
10
−92
VCC = ± 5 V
Vn − Voltage Noise − nV/ Hz
f = 250 KHz
RL = 800 W,
Rf = 390 W,
G=1
−90
Third Harmonic Distortion − dBc
Single Ended Input
Differential Output
−110
100 k
−30
−94
−96
VCC = 5 V
−98
VCC = ± 15 V
−100
−102
−104
−106
VCC = ± 15 V
−70
7
Figure 19. Second-Harmonic Distortion vs Output Voltage
VCC = ± 5 V
Single Ended Input
Differential Output
1
0
1
2
3
4
5
VO − Output Voltage − V
6
7
10
100
1k
10 k
100 k
f − Frequency − Hz
Figure 23. Third-Harmonic Distortion vs Output Voltage
Figure 24. Voltage Noise vs Frequency
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Typical Characteristics (continued)
7E−12
1000
V(OS) − Input Offset Voltage − m V
I n − Current Noise − pA/ Hz
6E−12
5E−12
4E−12
3E−12
2E−12
1E−12
0
800
VCC =± 2.5 V
600
400
200
VCC =± 5 V
0
VCC =± 15 V
−200
−400
1
10
100
1k
f − Frequency − Hz
10 k
100 k
Figure 25. Current Noise vs Frequency
−600
−12
VCC =± 5 V
VCC = ± 15 V
VOUT+
VOUT+
VCC = ± 5 V
VOUT−
VCC = ± 5 V
zo − Output impedance − W
5
0
−5
−10
12
100
Rf = 1 k
G=2
10
−9
−6
−3
0
3
6
9
VOCM − Common-Mode Output Voltage − V
Figure 26. Input Offset Voltage vs Common-Mode Output
Voltage
15
VO − Output Voltage − V
Rf = 1 k,
RL = 800 W,
G=1
VOUT−
10
1
VCC = ± 15 V
−15
100
1000
10 k
RL − Differential Load Resistance − W
100 k
Figure 27. Output Voltage vs Differential Load Resistance
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0.1
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 28. Output Impedance vs Frequency
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8 Detailed Description
8.1 Overview
The THS413x is a fully-differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully-differential amplifiers are differential in/differential out.
Differential Amplifier
Rf
R(g)
THS413x
Fully differential Amplifier
VCC+
_
_
VIN−
VIN+
+
VO+
+
+
R(g)
Rf
_
VO−
VOCM
VCC−
Figure 29. Differential Amplifier Versus a Fully-Differential Amplifier
To understand the THS413x fully-differential amplifiers, the definition for the pin outs of the amplifier are
provided.
(V ) + (VI- )
Input voltage definition VID = (VI+ ) - (VI- ) VIC = I+
(1)
2
V
V
+
( ) ( O- )
Output voltage definition VOD = (VO + ) - (VO - ) VOC = O +
(2)
2
Transfer function VOD = VID ´ A (f )
(3)
Output common mode voltage VOC = VOCM
Differential Structure Rejects
Coupled Noise at The Input
VIN−
VIN+
Differential Structure Rejects
Coupled Noise at The Power Supply
(4)
Differential Structure Rejects
Coupled Noise at The Output
VCC+
_
+
+
_
VO+
VO−
VOCM
VCC−
Figure 30. Definition of the Fully-Differential Amplifier
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
1
VO = VI
(5)
2
The second output is equal and opposite in sign:
1
VO = - VI
2
(6)
Fully-differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully-differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it is not as practical to feed a 2-VPP signal into the
targeted ADC. Using a fully-differential amplifier enables the user to break down the output into two 1-VPP signals
with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been
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Overview (continued)
able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully-differential amplifier. The
final result indicates twice as much dynamic range. Figure 31 illustrates the increase in dynamic range. The gain
factor should be considered in this scenario. The THS413x fully-differential amplifier offers an improved CMRR
and PSRR due to its symmetrical input and output. Furthermore, second-harmonic distortion is improved. Second
harmonics tend to cancel because of the symmetrical output.
a
VOD= 1−0 = 1
VCC+
+1
_
VIN−
VIN+
+
+
_
VO+
0
VO−
+1
0
VOCM
VOD = 0−1 = −1
VCC−
b
Figure 31. Fully-Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully-differential amplifier is selected
by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the
differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fullydifferential amplifier. Figure 32 depicts the general format of instrumentation amplifiers.
The general transfer function for this circuit is:
VOD
R æ
2R2 ö
= f 1+
VIN1 - VIN2 R(g) çè
R1 ÷ø
(7)
THS4012
VIN1
R(g)
+
_
Rf
R2
_
R1
THS413x
+
R2
_
VIN2
+
THS4012
R(g)
Rf
Figure 32. Instrumentation Amplifier
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8.2 Functional Block Diagram
VCC+
Output Buffer
VIN−
x1
VOUT+
C
VIN+
R
Vcm Error
Amplifier
+
_
C
x1
R
VOUT−
Output Buffer
VCC+
30 kW
VCC−
30 kW
VCC−
VOCM
8.3 Feature Description
Figure 33 and Figure 34 depict the differences between the operation of the THS413x fully-differential amplifier in
two different modes. Fully-differential amplifiers can work with differential input or can be implemented as single
in/differential out.
Rf
VIN−
R(g)
VCC+
VO+
−+
Vs
+−
VIN+
VO−
VOCM
R(g)
VCC−
Rf
Note: For proper operation, maintain symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) ⇒ A = R f/R(g)
Figure 33. Amplifying Differential Signals
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Feature Description (continued)
Rf
VIN−
VCC+
R(g)
RECOMMENDED RESISTOR VALUES
VO+
−+
+−
VIN+
Vs
VO−
VOCM
R(g)
GAIN
R(g) W
Rf W
1
2
5
10
390
374
402
402
390
750
2010
4020
VCC−
Rf
Figure 34. Single In With Differential Out
8.4 Device Functional Modes
8.4.1 Power-Down Mode
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS413x is an active low terminal. If it is left as a no-connect terminal, the device always stays on due to an
internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC– = –5 V, then the device is on when PD reaches –3.6 V, (–5 V
+ 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal
to VCC– in order to turn the device off. Figure 35 shows the simplified version of the power-down circuit. While in
the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically
greater than 1 MΩ in the power-down state.
VCC
50 kW
To Internal Bias
Circuitry Control
PD
VCC−
Figure 35. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed loop output impedance is shown in Figure 36.
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Device Functional Modes (continued)
2200
Output Impedance − W
VCC =±5 V
G=1
Rf = 1 kW
PD = VCC−
1200
200
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 36. Output Impedance (in Power-Down) vs Frequency
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Resistor Matching
Resistor matching is important in fully-differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistor. CMRR, PSRR, and cancellation of the second-harmonic distortion
diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCMpin, it is set to the midrail voltage
internally defined as:
(VCC+ ) + (VCC- )
2
(8)
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM
pin as a bypass capacitor. The Functional Block Diagram shows the simplified diagram of the THS413x.
9.1.2 Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS413x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 37. A minimum value of 20 Ω should work well for most applications. For
example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
390 W
20 W
Output
390 W
THS413x
20 W
390 W
Output
390 W
Figure 37. Driving a Capacitive Load
9.1.3 Data Converters
Data converters are one of the most popular applications for the fully-differential amplifiers. Figure 38 shows a
typical configuration of a fully-differential amplifier attached to a differential analog-to-digital converter (ADC).
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Application Information (continued)
VDD
VCC
5V
VIN
+
−
AIN1
−
+
AIN2
VOCM
0.1 mF
AVDD
DVDD
AVSS
Vref
−5 V
VCC−
Figure 38. Fully-Differential Amplifier Attached to a Differential ADC
Fully-differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.
If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the
amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input
terminal of the amplifier should not exceed the common-mode input voltage range.
VDD
VCC
5V
VIN
+
−
AIN1
−
+
AIN2
VOCM
0.1 mF
AVDD
DVDD
AVSS
Vref
Figure 39. Fully-Differential Amplifier Using a Single Supply
9.1.4 Single-Supply Applications
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the circuit configuration of Figure 40 is suggested to bring the common-mode input voltage within
the specifications of the amplifier.
VCC
Rg
VDD
Rf
RPU
VIN
5V
VP V
OCM
−
AIN1
−
+
AIN2
VOUT
RPU
VCC
VOUT
+
AVDD
DVDD
THS1206
0.1 mF
Rg
VCC
AVSS
Vref
Rf
Figure 40. Circuit With Improved Common-Mode Input Voltage
Equation 9 is used to calculate RPU:
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Application Information (continued)
RPU =
VP - VCC
1
1
(VIN - VP ) + (VOUT - VP )
RG
RF
(9)
9.2 Typical Application
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 41 presents a
method by which the noise may be filtered in the THS413x.
Figure 41 shows a typical application design example for the THS413x device in active low-pass filter topology
driving and ADC.
R2
C1
VCC
R4
+
−
VIN−
VIN+
R1
+
VIN+
R(t)
THS413x
−
+
C2
Vs
C3
R3
R1
THS1050
VIN−
VOCM
VOCM
R3
C3
VIC
R4
VCC−
+
C1
R2
Figure 41. Antialias Filtering
9.2.1 Design Requirements
Table 3 shows example design parameters and values for the typical application design example in Figure 41.
Table 3. Design Parameters
DESIGN PARAMETERS
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VALUE
Supply voltage
±2.5 V to ±15 V
Amplifier topology
Voltage feedback
Output control
DC coupled with output common
mode control capability
Filter requirement
500 kHz, Multiple feedback low pass
filter
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9.2.2 Detailed Design Procedure
9.2.2.1 Active Antialias Filtering
Figure 41 shows a multiple-feedback (MFB) lowpass filter. The transfer function for this filter circuit is:
æ
ö
Rt
ö
ç
÷ æ
ç
÷
K
R2
ç
÷
+
2R4
Rt
Hd (f ) = ç
÷ Where K =
2
÷´ç
p
j2
fR4RtC3
R1
f
1
jf
÷÷
ö
ç -æ
÷ çç 1 +
ç ç FSF ´ fc ÷ + Q FSF ´ fc + 1 ÷ è
2R4 + Rt ø
ø
è è
ø
1
FSF ´ fc =
and Q =
2p 2 ´ R2R3C1C2
2 ´ R2R3C1C2
R3C1 + R2C1 + KR3C1
(10)
(11)
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
FSF = Re2 + Im
2
and Q =
Re2 + Im
2
2Re
(12)
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
FSF ´ fc =
1
2pRC 2 ´ mn
and Q =
2 ´ mn
1 + m (1 + K )
(13)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
9.2.3 Application Curve
5
VCC = ± 15 V
0
Output − dB
−5
−10
VCC = ± 5 V
−15
−20
Gain = 1
Rf = 390 W,
RL = 800 W,
CF = 0 pF,
VI = 0.2 VRMS
−25
100 k
1M
VCC = 5 V
10 M
100 M
1G
f − Frequency − Hz
Figure 42. Large-Signal Frequency Response
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10 Power Supply Recommendations
The THS413x device was designed to be operated on power supplies ranging from 2.5V to 15V. Single power
supplies ranging from 5V to 30V can also be used. TI recommends using power-supply accuracy of 5%, or
better. When operated on a board with high-speed digital signals, it is important to provide isolation between
digital signal noise and the analog input pins. The THS413x is connected to power supplies through pin 3 (VCC+)
and pin 6 (VCC-). Each supply pin should be decoupled to GND as close to the device as possible with a lowinductance, surface-mount ceramic capacitor of approximately 10 nF. When vias are used to connect the bypass
capacitors to a ground plane the vias should be configured for minimal parasitic inductance. One method of
reducing via inductance is to use multiple vias. For broadband systems, two capacitors per supply pin are
advised.
To avoid undesirable signal transients, the THS413x device should not be powered on with large inputs signals
present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs
when an ADC is used in the application.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high-frequency performance of the THS413x device, follow proper printed-circuit board
(PCB) high-frequency design techniques. A general set of guidelines is given below. In addition, a THS413x
device evaluation board is available to use as a guide for layout or for evaluating the device performance.
• Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often lead to stability problems. Surface-mount packages soldered directly to
the printed-circuit board are the best implementation.
• Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for highfrequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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11.2 Layout Example
THS413x
Symmetrical
Input Paths
RG
RF
Symmetrical
Output Paths
Figure 43. THS413x EVM Top Layer
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Layout Example (continued)
Separate Vcc+ and
Vcc- planes
Vcc+
Vcc-
Figure 44. THS413x EVM Layer 3
11.3 General PowerPAD Design Considerations
The THS413x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted (see Figure 45a and Figure 45b). This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package (see Figure 45c). Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the previously awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, (PowerPAD Thermally-Enhanced Package, SLMA002). This document
can be found on the TI website (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to SLMA002 when ordering.
24
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: THS4130 THS4131
THS4130, THS4131
www.ti.com
SLOS318I – MAY 2000 – REVISED AUGUST 2015
General PowerPAD Design Considerations (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from
VCC– to VCC+. Typically, the thermal pad is connected to the ground plane because this plane tends to physically be
the largest and is able to dissipate the most amount of heat.
Figure 45. Views of Thermally-Enhanced DGN Package
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: THS4130 THS4131
Submit Documentation Feedback
25
THS4130, THS4131
SLOS318I – MAY 2000 – REVISED AUGUST 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
EVM User's Guide for High-Speed Fully-Differential Amplifier, SLOU101
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THS4130
Click here
Click here
Click here
Click here
Click here
THS4131
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: THS4130 THS4131
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4130CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
0 to 70
4130C
THS4130CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
0 to 70
4130C
THS4130CDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
ATP
THS4130CDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOB
THS4130CDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOB
THS4130CDGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOB
THS4130ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4130I
THS4130IDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASO
THS4130IDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-40 to 85
ASO
THS4130IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASO
THS4130IDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOC
THS4130IDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOC
THS4130IDGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOC
THS4130IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4130I
THS4130IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4130I
THS4131CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
0 to 70
4131C
THS4131CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
0 to 70
4131C
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
Orderable Device
Status
(1)
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4131CDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
ATQ
THS4131CDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
0 to 70
ATQ
THS4131CDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
ATQ
THS4131CDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOD
THS4131CDGNG4
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOD
THS4131CDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOD
THS4131CDGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AOD
THS4131CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
0 to 70
4131C
THS4131ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4131I
THS4131IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4131I
THS4131IDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASP
THS4131IDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-40 to 85
ASP
THS4131IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASP
THS4131IDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOE
THS4131IDGNG4
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOE
THS4131IDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOE
THS4131IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4131I
The marketing status values are defined as follows:
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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