THS4130, THS4131
SLOS318K – MAY 2000 – REVISED AUGUST 2022
THS413x High-Speed, Low-Noise, Fully-Differential I/O Amplifiers
1 Features
3 Description
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The THS413x device is one in a family of fullydifferential input/differential output devices fabricated
using Texas Instruments state-of-the-art high voltage
complementary bipolar process.
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2 Applications
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Single-ended to differential conversion
Differential ADC driver
Differential antialiasing
Differential transmitter and receiver
Output level shifter
Medical ultrasound
The THS413x is made of a true fully-differential signal
path from input to output and high supply capability
of up to ±15 V. This design leads to an excellent
common-mode noise rejection performance (95 dB
at 800 kHz) and total harmonic distortion (−102 dBc
at 2 VPP, 250 kHz). The wide supply range allows
high-voltage differential signal chains to benefit from
its improved headroom and dynamic range without
adding separate amplifiers for each polarity of the
differential signal.
The THS413x is characterized for operation over the
wide temperature range of –40°C to +85°C.
Device Information(1)
PART NUMBER
THS4130
PACKAGE(2)
THS4131
(1)
(2)
4.90 mm × 3.91 mm
MSOP (8)
3.00 mm × 3.00 mm
THS4032
+5 V
± 15 V
CH_A
To TGC VCNTL
DAC8802
THS413x
CH_B
AFE58JD18
-60
Filtering and
Attenuation
Time Gain Control DAC
Reference for Ultrasound
4.90 mm × 3.91 mm
MSOP (8)
3.00 mm × 3.00 mm
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-70
-80
-90
-100
-110
-120
100k
Low-Noise Current to
Voltage Converter
(8) 3.00 mm × 3.00 mm
SOIC (8)
For all available packages, see the orderable addendum at
the end of the data sheet.
See the device comparison table.
-50
± 15 V
BODY SIZE (NOM)
SOIC (8)
MSOP-PowerPAD™
THD - Total Harmonic Distortion (dBc)
•
High performance
– Bandwidth: 170 MHz (VCC = ±15 V, G = 1 V/V)
– Slew rate: 51 V/µs
– Gain bandwidth product: 215 MHz
– Distortion: –102 dBc THD at 2 VPP, 250 kHz
Voltage noise
– 1/f voltage noise corner: 350 Hz
– 1.25 nV/√Hz input-referred noise
Single supply operating range: 5 V to 30 V
Quiescent current (shutdown): 860 µA (THS4130)
1M
Frequency (Hz)
10M
VOUT = 2 VPP
Total Harmonic Distortion vs Frequency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4130, THS4131
www.ti.com
SLOS318K – MAY 2000 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Tables.............................................5
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics: THS413xD,
THS413xDGK ...............................................................7
7.6 Electrical Characteristics: THS413xDGN....................9
7.7 Typical Characteristics: THS413xD, THS413xDGK..11
7.8 Typical Characteristics: THS413xDGN..................... 16
8 Detailed Description......................................................21
8.1 Overview................................................................... 21
8.2 Functional Block Diagram......................................... 21
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................22
9 Application and Implementation.................................. 24
9.1 Application Information............................................. 24
9.2 Typical Application.................................................... 26
10 Power Supply Recommendations..............................28
11 Layout........................................................................... 28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 29
11.3 General PowerPAD Design Considerations............ 30
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 Receiving Notification of Documentation Updates..31
12.3 Support Resources................................................. 31
12.4 Trademarks............................................................. 31
12.5 Electrostatic Discharge Caution..............................31
12.6 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (March 2022) to Revision K (August 2022)
Page
• Updated thermal specifications for DGK package in Thermal Information table................................................ 7
• Changed title of Electrical Characteristics: THS413xD to Electrical Characteristics: THS413xD, THS413xDGK
............................................................................................................................................................................7
• Changed title of Electrical Characteristics: THS413xDGK, THS413xDGN table to Electrical Characteristics:
THS413xDGN ....................................................................................................................................................9
• Changed title of Typical Characteristics: THS413xD to Typical Characteristics: THS413xD, THS413xDGK .. 11
• Changed title of Typical Characteristics to Typical Characteristics: THS413xDGN .........................................16
Changes from Revision I (August 2015) to Revision J (March 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated Features section...................................................................................................................................1
• Updated Applications section............................................................................................................................. 1
• Updated Description section ..............................................................................................................................1
• Updated Available Device Packages table......................................................................................................... 5
• Removed Device Description table.....................................................................................................................5
• Updated Pin Configuration and Functions section..............................................................................................5
• Changed footnote 1 on Absolute Maximum Ratings table to add additional clarification .................................. 6
• Removed minimum supply voltage on Absolute Maximum Ratings table.......................................................... 6
• Added supply turn-on/off dV/dT specification to Absolute Maximum Ratings table..........................................6
• Removed continuous total power dissipation specification in Absolute Maximum Ratings table ...................... 6
• Changed Differential input voltage specification from ±6 to ±1.5 on Absolute Maximum Ratings table ............ 6
• Added continuous input current specification to Absolute Maximum Ratings table ...........................................6
• Changed charged-device model (CDM) reference from JESD22-C101 to JS-002 in ESD Ratings table ......... 6
• Updated thermal specifications for D package in Thermal Information table..................................................... 7
• Changed RθJA from 114.5°C/W to 126.3°C/W in Thermal Information table...................................................... 7
• Changed VSSOP and HVSSOP to MSOP and MSOP-PowerPad in Thermal Information table....................... 7
• Changed RθJC(top) from 60.3°C/W to 67.3°C/W in Thermal Information table.................................................... 7
• Changed small signal bandwidth at G = 1, VCC = 5 V from 125 MHz to 165 MHz in Electrical Characteristics:
THS413xD table................................................................................................................................................. 7
2
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
Changed small signal bandwidth at G = 1, VCC = ±5 V from 135 MHz to 166 MHz in Electrical Characteristics:
THS413xD table................................................................................................................................................. 7
Changed small signal bandwidth at G = 1, VCC = ±15 V from 150 MHz to 170 MHz in Electrical
Characteristics: THS413xD table........................................................................................................................7
Changed small signal bandwidth at G = 2, VCC = 5 V from 80 MHz to 97 MHz in Electrical Characteristics:
THS413xD table................................................................................................................................................. 7
Changed small signal bandwidth at G = 2, VCC = ±5 V from 85 MHz to 98 MHz in Electrical Characteristics:
THS413xD table................................................................................................................................................. 7
Changed small signal bandwidth at G = 2, VCC = ±15 V from 90 MHz to 100 MHz in Electrical Characteristics:
THS413xD table................................................................................................................................................. 7
Changed slew rate from 52 V/µs to 67 V/µs in Electrical Characteristics: THS413xD table.............................. 7
Changed settling time to 0.1% typical specification from 78 ns to 39 ns on Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed settling time to 0.01% typical specification from 213 ns to 61 ns on Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = 5 V, f = 250 kHz from -95 dBc to -101 dBc in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = 5 V, f = 1 MHz from -81 dBc to -87 dBc in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = ±5 V, f = 250 kHz from -96 dBc to -100 dBc in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = ±5 V, f = 1 MHz from -80 dBc to -87 dBc in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = ±15 V, f = 250 kHz from -97 dBc to -102 dBc in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = ±15 V, f = 1 MHz from -80 dBc to -88 dBc in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed THD typical at VCC = ±5 V, f = 250 kHz, VO = 4VPP from -91 dBc to -94 dBc in Electrical
Characteristics: THS413xD table .......................................................................................................................7
Changed THD typical at VCC = ±5 V, f = 1 MHz, VO = 4VPP from -75 dBc to -79 dBc in Electrical
Characteristics: THS413xD table .......................................................................................................................7
Changed THD typical at VCC = ±15 V, f = 250 kHz, VO = 4VPP from -91 dBc to -95 dBc................................... 7
Changed THD typical at VCC = ±15 V, f = 1 MHz, VO = 4VPP from -75 dBc to -80 dBc in Electrical
Characteristics: THS413xD table .......................................................................................................................7
Changed SFDR typical at VCC = ±2.5 V, VO = 2 VPP from 97 dB to 103 dB in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed SFDR typical at VCC = ±5 V, VO = 2 VPP from 98 dB to 106 dB in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed SFDR typical at VCC = ±15 V, VO = 2 VPP from 99 dB to 108 dB in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed SFDR typical at VCC = ±5 V, VO = 4 VPP from 98 dB to 106 dB in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed SFDR typical at VCC = ±15 V, VO = 4 VPP from 95 dB to 100 dB in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed input voltage noise typical from 1.3 nV/√Hz to 1.25 nV/√Hz on Electrical Characteristics: THS413xD
table.................................................................................................................................................................... 7
Changed input current noise typical from 1.3 nV/√Hz to 1.7 nV/√Hz on Electrical Characteristics: THS413xD
table.................................................................................................................................................................... 7
Changed common-mode input offset voltage maximum from 3.5 mV to 5.5 mV in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed typical input offset voltage drift from 4.5 µV/°C to 2 µV/°C in Electrical Characteristics: THS413xD
table ................................................................................................................................................................... 7
Changed typical input bias current spec from 2 µA to 5 µA in Electrical Characteristics: THS413xD table ...... 7
Changed Max input bias current limit from 6 µA to 15.4 µA in Electrical Characteristics: THS413xD table ......7
Changed typical offset current drift from 2 nA/°C to 1 nA/°C in Electrical Characteristics: THS413xD table .... 7
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
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Removed input resistance specification from Electrical Characteristics: THS413xD table ............................... 7
Added common-mode input resistance and differential input resistance specifications to Electrical
Characteristics: THS413xD table .......................................................................................................................7
Removed input capacitance, closed loop specification from Electrical Characteristics: THS413xD table ........ 7
Added common-mode input capacitance, closed loop and differential input capacitance, closed loop
specifications to Electrical Characteristics: THS413xD table ............................................................................ 7
Changed minimum output current at ±15 V, TA = 25℃, from 60 mA to 65 mA in Electrical Characteristics:
THS413xD table ................................................................................................................................................ 7
Changed minimum output current at ±15 V, full temperature range, from 65 mA to 60 mA in Electrical
Characteristics: THS413xD table .......................................................................................................................7
Changed Typical ICC at Vcc = ±5V from 12.3 mA to 10.4 mA in Electrical Characteristics: THS413xD table ....
7
Changed title of Electrical Characteristics table to Electrical Characteristics: THS413xDGK, THS413xDGN ....
9
Changed min/max single power supply range from 4V/33 V to 5V/30 V on Electrical Characteristics:
THS413xDGK, THS413xDGN table to align with recommended operating conditions...................................... 9
Changed min/max dual power supply range from ±2V/±16.5 V to ±2.5 V/±15 V on Electrical Characteristics:
THS413xDGK, THS413xDGN table to align with recommended operating conditions...................................... 9
Removed Dissipation Ratings table....................................................................................................................9
Changed minimum output current under VCC = ±15 V, RL = 7 Ω, TA = +25°C, from 60 mA to 65 mA on
Electrical Characteristics: THS413xDGK, THS413xDGN table..........................................................................9
Changed minimum output current under VCC = ±15 V, RL = 7 Ω, TA = full range, from 65 mA to 60 mA on
Electrical Characteristics: THS413xDGK, THS413xDGN table..........................................................................9
Added new Typical Characteristics section for D package............................................................................... 11
Updated Overview Section............................................................................................................................... 21
Updated Feature Description section............................................................................................................... 22
Updated Power-Down Mode section................................................................................................................ 22
Added Output Common-Mode Voltage section................................................................................................ 24
Updated Resistor Matching section.................................................................................................................. 24
Updated Driving a Capacitive Load section......................................................................................................25
Updated Data Converters section.....................................................................................................................25
Updated Single-Supply Applications section.................................................................................................... 26
Updated large-signal frequency response figure in Application Curve section ................................................28
Updated Power Supply Recommendations section..........................................................................................28
Updated Layout Guidelines section.................................................................................................................. 28
Updated Layout Example section..................................................................................................................... 29
Changed list of documentation in Related Documentation section.................................................................. 31
Changes from Revision H (May 2011) to Revision I (August 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section................................................................................................................................................................ 1
Changes from Revision G (January 2010) to Revision H (May 2011)
Page
• Changed footnote A in Views of Thermally-Enhanced DGN Package ............................................................ 30
Changes from Revision F (January 2006) to Revision G (January 2010)
Page
• Changed DGK package specifications in the Disspation Rating table............................................................... 6
4
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
5 Device Comparison Tables
Table 5-1. Available Device Packages
PACKAGED DEVICES
SOIC
(D)
MSOP PowerPAD™
(DGN)
MSOP
(DGK)
THS4130CD
THS4130CDGN
THS4130CDGK
THS4131CD
THS4131CDGN
THS4131CDGK
THS4130ID
THS4130IDGN
THS4130IDGK
THS4131ID
THS4131IDGN
THS4131IDGK
TA
0°C to +70°C
–40°C to +85°C
6 Pin Configuration and Functions
VIN- 1
8
VIN+
VIN- 1
8
VIN+
VOCM 2
7
PD
VOCM 2
7
NC
VCC+ 3
6
VCC -
VCC+ 3
6
VCC -
VOUT+ 4
5
VOUT-
VOUT+ 4
5
VOUT-
Figure 6-1. D, DGN, or DGK Package,
8-Pin SOIC, MSOP, or MSOP-PowerPAD
THS4130 (Top View)
Figure 6-2. D, DGN, or DGK Package,
8-Pin SOIC, MSOP, or MSOP-PowerPAD
THS4131 (Top View)
Table 6-1. Pin Functions
PIN
NAME
THS4130
THS4131
TYPE(1)
DESCRIPTION
NC
—
7
—
PD
7
—
I
Active low power-down pin
VCC+
3
3
I/O
Positive supply voltage pin
VCC–
6
6
I/O
Negative supply voltage pin
VIN–
1
1
I
Negative input pin
VOCM
2
2
I
Common mode input pin
VOUT+
4
4
O
Positive output pin
VOUT–
5
5
O
Negative output pin
VIN+
8
8
I
Positive input pin
(1)
No connect
I = input, O = output
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VI
Input voltage
VCC– to VCC+
Supply voltage
Supply turn-on/off
Output current
VID
Differential input voltage
IIN
Continuous Input Current
TJ (4)
TJ (5)
TA
Operating free-air temperature
Tstg
Storage temperature
(2)
(3)
(4)
(5)
MAX
UNIT
–VCC
+VCC
V
33
V
1.7
V/µs
150
mA
dV/dT(2)
IO (3)
(1)
MIN
-1.5
1.5
V
10
mA
Maximum junction temperature
150
°C
Maximum junction temperature, continuous operation, long-term reliability
125
°C
C-suffix
I-suffix
0
70
°C
–40
85
°C
–65
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remain off.
The THS413xmay incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD
thermally-enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
7.2 ESD Ratings
VALUE
UNIT
THS4130: D, DGN, OR DGK PACKAGES
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±1500
V
THS4131: D, DGN, OR DGK PACKAGES
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC
±2500
JS-002(2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Vcc+ to Vcc–
TA
6
Dual supply
Single supply
C-suffix
I-suffix
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NOM
MAX
±2.5
±15
5
30
0
70
–40
85
UNIT
V
°C
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.4 Thermal Information
THS413x
THERMAL
METRIC(1)
D (SOIC)
DGN (MSOP-PowerPAD)
DGK (MSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
126.3
55.8
147.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.3
61.6
37.9
°C/W
RθJB
Junction-to-board thermal resistance
69.8
34.5
83.2
°C/W
ψJT
Junction-to-top characterization parameter
19.5
13.8
0.9
°C/W
ψJB
Junction-to-board characterization parameter
69.0
34.4
81.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
8.4
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics: THS413xD, THS413xDGK
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
VCC = 5 V
VCC = ±5 V
BW
Small-signal bandwidth (–3 dB),
single-ended input, differential
output, VI = 63 mVPP
165
Gain = 1, RF = 390 Ω
VCC = ±15 V
170
VCC = 5 V
VCC = ±5 V
97
Gain = 2, RF = 750 Ω
VCC = ±15 V
SR
ts
166
98
100
Slew rate(2)
67
Settling time to 0.1%
39
Settling time to 0.01%
MHz
Step voltage = 2 V
61
V/µs
ns
DISTORTION PERFORMANCE
VCC = 5 V
Total harmonic distortion, differential
input, differential output, VO = 2 VPP
THD
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VO = 4 VPP
VCC = ±15 V
SFDR
Spurious-free dynamic range,
differential input, differential output, f
= 250 kHz
VO= 2 VPP
VO = 4 VPP
IMD3
Third intermodulation distortion
OIP3
Third-order intercept
f = 250 kHz
f = 1 MHz
f = 250 kHz
f = 1 MHz
f = 250 kHz
–101
–87
–100
–87
–102
f = 1 MHz
–88
f = 250 kHz
–94
f = 1 MHz
–79
f = 250 kHz
–95
f = 1 MHz
–80
VCC = ±2.5
103
VCC = ±5
106
VCC = ±15
108
VCC = ±5
98
VCC = ±15
100
VI(PP) = 4 V, F1 = 3 MHz, F2 = 3.5 MHz
dBc
dBc
–53
dBc
41.5
dB
NOISE PERFORMANCE
Vn
Input voltage noise
f = 10 kHz
1.25
nV/√Hz
In
Input current noise
f = 10 kHz
1.7
pA/√Hz
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.5 Electrical Characteristics: THS413xD, THS413xDGK (continued)
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = +25°C
71
78
TA = full range
69
MAX
UNIT
DC PERFORMANCE
Open-loop gain
VOS
Input offset voltage
TA = +25°C
±0.2
TA = full range(1)
IOS
2
3
Common-mode input offset voltage,
referred to VOCM
IIB
dB
0.2
5.5
Input offset voltage drift
TA = full range(1)
2
Input bias current
TA = full range(1)
5
15.4
range(1)
100
500
Input offset current
TA = full
Input offset current drift
mV
mV
µV/°C
µA
nA
1
nA/°C
95
dB
–3.77 to
–4 to 4.5
4.3
V
INPUT CHARACTERISTICS
CMRR
Common-mode rejection ratio
VICR
Common-mode input voltage range
RI_CM
Common-mode input resistance
RI_DIFF
Differential input resistance
CI_CM
Common-mode input capacitance,
closed loop
CI_DIFF
Differential input capacitance, closed
loop
TA = full range(1)
80
Measured into each input terminal
215
MΩ
10
kΩ
1.4
Measured into each input terminal
pF
2.5
OUTPUT CHARACTERISTICS
ro
Output resistance
Open loop
VCC = 5 V, RL = 1kΩ
Output voltage swing
VCC = ±5 V, RL = 1kΩ
VCC = ±15 V, RL = 1kΩ
VCC = 5 V, RL = 7 Ω
IO
Output current
VCC = ±5 V, RL = 7 Ω
VCC = ±15 V, RL = 7 Ω
41
TA = +25°C
1.2 to 3.8 0.9 to 4.1
TA = full range(1)
1.3 to 3.7
TA = +25°C
±3.7
TA = full range(1)
±3.6
TA = +25°C
TA = full
±11.5
range(1)
25
TA = full range
20
TA = +25°C
30
range(1)
V
±12.4
45
55
mA
28
TA = +25°C
TA = full
±4
±11.2
TA = +25°C
TA = full
Ω
65
range(1)
85
60
POWER SUPPLY
ICC
Quiescent current
VCC = ±5 V
VCC = ±15 V
ICC(SD)
Quiescent current (shutdown)
(THS4130 only)(3)
PSRR
Power-supply rejection ratio (dc)
(1)
(2)
8
PD = –5 V
TA = +25°C
10.4
TA = full range(1)
16
TA = +25°C
13
TA = +25°C
0.86
TA = full
15
range(1)
1.4
1.5
TA = +25°C
73
TA = full range(1)
70
98
mA
mA
dB
The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
Slew rate is measured from an output level range of 25% to 75%.
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(3)
SLOS318K – MAY 2000 – REVISED AUGUST 2022
For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section.
7.6 Electrical Characteristics: THS413xDGN
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Small-signal bandwidth (–3 dB),
single-ended input, differential
output, VI = 63 mVPP
BW
Small-signal bandwidth (–3 dB),
single-ended input, differential
output, VI = 63 mVPP
SR
ts
Slew
rate(2)
VCC = 5
Gain = 1, Rf = 390 Ω
125
VCC = ±5
Gain = 1, Rf = 390 Ω
135
VCC = ±15
Gain = 1, Rf = 390 Ω
150
VCC = 5
Gain = 2, Rf = 750 Ω
80
VCC = ±5
Gain = 2, Rf = 750 Ω
85
VCC = ±15
Gain = 2, Rf = 750 Ω
90
Gain = 1
52
Settling time to 0.1%
Step voltage = 2 V, gain = 1
78
Settling time to 0.01%
Step voltage = 2 V, gain = 1
213
MHz
V/µs
ns
DISTORTION PERFORMANCE
VCC = 5
Total harmonic distortion, differential
input, differential output, gain = 1, Rf VCC = ±5
= 390 Ω, RL = 800 Ω, VO= 2 VPP
VCC = ±15
THD
VCC = ±5
VO = 4 VPP
VCC = ±15
SFDR
Spurious-free dynamic range,
differential input, differential output,
gain = 1, Rf = 390 Ω,
RL = 800 Ω, f = 250 kHz
VO= 2 VPP
VO = 4 VPP
f = 250 kHz
–95
f = 1 MHz
–81
f = 250 kHz
–96
f = 1 MHz
–80
f = 250 kHz
–97
f = 1 MHz
–80
f = 250 kHz
–91
f = 1 MHz
–75
f = 250 kHz
–91
f = 1 MHz
–75
VCC = ±2.5
97
VCC = ±5
98
VCC = ±15
99
VCC = ±5
93
VCC = ±15
dBc
dB
95
Third intermodulation distortion
VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz
–53
dBc
Third-order intercept
VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz
41.5
dB
NOISE PERFORMANCE
Vn
Input voltage noise
f = 10 kHz
1.3
nV/√Hz
In
Input current noise
f = 10 kHz
1
pA/√Hz
DC PERFORMANCE
Open-loop gain
Input offset voltage
V(OS)
IIB
IOS
TA = +25°C
71
TA = full range
69
TA = +25°C
78
0.2
TA = full range
dB
2
3
Common-mode input offset voltage,
referred to VOCM
TA = +25°C
0.2
Input offset voltage drift
TA = full range
4.5
Input bias current
TA = full range
2
6
Input offset current
TA = full range
100
500
Offset drift
2
mV
3.5
µV/°C
µA
nA
nA/°C
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.6 Electrical Characteristics: THS413xDGN (continued)
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
CMRR
Common-mode rejection ratio
VICR
Common-mode input voltage range
RI
Input resistance
CI
Input capacitance, closed loop
ro
Output resistance
TA = full range
95
dB
–3.77 to
–4 to 4.5
4.3
80
V
Measured into each input terminal
34
MΩ
4
pF
Open loop
41
Ω
OUTPUT CHARACTERISTICS
VCC = 5 V
Output voltage swing
VCC = ±5 V
VCC = ±15 V
VCC = 5 V, RL = 7 Ω
IO
Output current
VCC = ±5 V, RL = 7 Ω
VCC = ±15 V, RL = 7 Ω
TA = +25°C
1.2 to 3.8 0.9 to 4.1
TA = full range
1.3 to 3.7
TA = +25°C
±3.7
TA = full range
±3.6
TA = +25°C
±10.5
TA = full range
±10.2
TA = +25°C
25
TA = full range
20
TA = +25°C
30
TA = full range
28
TA = +25°C
65
TA = full range
60
±4
V
±12.4
45
55
mA
85
POWER SUPPLY
VCC
Supply voltage range
ICC
Quiescent current
Single supply
Split supply
VCC = ±5 V
VCC = ±15 V
ICC(SD)
Quiescent current (shutdown)
(THS4130 only)(3)
PSRR
Power-supply rejection ratio (dc)
(1)
(2)
(3)
10
V = –5 V
5
30
±2.5
±15
TA = +25°C
12.3
TA = full range
15
16
TA = +25°C
14
TA = +25°C
0.86
TA = full range
1.4
1.5
TA = +25°C
73
TA = full range
70
98
V
mA
mA
dB
The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
Slew rate is measured from an output level range of 25% to 75%.
For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section.
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.7 Typical Characteristics: THS413xD, THS413xDGK
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise
noted)
3
25
2
20
1
0
Output (dB)
Output (dB)
15
10
5
0
-5
-10
G
G
G
G
=
=
=
=
10M
Frequency (Hz)
-2
-3
-4
-5
1, RF = 390
2, RF = 750
5, RF = 2 k
10, RF = 4 k
1M
-1
-6
RF = 390
RF = 620
-7
100M
-8
1G
1M
10M
Frequency (Hz)
VI = 63 mVPP
Figure 7-2. Small-Signal Frequency Response
2
1
0
Output (dB)
Output (dB)
-1
-2
-3
-4
-5
-6
-8
VCC = 5 V
VCC = 15 V
1M
10M
Frequency (Hz)
100M
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
CF = 0 pF
CF = 1 pF
1M
1G
10M
Frequency (Hz)
1G
Figure 7-4. Small-Signal Frequency Response
Figure 7-3. Small-Signal Frequency Response
1
Large Signal Transient Response (V)
Output (dB)
100M
VI = 63 mVPP
VI = 63 mVPP
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
1G
VI = 63 mVPP
Figure 7-1. Small-Signal Frequency Response
-7
100M
CL = 0 pF
CL = 10 pF
1M
0.5
0
-0.5
0.5
0
VOUT+
VOUTVIN+
VIN-
-0.5
-1
10M
Frequency (Hz)
100M
1G
0
0.1
0.2
0.3
Time (s)
0.4
0.5
0.6
.
VI = 63 mVPP
Figure 7-5. Small-Signal Frequency Response
Figure 7-6. Large-Signal Transient Response (Differential In/
Single Out)
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.7 Typical Characteristics: THS413xD, THS413xDGK (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise
noted)
CMRR - Common Mode Rejection Ratio (dB)
5
0
Output (dB)
-5
-10
-15
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-20
-25
1M
10M
Frequency (Hz)
100M
1G
-60
-70
-80
-90
-100
100k
1M
10M
100M
Frequency (Hz)
950
VCC = 15 V
VCC = 5 V
ICC - Supply Current (A)
ICC - Supply Current (mA)
-50
Figure 7-8. Common-Mode Rejection Ratio vs Frequency
Figure 7-7. Large-Signal Frequency Response
14
-40
RF = 1 kΩ
VI = 0.2 VRMS
15
-30
13
12
11
10
900
850
800
9
8
-40
-20
0
20
40
60
TA - Free-Air Temperature (C)
80
750
-40
100
-20
0
20
40
60
TA - Free-Air Temperature (C)
Figure 7-10. Supply Current vs Free-Air Temperature (Shutdown
State)
Figure 7-9. Supply Current vs Free-Air Temperature
2.04
IBIB+
-3
2.02
VO - Output Voltage (V)
IIB - Input Bias Current (A)
-2
-4
-5
-6
2
1.98
1.96
1.94
1.92
-7
1.9
-25
0
25
50
TA - Free-Air Temperature (C)
75
100
.
0
25
50
75
Time (ns)
100
125
150
RF = 510 Ω, CF= 1 pF, VCC= 5 V, VO = 4 VPP
Figure 7-11. Input Bias Current vs Free-Air Temperature
12
100
.
.
-8
-50
80
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Figure 7-12. Settling Time
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.7 Typical Characteristics: THS413xD, THS413xDGK (continued)
-30
2.5
VCC+ = +5 V
VCC- = -5 V
-40
2
VO - Output Voltage (V)
PSRR - Power Supply Rejection Ratio (dB)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise
noted)
-50
-60
-70
-80
-90
1.5
1
0.5
0
VOUT+
VOUT-
-0.5
-1
-1.5
-2
-100
10k
100k
1M
Frequency (Hz)
10M
-2.5
100M
0
RF = 330 Ω, RL = 400 Ω
THD - Total Harmonic Distortion (dBc)
120
Time (ns)
160
200
Figure 7-14. Large-Signal Transient Response
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-60
-70
-80
-90
-100
-110
-120
100k
1M
Frequency (Hz)
10M
VOUT = 2 VPP
VOUT = 2 VPP, Single-ended Input, Differential Output
Figure 7-15. Total Harmonic Distortion vs Frequency
-30
Figure 7-16. Second-Harmonic Distortion vs Frequency
-102
VCC = 5 V
VCC = 15 V
-40
HD2 - Second Harmonic Distortion (dBc)
HD2 - Second Harmonic Distortion (dBc)
80
VI_Peak = 2 V, CL = 10 pF, VCC = ±15 V
Figure 7-13. Power-Supply Rejection Ratio vs Frequency
(Differential Out)
-50
40
-50
-60
-70
-80
-90
-100
-110
-120
100k
1M
Frequency (Hz)
10M
VOUT = 4 VPP, Single-ended Input, Differential Output
Figure 7-17. Second-Harmonic Distortion vs Frequency
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
0
1
2
3
4
5
VOUT - Output Voltage (V)
6
7
f = 250 kHz, Single-ended Input, Differential Output
Figure 7-18. Second-Harmonic Distortion vs Output Voltage
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.7 Typical Characteristics: THS413xD, THS413xDGK (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise
noted)
-30
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-102
HD3 - Third Harmonic Distortion (dB)
HD2 - Second Harmonic Distortion (dBc)
-98
-100
-104
-106
-108
-110
-112
-114
-116
1
2
3
4
5
VOUT - Output Voltage (V)
6
-50
-60
-70
-80
-90
-100
-110
100k
-118
0
VCC = 5 V
VCC = 15 V
-40
7
Figure 7-20. Third-Harmonic Distortion vs Frequency
Figure 7-19. Second-Harmonic Distortion vs Output Voltage
-60
HD3 - Second Harmonic Distortion (dBc)
HD3 - Third Harmonic Distortion (dB)
-85
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-50
-70
-80
-90
-100
-110
-120
-130
100k
10M
VOUT = 4 VPP, Single-ended Input, Differential Output
f = 500 kHz, Single-ended Input, Differential Output
-40
1M
Frequency (Hz)
1M
Frequency (Hz)
-90
-95
-100
-105
-110
-115
-120
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-125
-130
10M
0
VOUT = 2 VPP, Single-ended Input, Differential Output
Figure 7-21. Third-Harmonic Distortion vs Frequency
1
2
3
4
5
VOUT - Output Voltage (V)
6
7
f = 500 kHz, Single-ended Input, Differential Output
Figure 7-22. Third-Harmonic Distortion vs Output Voltage
Vn - Voltage Noise (nV/Hz)
10
1
10
100
14
10k
100k
.
f = 250 kHz, Single-ended Input, Differential Output
Figure 7-23. Third-Harmonic Distortion vs Output Voltage
1k
Frequency (Hz)
Figure 7-24. Voltage Noise vs Frequency
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.7 Typical Characteristics: THS413xD, THS413xDGK (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω (unless otherwise
noted)
400
In (pA/Hz)
VOS - Input Offset Voltage - V
10
1
10
100
1k
Frequency (Hz)
10k
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
350
300
250
200
150
100
50
0
-12
100k
-9
-6
-3
0
3
6
VOCM - Common-Mode Output Voltage
.
12
RF = 1 kΩ
Figure 7-25. Current Noise vs Frequency
Figure 7-26. Input Offset Voltage vs Common-Mode Output
Voltage
100
VCC = 5 V
VCC = 15 V
10
5
0
-5
Output Impedance ()
15
VO - Output Voltage (V)
9
10
1
-10
-15
100
1k
10k
100k
RL ()
0.1
100k
RF = 1 kΩ, G = 2 V/V
1M
10M
Frequency (Hz)
100M
1G
.
Figure 7-27. Output Voltage vs Differential Load Resistance
Figure 7-28. Output Impedance vs Frequency
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.8 Typical Characteristics: THS413xDGN
25
3
RL = 800 W,
VCC = ± 5 V,
VI = 63 mVPP
Gain = 10_Rf = 4 kW
20
1
Gain = 5_Rf = 2 kW
Rf = 620 W
0
Output − dB
Output −dB
15
Gain = 1,
RL = 800 W,
VCC = ± 5 V,
VI = 63 mVPP
2
10
Gain = 2_Rf = 750 W
5
−1
Rf = 390 W
−2
−3
−4
Gain = 1_Rf = 390 W
−5
0
−6
−5
−7
−10
100 k
1M
10 M
100 M
f − Frequency − Hz
−8
100 k
1G
Figure 7-29. Small-Signal Frequency Response
0
0
−1
VCC= 5
−2
−3
Gain = 1,
RL = 800 W,
Rf = 390 W,
VI = 63 mVPP
−8
100 k
1M
−8
−9
10 M
100 M
f − Frequency − Hz
−10
100 k
1G
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 7-32. Small-Signal Frequency Response (Various CF)
5
1
Gain = 1,
RL = 800 W,
VCC = ± 5 V,
VI = 63 mVPP,
Rf = 390 W
CL = 10 pF
Large Signal Transient Response − V
VO+
1
Output − dB
CF = 1 pF
−4
−7
Figure 7-31. Small-Signal Frequency Response (Various
Supplies)
−0
CL = 0 pF
−1
−2
−3
−4
−5
−6
−7
−8
100 k
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 7-33. Small-Signal Frequency Response (Various CL)
16
−3
−6
−5
2
−2
−5
−4
3
CF = 0 pF
1
Output − dB
Output − dB
2
−1
4
1G
3
VCC= ±15
1
−7
10 M
100 M
f − Frequency − Hz
Figure 7-30. Small-Signal Frequency Response
2
−6
1M
0.5
0
VO−
−0.5
0.5
0
VI (Diff)
−0.5
−1
0
0.1
0.2
0.4
0.3
t − Time − ms
0.5
0.6
Figure 7-34. Large-Signal Transient Response (Differential In/
Single Out)
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.8 Typical Characteristics: THS413xDGN (continued)
5
CMRR − Common Mode Rejection Ratio − dB
−50
VCC = ± 15 V
0
Output − dB
−5
−10
VCC = ± 5 V
−15
−20
Gain = 1
Rf = 390 W,
RL = 800 W,
CF = 0 pF,
VI = 0.2 VRMS
−25
100 k
VCC = 5 V
1M
10 M
100 M
Rf = 1 kW,
VCC = ± 5 V
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
100 k
1G
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 7-35. Large-Signal Frequency Response
100 M
Figure 7-36. Common-Mode Rejection Ratio vs Frequency
15
940
14.5
920
I CC − Supply Current − m A
I CC − Supply Current − mA
14
VCC = ± 15 V
13.5
13
12.5
VCC = ± 5 V
12
11.5
880
860
840
11
820
10.5
10
−40
−20
0
20
40
60
80
800
−50
−25
0
25
50
75
100
TA − Free-Air Temperature (Shutdown State) − °C
100
TA − Free-Air Temperature − °C
Figure 7-37. Supply Current vs Free-Air Temperature
Figure 7-38. Supply Current vs Free-Air Temperature (Shutdown
State)
2.4
2.04
2.35
2.02
VO − Output Voltage − V
IIB− Input Bias Current − m A
900
2.3
IIB+
2.25
2.2
2.15
2
RF = 510 W
CF = 1 pF,
VCC = 5 V
VO = 4 VPP
RL = 800 W
1.98
1.96
1.94
IIB−
2.1
2.05
−50
1.92
1.9
−25
0
25
50
75
TA − Free-Air Temperature − °C
100
0
Figure 7-39. Input Bias Current vs Free-Air Temperature
25
50
75
100
t − Time − ns
125
150
Figure 7-40. Settling Time
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SLOS318K – MAY 2000 – REVISED AUGUST 2022
7.8 Typical Characteristics: THS413xDGN (continued)
2.5
−50
Gain = 1,
Rf = 330 W,
RL = 400 W
1.5
−60
VCC = 5 V
−70
−80
VCC = −5 V
0
−5
−1
−2
VO−
100 k
1M
10 M
f − Frequency (Differential Out) − Hz
100 M
0
80
120
160
200
Figure 7-42. Large-Signal Transient Response
−30
VOUT = 2 VPP
−40
−50
−60
VCC = 5 V to ± 5 V
−70
−80
VCC = ± 15 V
−90
−60
VCC = 5 V
−70
−80
−90
−110
100 k
10M
1M
f − Frequency − Hz
10 M
Figure 7-44. Second-Harmonic Distortion vs Frequency
−30
−92
Single Ended Input
Differential Output
VCC = ± 5 V
−70
−80
VCC = ± 15 V
−90
−100
−96
10 M
Figure 7-45. Second-Harmonic Distortion vs Frequency
VCC = ± 5 V
VCC = 5 V
−98
VCC = ± 15 V
−100
−102
−104
−106
1M
f − Frequency − Hz
f = 250 KHz
RL = 800 W,
Rf = 390 W,
G=1
−94
Second Harmonic Distortion − dBc
VO = 4 VPP,
RL = 800 W,
Rf = 390 W,
G=1
−60
−110
100 k
−50
VCC = ±15V, ±5V
1M
f − Frequency − Hz
Figure 7-43. Total Harmonic Distortion vs Frequency
−50
Single Ended Input
Differential Output
−100
−100
100k
−40
VO = 2 VPP,
RL = 800 W,
Rf = 390 W,
G=1
−40
Second Harmonic Distortion − dBc
−30
40
t − Time − nS
−20
THD − Total Harmonic Distortion − dB
5
−2.5
Figure 7-41. Power-Supply Rejection Ratio vs Frequency
(Differential Out)
Second Harmonic Distortion − dBc
G = 1,
Rf = 390 W,
RL = 800 W,
CF = 0 pF,
CL = 10 pF,
VI_Peak = 2 V,
VCC = ± 15 V
TA = 25°C
1
−1.5
−90
−100
10 k
18
VO+
2
VO − Output Voltage − V
PSRR − Power Supply Rejection Ratio − dB
−40
Single Ended Input
Differential Output
0
1
2
3
4
5
VO − Output Voltage − V
6
7
Figure 7-46. Second-Harmonic Distortion vs Output Voltage
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7.8 Typical Characteristics: THS413xDGN (continued)
−88
−30
VO = 4 VPP
RL = 800 W,
Rf = 390 W,
G=1
VCC = ±15 V
−40
−92
−94
Third Harmonic Distortion − dBc
Second Harmonic Distortion − dBc
−90
VCC = ± 5 V
−96
−98
VCC = 5 V
−100
−102
f = 500 KHz
RL = 800 W,
Rf = 390 W,
G=1
Single Ended Input
Differential Output
−104
−106
0
1
2
3
4
5
VO − Output Voltage − V
6
−80
−90
−100
Single Ended Input
Differential Output
−90
Third Harmonic Distortion − dBc
Third Harmonic Distortion − dBc
VCC = ± 15 V
−70
1M
f − Frequency − Hz
10 M
−88
VO = 2 VPP,
RL = 800 W,
Rf = 390 W,
Gain = 1
−40
−50
Single Ended Input
Differential Output
−60
−70
VCC = ± 15 V
−80
VCC = ± 5 V
−90
VCC = 5 V
−100
−110
100 k
VCC = ± 15 V
−92
−94
VCC = ± 5 V
−96
VCC = 5 V
−98
f = 500 KHz
RL = 800 W,
Rf = 390 W,
G=1
−100
−102
−104
Single Ended Input
Differential Output
−106
1M
f − Frequency − Hz
0
10 M
1
2
3
4
5
6
7
VO − Output Voltage − V
Figure 7-49. Third-Harmonic Distortion vs Frequency
Figure 7-50. Third-Harmonic Distortion vs Output Voltage
10
−88
−92
VCC = ± 5 V
Vn − Voltage Noise − nV/ Hz
f = 250 KHz
RL = 800 W,
Rf = 390 W,
G=1
−90
Third Harmonic Distortion − dBc
−60
Figure 7-48. Third-Harmonic Distortion vs Frequency
−30
−94
−96
VCC = 5 V
−98
VCC = ± 15 V
−100
−102
−104
−106
VCC = ± 5 V
−110
100 k
7
Figure 7-47. Second-Harmonic Distortion vs Output Voltage
−50
Single Ended Input
Differential Output
1
0
1
2
3
4
5
VO − Output Voltage − V
6
7
10
100
1k
10 k
100 k
f − Frequency − Hz
Figure 7-51. Third-Harmonic Distortion vs Output Voltage
Figure 7-52. Voltage Noise vs Frequency
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7.8 Typical Characteristics: THS413xDGN (continued)
7E−12
1000
V(OS) − Input Offset Voltage − m V
I n − Current Noise − pA/ Hz
6E−12
5E−12
4E−12
3E−12
2E−12
1E−12
0
800
VCC =± 2.5 V
600
400
200
VCC =± 5 V
0
VCC =± 15 V
−200
−400
1
10
100
1k
f − Frequency − Hz
10 k
100 k
Figure 7-53. Current Noise vs Frequency
−600
−12
VCC =± 5 V
VCC = ± 15 V
VOUT+
VOUT+
VCC = ± 5 V
VOUT−
VCC = ± 5 V
zo − Output impedance − W
5
0
−5
−10
12
100
Rf = 1 k
G=2
10
−9
−6
−3
0
3
6
9
VOCM − Common-Mode Output Voltage − V
Figure 7-54. Input Offset Voltage vs Common-Mode Output
Voltage
15
VO − Output Voltage − V
Rf = 1 k,
RL = 800 W,
G=1
VOUT−
10
1
VCC = ± 15 V
−15
100
1000
10 k
RL − Differential Load Resistance − W
100 k
Figure 7-55. Output Voltage vs Differential Load Resistance
20
0.1
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 7-56. Output Impedance vs Frequency
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8 Detailed Description
8.1 Overview
8.1.1 Fully-Differential Amplifiers
The THS413x is a fully differential amplifier (FDA). Differential signal processing offers a number of performance
advantages in high-speed analog signal processing systems, including immunity to external common-mode
noise, suppression of even-order non-linearities, and increased dynamic range. FDAs not only serve as the
primary means of providing gain to a differential signal chain, but also provide a monolithic solution for
converting single-ended signals into differential signals allowing for easy, high-performance processing. For
more information on the basic theory of operation for FDAs, refer to the Fully Differential Amplifiers application
note.
8.2 Functional Block Diagram
VCC+
Output Buffer
VIN−
x1
VOUT+
C
VIN+
R
Vcm Error
Amplifier
+
_
C
x1
R
VOUT−
Output Buffer
VCC+
30 kW
VCC−
30 kW
VCC−
VOCM
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8.3 Feature Description
Figure 8-1 and Figure 8-2 depict the differences between the operation of the THS413x in two different modes.
FDAs can work with either differential or single-ended inputs.
RG
RG
RF
RF
VCC+
VCC+
VSource
–
–
VOUT+
+
VSource
VOCM
VOCM
–
VOUT-
+
VOUT+
–
VOUT-
+
VCC-
VCCRG
+
RG
RF
Figure 8-1. Amplifying Differential Input Signals
RF
Figure 8-2. Amplifying Single-ended Input Signals
8.4 Device Functional Modes
8.4.1 Power-Down Mode
The Power-Down mode is used when power saving is required. The power-down terminal (PD) found on the
THS4130 is an active low input. If left unconnected, an internal 250 kΩ resistor to VCC+ keeps the device turned
on. The threshold voltage for the power-down function is approximately 1.4 V above VCC–. This means that if
the PD terminal is 1.4 V above VCC–, then the device is active. If the PD terminal is less than 1.4 V above
VCC–, then the device is off. It is recommended to pull the terminal to VCC– to turn the device off. Figure 8-3
shows the simplified version of the power-down circuit. While in the Power-Down mode, the amplifier goes into a
high-impedance state. The amplifier's output impedance is typically greater than 1 MΩ in the Power-Down mode.
VCC
250 kΩ
To Internal Bias
Circuitry Control
PD
VCC
Figure 8-3. Simplified Power-Down Circuit
Similar to an opamp in an inverting configuration, the output impedance of an FDA is determined by its feedback
network configuration. In addition, the THS4130 has an internal 10 kΩ resistor at each output that is tied to the
VCM error amplifier (see Section 8.2). The differential output impedance is equal to [(2*RF + 2*RG) || 20 kΩ].
Figure 8-4 shows the closed loop output impedance of the THS4130 when in power-down.
22
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Differential Output Impedance ()
3500
3000
2500
2000
1500
1000
500
0
100k
1M
10M
Frequency (Hz)
100M
1G
VCC = ±5 V, G = 1 V/V, RF = 1kΩ, PD = VCC-
Figure 8-4. Output Impedance (in Power-Down) vs Frequency
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Output Common-Mode Voltage
The output common-mode voltage pin sets the dc output voltage of the THS413x. A voltage applied to the VOCM
pin from a low-impedance source can be used to directly set the output common-mode voltage. If the VOCM pin
is left floating, then it defaults to the mid-rail voltage, defined as:
(VCC+ ) + (VCC- )
(1)
2
To minimize common-mode noise, connect a 0.1-µF bypass capacitor to the VOCM pin. Output common-mode
voltage causes additional current to flow in the feedback resistor network. Since this current is supplied by the
output stage of the amplifier, this creates additional power dissipation. For commonly-used feedback resistance
values, this current is easily supplied by the amplifier. The additional internal power dissipation created by
this current may be significant in some applications and may dictate use of the MSOP PowerPAD package to
effectively control self-heating.
9.1.1.1 Resistor Matching
Resistor matching is important in FDAs to maintain good output balance. An ideal differential output signal
implies the two outputs of the FDA should be exactly equal in amplitude and shifted 180° in phase. Any
imbalance in amplitude or phase between the two output signals results in an undesirable common-mode signal
at the output. The output balance error is a measure of how well the outputs are balanced and is defined as the
ratio of the output common-mode voltage to the output differential signal.
Output Balance Error =
VOUT + − VOUT −
2
VOUT + − VOUT −
(2)
At low frequencies, resistor mismatch is the primary contributor to output balance errors. Additionally CMRR,
PSRR, and HD2 performance diminish if resistor mismatch occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to optimize performance. Table 9-1 provides the recommended resistor values to
use for a particular gain.
Table 9-1. Recommended Resistor Values
24
Gain (V/V)
RG (Ω)
RF (Ω)
1
390
390
2
374
750
5
402
2010
10
402
4020
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9.1.2 Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The THS413x has been internally compensated to maximize its bandwidth and slew rate performance.
When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the
device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in
Figure 9-1. A minimum value of 20 Ω should work well for most applications. For example, in 50-Ω transmission
systems, setting the series resistor value to 50 Ω both isolates any capacitance loading and provides the proper
line impedance matching at the source end.
RG
RF
VCC+
20 Ω
VOUT+
–
+
VOCM
–
+
VOUT20 Ω
VCCRG
RF
Figure 9-1. Driving a Capacitive Load
9.1.3 Data Converters
Driving data converters are one of the most popular applications for fully-differential amplifiers. Figure 9-2 shows
a typical configuration of an FDA attached to a differential analog-to-digital converter (ADC).
RG
RF
VDD
VIN
VCC+ = 5 V
RCB
AIN1
–
VOCM
+
CCB
AVDD
DVDD
THS1206
–
+
0.1 μF
AIN2
VCC- = -5 V
RG
VREF
AVSS
RCB
RF
Figure 9-2. Fully-Differential Amplifier Attached to a Differential ADC
FDAs can operate with a single supply. VOCM defaults to the mid-rail voltage, VCC/2. The differential output may
be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a
reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the amplifier using a
bypass capacitor to reduce broadband common-mode noise.
RG
RF
VDD
VIN
VCC = 5 V
RCB
AIN1
–
VOCM
+
CCB
0.1 μF
DVDD
THS1206
–
+
AVDD
AIN2
AVSS
VREF
RCB
RG
RF
Figure 9-3. Fully-Differential Amplifier Using a Single Supply
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9.1.4 Single-Supply Applications
For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed
the common-mode input voltage range. However, some single-supply applications may require the input voltage
to exceed the common-mode input voltage range. In such cases, the circuit configuration of Figure 9-4 is
suggested to bring the common-mode input voltage within the specifications of the amplifier.
VCC
RPU
RG
RF
VDD
VIN
VP
VCC = 5 V
RCB
VOUT
AVDD
AIN1
–
VOCM
+
CCB
THS1206
–
VCC
DVDD
+
0.1 μF
AIN2
RPU
VOUT
RG
AVSS
VREF
RCB
RF
Figure 9-4. Circuit With Improved Common-Mode Input Voltage
Equation 3 is used to calculate RPU:
RPU =
VP − VCC
VIN − VP R1 + VOUT − VP R1
G
F
(3)
9.2 Typical Application
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 9-5 shows a
method by which the noise may be filtered in the THS413x.
Figure 9-5 shows a typical application design example for the THS413x device in active low-pass filter topology
driving and ADC.
R2
C1
VCC
R4
+
−
VIN−
VIN+
R1
+
VIN+
R(t)
THS413x
−
+
C2
Vs
C3
R3
R1
VOCM
R3
THS1050
VIN−
VOCM
C3
VIC
R4
VCC−
+
C1
R2
Figure 9-5. Antialias Filtering
26
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9.2.1 Design Requirements
Table 9-2 shows example design parameters and values for the typical application design example in Figure 9-5.
Table 9-2. Design Parameters
DESIGN PARAMETERS
VALUE
Supply voltage
±2.5 V to ±15 V
Amplifier topology
Voltage feedback
Output control
DC coupled with output common
mode control capability
Filter requirement
500 kHz, Multiple feedback low
pass filter
9.2.2 Detailed Design Procedure
9.2.2.1 Active Antialias Filtering
Figure 9-5 shows a multiple-feedback (MFB) lowpass filter. The transfer function for this filter circuit is:
æ
ö
Rt
ö
ç
÷ æ
ç
÷
K
R2
÷´
2R4 + Rt
Hd (f ) = çç
÷ Where K =
2
÷ ç
j2pfR4RtC3 ÷
R1
f
1
jf
ö
ç -æ
÷ çç 1 +
÷
ç ç FSF ´ fc ÷ + Q FSF ´ fc + 1 ÷ è
2R4 + Rt ø
ø
è è
ø
1
FSF ´ fc =
and Q =
2p 2 ´ R2R3C1C2
2 ´ R2R3C1C2
R3C1 + R2C1 + KR3C1
(4)
(5)
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
2
FSF = Re + Im
2
and Q =
Re2 + Im
2
2Re
(6)
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
FSF ´ fc =
1
2pRC 2 ´ mn
and Q =
2 ´ mn
1 + m (1 + K )
(7)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
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9.2.3 Application Curve
5
0
Output (dB)
-5
-10
-15
-20
-25
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
1M
10M
Frequency (Hz)
100M
1G
Figure 9-6. Large-Signal Frequency Response
10 Power Supply Recommendations
The THS413x device was designed to operate on power supplies ranging from ±2.5 V to ±15 V (single-ended
supplies of 5 V to 30 V). TI recommends using a power-supply accuracy of 5% or better. When operated on
a board with high-speed digital signals, it is important to provide isolation between digital signal noise and the
analog input pins. The THS413x is connected to power supplies through pin 3 (VCC+) and pin 6 (VCC-). Each
supply pin should be decoupled to GND as close to the device as possible with a low-inductance, surface-mount
ceramic capacitor of approximately 10 nF. When vias are used to connect the bypass capacitors to a ground
plane the vias should be configured for minimal parasitic inductance. One method of reducing via inductance is
to use multiple vias. For broadband systems, two capacitors per supply pin are advised.
To avoid undesirable signal transients, the THS413x device should not be powered on with large inputs signals
present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs
when an ADC is used in the application.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high-frequency performance of the THS413x device, follow proper printed-circuit board
(PCB) high-frequency design techniques. The following is a general set of guidelines. In addition, a THS413x
device evaluation board is available to use as a guide for layout or for evaluating the device performance.
•
•
•
28
Ground planes—it is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
Proper power-supply decoupling—use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending
on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every
amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal.
As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The
designer should strive for distances of less than 0.1 inches between the device power terminals and the
ceramic capacitors.
Short trace runs or compact part placements—optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inputs of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
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11.2 Layout Example
RG–
RF+
VIN
RT–
VCC+
CBYP
RO+
–
+
FDA
VOCM
CL
–
+
PD
RO–
VCC+
CBYP
VCCRG+
RS+
RF–
RT+
Figure 11-1. Representative Schematic for Layout
RS+
VIN
RT+
IN–
IN+
3
VCC+
Vias to connect supply pins to
CBYP. Place CBYP capacitors on
the other side of the PCB as
close to the vias as possible.
RO+
4
OUT+
PD
7
VCC–
6
OUT–
CL
RF–
VOCM
RF+
2
8
Place the feedback resistors, RF±, gain
resistors, RG±, and the isolation
resistors, RO±, as close to the device
pins as possible to minimize parasitics
5
RO–
1
RG+
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
RG–
RT–
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
Figure 11-2. Layout Recommendations
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11.3 General PowerPAD Design Considerations
The THS413x is available in a thermally-enhanced DGN package, which is a member of the PowerPAD family of
packages. This package is constructed using a downset leadframe upon which the die is mounted (see Figure
11-3 a and Figure 11-3 b). This arrangement results in the lead frame being exposed as a thermal pad on the
underside of the package (see Figure 11-3 c). Because this thermal pad has direct thermal contact with the die,
excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the previously awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in PowerPAD Thermally-Enhanced Package. This document can be found on the TI website (www.ti.com) by
searching on the key word PowerPAD. The document can also be ordered through your local TI sales office.
Refer to SLMA002 when ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from VCC– to VCC+.
Typically, the thermal pad is connected to the ground plane because this plane tends to physically be the largest and is able to dissipate
the most amount of heat.
Figure 11-3. Views of Thermally-Enhanced DGN Package
30
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Design Guide for 2.3 nV/√Hz, Differential, Time Gain Control (TGC) DAC Reference
Design for Ultrasound design guide
• Texas Instruments, EVM User's Guide for High-Speed Fully-Differential Amplifier user's guide
• Texas Instruments, Fully Differential Amplifiers application note
• Texas Instruments, Maximizing Signal Chain Distortion Performance Using High Speed Amplifiers application
note
• Texas Instruments, PowerPAD Thermally-Enhanced Package application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, TI Precision Labs - Fully Differential Amplifiers video series
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
PowerPAD™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS4130CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4130C
Samples
THS4130CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4130C
Samples
THS4130CDGK
LIFEBUY
VSSOP
DGK
8
80
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
ATP
THS4130CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOB
Samples
THS4130CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOB
Samples
THS4130CDGNRG4
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOB
Samples
THS4130ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4130I
Samples
THS4130IDGK
LIFEBUY
VSSOP
DGK
8
80
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASO
THS4130IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASO
Samples
THS4130IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOC
Samples
THS4130IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOC
Samples
THS4130IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4130I
Samples
THS4131CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4131C
Samples
THS4131CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4131C
Samples
THS4131CDGK
LIFEBUY
VSSOP
DGK
8
80
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
ATQ
THS4131CDGKG4
LIFEBUY
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ATQ
THS4131CDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
ATQ
Samples
THS4131CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOD
Samples
THS4131CDGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOD
Samples
THS4131CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOD
Samples
THS4131CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4131C
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS4131ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4131I
Samples
THS4131IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4131I
Samples
THS4131IDGK
LIFEBUY
VSSOP
DGK
8
80
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASP
THS4131IDGKG4
LIFEBUY
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASP
THS4131IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASP
Samples
THS4131IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOE
Samples
THS4131IDGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOE
Samples
THS4131IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOE
Samples
THS4131IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4131I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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