D−8
DGN−8
THS4140
THS4141
DGK−8
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS
FEATURES
KEY APPLICATIONS
•
•
•
•
•
•
•
•
•
High Performance
– 160 MHz –3 dB Bandwidth (VCC = ±15 V)
– 450 V/µs Slew Rate
– –79 dB, Third Harmonic Distortion at
1 MHz
– 6.5 nV/√Hz Input-Referred Noise
Differential Input/Differential Output
– Balanced Outputs Reject Common-Mode
Noise
– Reduced Second Harmonic Distortion Due
to Differential Output
Wide Power-Supply Range
– VCC = 5-V Single Supply to ±15-V Dual
Supply
ICC(SD) = 880 µA in Shutdown Mode (THS4140)
Single-Ended to Differential Conversion
Differential ADC Driver
Differential Antialiasing
Differential Transmitter And Receiver
Output Level Shifter
THS4140
D, DGN, OR DGK PACKAGE
(TOP VIEW)
VIN−
VOCM
VCC+
VOUT+
1
8
2
7
3
6
4
5
VIN+
PD
VCC−
VOUT−
THS4141
D, DGN, OR DGK PACKAGE
(TOP VIEW)
VIN−
VOCM
VCC+
VOUT+
1
8
2
7
3
6
4
5
VIN+
NC
VCC−
VOUT−
HIGH-SPEED DIFFERENTIAL I/O FAMILY
DEVICE
NUMBER OF
CHANNELS
THS4140
1
X
THS4141
1
−
SHUTDOWN
DESCRIPTION
The THS414x is one in a family of fully differential input/differential output devices fabricated using Texas
Instruments' state-of-the-art BiComI complementary bipolar process.
The THS414x is made of a true, fully differential signal path from input to output. This design leads to an
excellent common-mode noise rejection and improved total harmonic distortion.
RELATED DEVICES
DEVICE
DESCRIPTION
THS412x
100 MHz, 43 V/µs, 3.7 nV/√Hz
THS413x
150 MHz, 51 V/µs, 1.3 nV/√Hz
THS415x
150 MHz, 650 V/µs, 7.6 nV/√Hz
TOTAL HARMONIC DISTORTION vs FREQUENCY
−30
VDD
5V
VIN
VOCM
+
−
AIN
−
+
AIN
−5 V
AVDD
AVSS
DVDD
Vref
DIGITAL
OUTPUT
THD − Total Harmonic Distortion − dB
Typical A/D Application Circuit
−40
−50
−60
−70
−80
VCC = 5 V to ± 15 V
−90
−100
100 k
1M
10 M
100 M
f − Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2006, Texas Instruments Incorporated
THS4140
THS4141
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. AVAILABLE OPTIONS
PACKAGED DEVICES (1)
TA
0°C to 70°C
–40°C to 85°C
(1)
MSOP PowerPAD™
SMALL OUTLINE
(D)
EVALUATION
MODULES
MSOP
(DGN)
SYMBOL
(DGK)
SYMBOL
THS4140CD
THS4140CDGN
AOF
THS4140CDGK
ATR
THS4140EVM
THS4141CD
THS4141CDGN
AOI
THS4141CDGK
ATS
THS4141EVM
THS4140ID
THS4140IDGN
AOG
THS4140IDGK
ASQ
–
THS4141ID
THS4141IDGN
AOK
THS4141IDGK
ASR
–
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage
VCC– to VCC+
VI
Input voltage
IO
Output current (2)
VID
Differential input voltage
±16.5 V
±VCC
150 mA
±6 V
Continuous total power dissipation
See Dissipation Rating Table
Maximum junction temperature (3)
TJ
150°C
Maximum junction temperature, continuous operation, long term
TA
Operating free-air temperature
Tstg
Storage temperature
reliability (4)
125°C
C suffix
0°C to 70°C
I suffix
–40°C to 85°C
–65°C to 150°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
ESD ratings
(1)
(2)
(3)
(4)
300°C
HBM
2500 V
CDM
1500 V
MM
200 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS414x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
PowerPad™ thermally enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATING TABLE
(1)
(2)
2
POWER RATING (2)
PACKAGE
θJA (1) (°C/W)
θJC (°C/W)
TA = 25°C
TA = 85°C
D
97.5
38.3
1.02 W
410 mW
DGN
58.4
4.7
1.71 W
685 mW
DGK
260
54.2
385 mW
154 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage, VCC– to VCC+
TA
Operating free-air temperature
Dual supply
TYP
MAX
±2.5
±15
Single supply
5
30
C suffix
0
70
–40
85
I suffix
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
BW
Small signal bandwidth (–3 dB)
SR
Slew
rate (2)
Settling time to 0.1%
VCC = ±5,
Gain = 1, Rf = 390 Ω
150
MHz
VCC = ±15,
Gain = 1, Rf = 390 Ω
160
MHz
450
V/µs
Gain = 1
96
Differential step voltage = 2 VPP,
Gain = 1
304
Second harmonic distortion, differential
in/differential out
1 MHz
VO = 2 VPP
–85
8 MHz
VO = 2 VPP
–65
Third harmonic distortion, differential in/differential
out
1 MHz
VO = 2 VPP
–79
8 MHz
VO = 2 VPP
–55.5
VCC = 5
f = 1 MHz
–78
VCC = ±5
f = 1 MHz
–78
VCC = ±15
f = 1 MHz
–79
ts
Settling time to 0.01%
ns
DISTORTION PERFORMANCE
THD
Total harmonic distortion
Differential input, differential output
Gain = 1, Rf = 390 Ω, RL = 800 Ω,
VO = 2 VPP
Spurious free dynamic range (SFDR)
dB
dB
dB
–79
dB
Intermodulation distortion
5 MHz
–103
dBc
Third-order intercept
20 MHz
37
dB
NOISE PERFORMANCE
Vn
Input voltage noise
f = 10 kHz
6.5
nV/√Hz
In
Input current noise
f = 10 kHz
1.25
pA/√Hz
DC PERFORMANCE
Open loop gain
Input offset voltage, differential
VOS
Input offset voltage, referred to VOCM
Offset drift
IIB
Input bias curent
IOS
Input offset current
TA = 25°C
63
TA = full range
60
TA = 25°C
1
TA = full range
TA = 25°C
TA = full range
TA = full range
Offset drift
(1)
(2)
67
dB
7
8.5
0.5
mV
8
7
µV/°C
5.1
15
µA
0.1
1
µA
0.3
nA/°C
The full range temperature is 0°C to 70°C for the C suffix, and –40°C to 85°C for the I suffix.
Slew rate is measured from an output level range of 25% to 75%.
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ELECTRICAL CHARACTERISTICS (continued)
VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
CMRR
Common-mode rejection ratio
VICR
Common-mode input voltage range
RI
Input resistance, closed loop
CI
Input capacitance
ro
Output resistance
TA = full range
75
84
dB
–3.77 to
4.3
–4 to 4.5
V
Measured into each input terminal
14.4
MΩ
3.9
pF
43
Ω
Open loop
OUTPUT CHARACTERISTICS
VCC = 5 V
Output voltage swing
VCC = ±5 V
VCC = ±15 V
VCC = 5 V
IO
Output current, RL = 7Ω
VCC = ±5 V
VCC = ±15 V
TA = 25°C
1.2 to 3.8
TA = full range
1.3 to 3.7
TA = 25°C
±3.7
TA = full range
±3.6
TA = 25°C
±12
TA = full range
±11
TA = 25°C
35
TA = full range
25
TA = 25°C
45
TA = full range
35
TA = 25°C
65
TA = full range
50
0.9 to 4.1
±3.9
V
±12.9
45
60
mA
85
POWER SUPPLY
VCC
Supply voltage range
ICC
Quiescent current
Single supply
Split supply
VCC = ±5 V
VCC = ±15 V
ICC(SD)
Quiescent current (shutdown)
(THS4140) (3)
PSRR
Power supply rejection ratio (dc)
(3)
4
4
33
±2
±16.5
TA = 25°C
13.2
TA = full range
16
18
TA = 25°C
V
mA
15
TA = 25°C
0.88
TA = full range
1.2
1.4
TA = 25°C
70
TA = full range
65
90
mA
dB
For detailed information on the behavior of the power-down circuit, see the power-down mode description in the Principles of Operation
section of this data sheet.
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
PSRR
Power supply rejection ratio
vs Frequency (differential out)
1
Small signal frequency response
2
Large signal frequency response
CMMR
Common-mode rejection ratio
3
vs Frequency
4
Small signal frequency response
SR
5
Slew rate
6
Second harmonic distortion
Third harmonic distortion
vs Frequency
7
vs Output voltage
8, 9
vs Frequency
10, 11
vs Output voltage
12, 13
Settling time
Vn
14
Voltage noise
vs Frequency
15
Single-ended output voltage
vs Common-mode output voltage
16
VO
Output voltage
vs Differential load resistance
17
zo
Output impedance
vs Frequency
18
Input bias current
vs Supply voltage
19
Output current range
vs Supply voltage
20
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY (DIFFERENTIAL OUT)
SMALL SIGNAL FREQUENCY RESPONSE
45
VCC = 5 V to ±15 V
40
35
−30
30
Rf = 24 kΩ
RL = 800 Ω,
VCC = ±5 V,
VI = 45 mVPP
25
−40
Output − dB
PSRR − Power Supply Rejection Ratio − dB
−20
VCC−
−50
−60
20
15
10
Rf = 1.2 kΩ
5
Rf = 470 Ω
0
VCC
−5
−70
Rf = 2.4 kΩ
Rf = 240 Ω
−10
−15
−80
100 k
1M
10 M
f − Frequency (Differential Out) − Hz
100 M
−20
100 k
Figure 1.
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 2.
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TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
LARGE SIGNAL FREQUENCY RESPONSE
−40
CMRR − Common-Mode Rejection Ratio − dB
5
VI = 0.4 VPP
0
Output − dB
−5
VI = 0.126 VPP
−10
−15
VI = 40 m VPP
−20
−25
−30
Rf = 330 Ω,
RL = 800 Ω,
VCC = ±5 V,
G=1
−35
100 k
1M
10 M
100 M
f − Frequency − Hz
VI = 0.8 mVPP
−50
VCC = 5 V
−60
VCC = ±15 V
−70
−80
VCC = ±5 V
−90
−100
1M
1G
10 M
100 M
f − Frequency − Hz
Figure 3.
Figure 4.
SMALL SIGNAL FREQUENCY RESPONSE
SLEW RATE
1.25
1
VCC = 5 V
1
VI Peak = 1,
TA = 25 °C
0.75
VO − Output Voltage − V
Output − dB
0
VCC = ±5 V
VCC = ±15 V
−1
−2
Rf = 390 Ω,
RL = 800 Ω,
VI = 45 mV RMS
G=1
−3
100 k
1M
VCC = ±15 V
0.5
0.25
0
VCC = 5 V
−0.25
−0.5
G = 1,
Rf = 330 Ω,
RL = 800 Ω,
CF = 1 pF,
CI = 0
−0.75
−1
10 M
100 M
1G
−1.25
116
f − Frequency − Hz
Figure 5.
6
1G
118
120
122
124
t − Time − ns
Figure 6.
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128
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
SECOND HARMONIC DISTORTION
vs
FREQUENCY
SECOND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−80
−50
VO = 4 VPP,
RL = 800 Ω,
Rf = 330 Ω,
G=1
−60
VCC = ±5 V
Second Harmonic Distortion − dBc
Second Harmonic Distortion − dBc
−55
−65
VCC = ±15 V
−70
−75
−80
−85
−90
f = 1 MHz,
RL = 800 Ω,
Rf = 330 Ω,
G=1
−82
VCC = ±15 V
−84
VCC = ±5 V
−86
VCC = 5 V
−88
−90
−95
−92
−100
100 k
1M
10 M
1
100 M
2
3
4
VO − Output Voltage − V
f − Frequency − Hz
Figure 7.
Figure 8.
SECOND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
THIRD HARMONIC DISTORTION
vs
FREQUENCY
6
−30
−57
−58
−59
VCC = ±15 V
−60
−61
−62
VCC = ±5 V
−63
f = 16 MHz,
RL = 800 Ω,
Rf = 330 Ω,
G=1
−64
−65
2
3
4
VO − Output Voltage − V
5
−50
−60
−70
VCC = 5 V
VCC = ±15 V
−80
−90
−100
−66
1
VO = 2 VPP,
RL = 800 Ω,
Rf = 330 Ω,
G=1
−40
VCC = 5 V
Third Harmonic Distortion − dBc
Second Harmonic Distortion − dBc
5
6
−110
100 k
VCC = ±5 V
1M
10 M
100 M
f − Frequency − Hz
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
THIRD HARMONIC DISTORTION
vs
FREQUENCY
THIRD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−30
−50
−60
f = 1 MHz
RL = 800 Ω,
Rf = 330 Ω,
G=1
−73
Third Harmonic Distortion − dBc
Third Harmonic Distortion − dBc
−40
−71
VO = 4 VPP,
RL = 800 Ω,
Rf = 330 Ω,
G=1
VCC = ±5 V
−70
VCC = ±15 V
−80
−90
−100
−75
VCC = ±5 V
−77
−79
−81
VCC = 5 V
−83
VCC = ±15 V
−85
−87
−110
100 k
1M
10 M
−89
100 M
1
1.5
f − Frequency − Hz
2
2.5
Figure 11.
5
2.20
−49
−51
VCC = ±15 V
−53
Rf = 510 Ω,
CF = 1 pF,
VO(PP) = 4 V,
VCC = 5 V,
Small Scale
2.30
VO − Output Voltage − V
Third Harmonic Distortion − dBc
VCC = ±5 V
f = 16 MHz
RL = 800 Ω,
Rf = 330 Ω,
G=1
−55
VCC = 5 V
2.10
2
19 ns to 1%
96 ns to 0.1%
304 ns to 0.01%
1.90
1.80
−57
1.70
−59
1.60
1.50
2
3
4
VO − Output Voltage − V
5
6
0
50
100
150
t − Time − ns
Figure 13.
8
4.5
2.40
−47
−61
1
4
SETTLING TIME
−41
−45
3.5
Figure 12.
THIRD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−43
3
VO − Output Voltage − V
Figure 14.
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250
300
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TYPICAL CHARACTERISTICS (continued)
VOLTAGE NOISE
vs
FREQUENCY
SINGLE-ENDED INPUT OFFSET VOLTAGE
vs
COMMON-MODE OUTPUT VOLTAGE
VOS − Single-Ended Input Offset Voltage − mV
Vn − Voltage Noise − nV/ Hz
100
10
1
10
100
1K
10 K
f − Frequency − Hz
VCC = ±5 V
VCC = ±2.5 V
2
1.5
VCC = ±15 V
1
0.5
−9
−6
−3
0
3
6
9
12
VOCM − Common-Mode Output Voltage − V
Figure 16.
OUTPUT VOLTAGE
vs
DIFFERENTIAL LOAD RESISTANCE
OUTPUT IMPEDANCE
vs
FREQUENCY
100
VCC = ±15 V
VCC = ±5 V
VOUT+
VOUT+
Output Impedance − Ω
VO − Output Voltage − V
2.5
Figure 15.
Rf = 1 kΩ
G=2
5
Rf = 1 kΩ,
RL = 800 Ω,
G=1
0
−12
100 K
15
10
3
VCC = ±5 V
0
VOUT−
−5
VCC = − ±5 V
10
1
0.1
VVOUT−
OUT−
−10
VCC = − ±15 V
−15
100
1k
10 k
RL − Differential Load Resistance − Ω
100 k
0.01
100 k
Figure 17.
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
INPUT BIAS CURRENT
vs
SUPPLY VOLTAGE
OUTPUT CURRENT RANGE
vs
SUPPLY VOLTAGE
90
6.50
I O − Output Current Range − mA
I IB − Input Bias Current − µ A
80
TA = −40°C
6
5.50
5
TA = 85°C
TA = 25°C
4.50
4
3.50
TA = −40°C
TA = 25°C
70
60
TA = 85°C
50
40
30
20
10
3
1
3
11
7
9
VCC − Supply Voltage − ±V
5
13
15
0
1
Figure 19.
10
2
3
4
5 6 7 8 9 10 11 12 13 14 15
VCC − Supply Voltage − ±V
Figure 20.
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APPLICATION INFORMATION
RESISTOR MATCHING
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion
will diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it will be set to the midrail
voltage internally defined as:
ǒVCC)Ǔ ) ǒVCC–Ǔ
2
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM
pin as a bypass capacitor. Figure 21 shows the simplified diagram of the THS414x.
VCC+
Output Buffer
VIN-
x1
VOUT+
C
VIN+
R
Vcm Error
Amplifier
+
_
C
x1
R
VOUT-
Output Buffer
VCC+
30 kΩ
VCC-
30 kΩ
VCCVOCM
Figure 21. THS414x Simplified Diagram
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APPLICATION INFORMATION (continued)
DATA CONVERTERS
Data converters are one of the most popular applications for the fully differential amplifiers. Figure 22 shows a
typical configuration of a fully differential amplifier attached to a differential ADC.
VDD
VCC
5V
VIN
+
-
AIN1
-
+
AIN2
VOCM
0.1 µF
AVDD
DVDD
AVSS
Vref
-5 V
VCC-
Figure 22. Fully Differential Amplifier Attached to a Differential ADC
Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the
circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM
of the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to
the input terminal of the amplifier should not exceed the common-mode input voltage range.
VDD
VCC
5V
VIN
+
-
AIN1
-
+
AIN2
VOCM
0.1 µF
AVDD
DVDD
AVSS
Vref
Figure 23. Fully Differential Amplifier Using a Single Supply
Some single supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the
specifications of the amplifier.
VCC
Rg
VIN
VDD
Rf
RPU
VP
5V
VOUT
+
-
AIN
-
+
AIN
VOCM
0.1 µF
Rg
VCC
VOUT
RPU
VCC
AVDD
DVDD
AVSS
Vref
Rf
Figure 24. Circuit With Improved Common-Mode Input Voltage
12
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
APPLICATION INFORMATION (continued)
The following equation is used to calculate RPU:
V –V
P
CC
R
+
PU
1
1
ǒVIN – V PǓ RG ) V OUT – V P RF
ǒ
Ǔ
(1)
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS414x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 25. A minimum value of 20 Ω should work well for most applications. For
example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
390 Ω
20 Ω
Output
390 Ω
THS414x
20 Ω
390 Ω
Output
390 Ω
Figure 25. Driving a Capacitive Load
ACTIVE ANTIALIAS FILTERING
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high frequency noise with the frequency of operation. Figure 26 presents a
method by which the noise may be filtered in the THS414x.
R2
C1
VCC
R4
+
R1
-
VIN-
VIN+
R1
+
VIN+
R(t)
THS414x
+
C2
Vs
C3
R3
VOCM
R3
THS1050
VINVOCM
C3
VIC
R4
VCC-
+
C1
R2
Figure 26. Antialias Filtering
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APPLICATION INFORMATION (continued)
The transfer function for this filter circuit is:
ȡ
ȣ ȡ
Rt
ȣ
2R4
) Rt
K
ȧ
H (f) + ȧ
xȧ
d
ȧ f 2 1 jf
ȧ 1 ) j2πfR4RtC3ȧ
ǒ
Ǔ
2R4 ) Rt Ȥ
Ȣ– FSF x fc ) Q FSF x fc ) 1Ȥ Ȣ
Ǹ2 x R2R3C1C2
1
FSF x fc +
and Q +
R3C1 ) R2C1 ) KR3C1
2π Ǹ2 x R2R3C1C2
Where K + R2
R1
(2)
(3)
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency-scaling factor, and Q is the
quality factor.
FSF +
ǸRe
2
) |Im|
2
and Q +
ǸRe
2
) |Im|
2
2Re
(4)
Where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR,
C1 = C, and C2 = nC results in:
Ǹ2 x mn
1
FSF x fc +
and Q +
Ǹ
1
)
m(1 ) K)
2πRC 2 x mn
(5)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
PRINCIPLES OF OPERATION
THEORY OF OPERATION
The THS414x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully differential amplifiers are differential in/differential out.
Differential Amplifier
Rf
R(g)
THS414x
Fully differential Amplifier
VCC+
_
_
VINVIN+
+
+
R(g)
Rf
VO+
+
_
VO-
VOCM
VCC-
Figure 27. Differential Amplifier Versus a Fully Differential Amplifier
To understand the THS414x fully differential amplifiers, the definition for the pinouts of the amplifier are
provided.
Input voltage definition
V
ID
Output voltage definition
V
Transfer function
V
+
ǒVI)Ǔ – ǒV I–Ǔ
ǒVO)Ǔ – ǒVO–Ǔ
OD
+
OD
+ V
Output common mode voltage V
OC
V
ID
x A
+ V
IC
V
ǒVI)Ǔ
+
)
ǒVI–Ǔ
2
OC
+
(6)
ǒVO)Ǔ ) ǒVO–Ǔ
2
(7)
ǒfǓ
(8)
OCM
(9)
Differential Structure Rejects
Coupled Noise at the Input
Differential Structure Rejects
Coupled Noise at the Output
VCC+
VINVIN+
Differential Structure Rejects
Coupled Noise at the Power Supply
_
+
+
_
VO+
VO-
VOCM
VCC-
Figure 28. Definition of the Fully Differential Amplifier
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PRINCIPLES OF OPERATION (continued)
The following schematics depict the differences between the operation of the THS414x, fully differential
amplifier, in two different modes. Fully differential amplifiers can work with differential input or can be
implemented as single in/differential out.
Rf
VIN-
R(g)
VCC+
- +
Vs
VO+
+-
VIN+
VOVOCM
R(g)
Note: For proper operation, maintain
symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g)
⇒ A = Rf/R(g)
VCCRf
Figure 29. Amplifying Differential Signals
Rf
VIN-
R(g)
VCC+
RECOMMENDED RESISTOR VALUES
- +
+-
VIN+
Vs
VO+
VOVOCM
R(g)
GAIN
R(g) Ω
Rf Ω
1
2
5
10
390
374
402
402
390
750
2010
4020
VCCRf
Figure 30. Single In With Differential Out
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
V + 1 V
O
2 I
(10)
The second output is equal and opposite in sign:
V + –1 V
O
2 I
(11)
Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it will not be practical to feed a 2-VPP signal into the
targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP
signals with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer
has been able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential
amplifier. The final result indicates twice as much dynamic range. Figure 31 illustrates the increase in dynamic
range. The gain factor should be considered in this scenario. The THS414x fully differential amplifier offers an
improved CMRR and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion is
improved. Second harmonics tend to cancel because of the symmetrical output.
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PRINCIPLES OF OPERATION (continued)
a
VOD= 1-0 = 1
VCC+
+1
_
VINVIN+
+
+
_
VO+
0
VO-
+1
0
VOCM
VOD = 0-1 = -1
VCC-
b
Figure 31. Fully Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully differential amplifier is
selected by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to
implement the differential amplifier as an instrumentation amplifier. This configuration improves the input
impedance of the fully differential amplifier. Figure 32 depicts the general format of instrumentation amplifiers.
The general transfer function for this circuit is:
V
R
OD
f 1 ) 2R2
+
V
–V
R
R1
IN1
IN2
(g)
ǒ
Ǔ
(12)
THS4012
VIN1
R(g)
+
_
Rf
R2
_
R1
THS414x
+
R2
_
VIN2
+
THS4012
R(g)
Rf
Figure 32. Instrumentation Amplifier
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
PRINCIPLES OF OPERATION (continued)
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high frequency performance of the THS414x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS414x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
• Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this
distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer
should strive for distances of less than 0.1 inches (2,54 mm) between the device power terminals and the
ceramic capacitors.
• Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
• Short trace runs/compact part placements—Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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PRINCIPLES OF OPERATION (continued)
POWER-DOWN MODE
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS414x is an active low terminal. If it is left as a no-connect terminal, the device will always stay on due to an
internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC– = –5 V, then the device is on when PD reaches 3.6 V, (–5 V
+ 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal
to VCC– in order to turn the device off. Figure 33 shows the simplified version of the power-down circuit. While in
the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is
typically greater than 1 MΩ in the power-down state.
VCC
50 kΩ
To Internal Bias
Circuitry Control
PD
VCC-
Figure 33. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed-loop output impedance is shown in Figure 34.
OUTPUT IMPEDANCE (IN SHUTDOWN)
vs
FREQUENCY
Output Impedance - Ω
2200
VCC = ±5 V,
VI = 0.8 VPP RMS
PD = VCC-
1200
200
10 k
100 k
1M
10 M
f - Frequency - Hz
100 M
Figure 34.
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SLOS320F – MAY 2000 – REVISED JANUARY 2006
PRINCIPLES OF OPERATION (continued)
GENERAL PowerPAD DESIGN CONSIDERATIONS
The THS414x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 35(a) and Figure 35(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 35(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This document
can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 35. Views of Thermally Enhanced DGN Package
20
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
THS4140CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4140C
Samples
THS4140CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOF
Samples
THS4140ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4140I
Samples
THS4140IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASQ
Samples
THS4140IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOG
Samples
THS4140IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AOG
Samples
THS4141CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
4141C
Samples
THS4141CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOI
Samples
THS4141CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AOI
Samples
THS4141ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
4141I
Samples
THS4141IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASR
Samples
THS4141IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOK
Samples
THS4141IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AOK
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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