THS6204IPWPR

THS6204 ® TH S6 204 TH S6 ® 20 4 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 Dual-Port, Differential VDSL2 Line Driver Amplifiers FEATURES 1 • Low Power Consumption: – 21mA/Port Full Bias Mode – 16.2mA/Port Mid Bias Mode – 11.2mA/Port Low Bias Mode – Low-Power Shutdown Mode – IADJ Pin for Variable Bias • Low Noise: – 2.5nV/√Hz Voltage Noise – 17pA/√Hz Inverting Current Noise – 1.2pA/√Hz Noninverting Current Noise • Low MTPR Distortion: – 70dB with +20.5dBm G.993.2—Profile 8b • –89dBc HD3 (1MHz, 100Ω Differential) • High Output Current: > 424mA (25Ω Load) • Wide Output Swing: 43.2VPP (±12V, 100Ω Differential) • Wide Bandwidth: 150MHz (Gain = 10V/V) • Port-To-Port Separation of 90dB at 1MHz • PSRR of 50dB at 1MHz for Good Isolation • Wide Power-Supply Range: 10V to 28V 23 APPLICATIONS • • Ideal For VDSL2 Systems Backward-Compatible with ADSL/ADSL2+/ADSL2++ Systems DESCRIPTION The THS6204 is a dual-port, current-feedback architecture, differential line driver amplifier system ideal for xDSL systems. The device is targeted for use in VDSL2 (very-high-bit-rate digital subscriber line 2) line driver systems that enable greater than +20.5dBm line power up to 8.5MHz with good linearity supporting the G.993.2 VDSL2 8b profile. It is also fast enough to support central-office transmission of +14.5dBm line power up to 18.1MHz—Profile 30a. The unique architecture of the THS6204 allows quiescent current to be minimal while still achieving very high linearity. Differential distortion, under full bias conditions, is –89dBc at 1MHz and reduces to only –73dBc at 10MHz. Fixed multiple bias settings of the amplifiers allows for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an IADJ pin is available to further lower the bias currents. The wide output swing of 43.2VPP (100Ω differentially) with ±12V power supplies, coupled with over 425mA current drive (25Ω), allows for wide dynamic headroom, keeping distortion minimal. The THS6204 is available in a QFN-24 or a TSSOP-24 PowerPAD™ package. +12V CODEC VIN+ 9.1W 2kW 2.74kW 1:1.1 +20.5dBm Line Power 100W 1.33kW 2.74kW 2kW 9.1W CODEC VIN-12V Figure 1. Typical VDSL2 Line Driver Circuit Utilizing One Port of the THS6204 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT (2) PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING QFN-24 RHF 6204 TSSOP-24 PWP THS6204 THS6204IRHFT THS6204IRHFR THS6204IPWP THS6204IPWPR (1) (2) TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 3000 Rails, 60 Tape and Reel, 2000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The PowerPAD is electrically isolated from all other pins. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. THS6204 UNIT Supply voltage, VS– to VS+ 28 V Input voltage, VI ±VS Differential input voltage, VID Output current, IO—static dc (2) Continuous power dissipation Maximum junction temperature, any condition, TJ ±2 V ±100 mA See Dissipation Ratings table (3) +150 °C Maximum junction temperature, continuous operation, long-term reliability, TJ (4), QFN package +130 °C Maximum junction temperature, continuous operation, long-term reliability, TJ (4), TSSOP package +140 °C –65 to +150 °C +300 °C Human body model (HBM) 2000 V Charged device model (CDM) 500 V Machine model (MM) 100 V Storage temperature range, TSTG Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ESD ratings (1) (2) (3) (4) 2 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability. The THS6204 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally-enhanced package. Under high-frequency ac operation (> 10kHz), the short-term output current capability is much greater than the continuous dc output current rating. This short-term output current rating is about 8.5X the dc capability, or about ±850mA. The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 DISSIPATION RATINGS POWER RATING (3) (TJ = +130°C) (1) (2) (3) PACKAGE θJC (°C/W) θJA (°C/W) (1) (2) TA = +25°C TA = +85°C QFN-24 (RHF) 1.7 32 3.28W 1.4W HTSSOP-24 (PWP) 0.92 31 3.39W 1.45W This data was taken using a 4-layer, 3in × 3in (76.2mm × 76.2mm) test PCB with the PowerPAD soldered to the PCB. If the PowerPAD is not soldered to the PCB, θJA increases to +74°C/W for the RHF package and +62°C/W for the PWP package. For high-power dissipation applications, soldering the PowerPAD to the PCB is required. Failure to do so may result in reduced reliability and/or lifetime of the device. See TI technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package. Power rating is determined with a junction temperature of +130°C. This is the point where distortion starts to substantially increase and long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below +130°C for best performance and reliability. RECOMMENDED OPERATING CONDITIONS THS6204 MIN MAX UNIT Dual supply ±5 ±14 V Single supply 10 28 V Operating free-air temperature, TA –40 +85 °C Operating junction temperature, continuous operating temperature, TJ, QFN package –40 +130 °C Operating junction temperature, continuous operating temperature, TJ, TSSOP package –40 +140 °C Normal storage temperature, TSTG –40 +85 °C Supply voltage, VS– to VS+ PIN CONFIGURATIONS(1)(2)(3) QFN-24(4) RHF PACKAGE (TOP VIEW) D1 IN+ BIAS-2/ D1D2 BIAS-1/ D1D2 VS- VS+ D1 OUT VS- 24 23 22 21 20 HTSSOP-24(4) PWP PACKAGE (TOP VIEW) BIAS-1/D1D2 19 1 2 18 D2 IN- GND 3 17 D2 OUT 4 16 NC (4) 5 15 D3 OUT D3 IN+ 6 14 D3 IN- D1 OUT BIAS-2/D1D2 3 22 D1 IN- D1 IN+ 4 21 D2 IN- D2 IN+ 5 20 D2 OUT GND 6 19 NC (4) PowerPAD NC D3 IN+ 8 17 D3 OUT D4 IN+ 9 16 D3 IN- BIAS-2/D3D4 10 15 D4 IN- 12 (4) 18 BIAS-1/D3D4 11 14 D4 OUT D4 OUT 11 VS+ 10 VS- 9 BIAS-1/ D3D4 23 7 VS- 12 13 VS+ 13 BIAS-2/ D3D4 2 IADJ 7 8 D4 IN+ VS+ (4) IADJ PowerPAD 24 D1 IN- D2 IN+ NC 1 D4 IN- (1) The PowerPAD is electrically isolated from all other pins and can be connected to any potential voltage range from VS– to VS+. Typically, the PowerPAD is connected to the GND plane as this plane tends to physically be the largest and is able to dissipate the most amount of heat. (2) The THS6204 defaults to shutdown mode if no signal is present on the bias pins. (3) The GND pin range is from VS– to (VS+ – 5V). (4) NC = no connection. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 3 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±12V At TA = +25°C, RF = 1.24kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE UNITS MIN/ MAX TEST LEVEL (1) MHz Typ C MHz Min B 114 MHz Typ C GDIFF = 10V/V differential, VO = 20VPP 120 MHz Typ C GDIFF = 10V/V, VO = 20V step, differential 3800 V/µs Min B GDIFF = +5V/V, VO = 2VPP, differential 5 ns Typ C PARAMETER CONDITIONS +25°C GDIFF = 5V/V differential, RF = 1.5kΩ, VO = 2VPP 160 GDIFF = 10V/V differential, RF = 1.24kΩ, VO = 2VPP 150 0.1dB bandwidth flatness GDIFF = 10V/V differential, RF = 1.24kΩ Large-signal bandwidth +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) AC PERFORMANCE Small-signal bandwidth, –3dB (VO = 2VPP) Slew rate (10% to 90% level) Rise and fall time 120 3200 110 3100 100 3000 Harmonic distortion 2nd harmonic 3rd harmonic GDIFF = 10V/V, VO = 2VPP, f = 1MHz, RL = 100Ω 2nd harmonic 3rd harmonic GDIFF = 10V/V, VO = 2VPP, f = 10MHz, RL = 100Ω Full bias –100 Low bias –96 Full bias –89 Low bias –85 –95 –85 –70 –92 –82 –80 Min B dBc Typ C dBc Min B dBc Typ C Full bias –75 –72 Full bias –73 dBc Min B Low bias –58 dBc Typ C –61 –65 dBc Low bias –65 –68 –90 –53 dBc Min B dBc Typ C VDSL2 8b profile +20.5dBm –70 dBc Typ C VDSL2 17a profile +14.5dBm; power supply = ±7.5V –65 dBc Typ C Differential input voltage noise f = 1MHz 2.5 3.0 3.2 3.3 nV/√Hz Max B Differential inverting current noise f = 1MHz 17 20 22 24 pA/√Hz Max B Differential noninverting current noise f = 1MHz 1.2 1.4 1.5 1.6 pA/√Hz Max B RL = 100Ω 700 330 320 300 kΩ Typ A ±15 ±50 ±55 ±60 mV Max A ±110 ±155 µV/°C Max B Multi-tone power ratio (MTPR) G ≈ 11, active termination, SF ≈ 4. DC PERFORMANCE Open-loop transimpedance gain Input offset voltage Input offset voltage drift Input offset voltage matching Channels 1 to 2 and 3 to 4 only Noninverting input bias current ±0.5 ±5 ±6 ±7 mV Max A ±1 ±3 ±4 ±5 µA Max A ±25 ±30 nA/°C Max B ±45 ±50 µA Max A ±115 ±135 nA/°C Max B µA Max A A Noninverting input bias current drift Inverting input bias current ±8 ±40 Inverting input bias current drift Inverting input bias current matching ±8 ±25 ±30 ±35 INPUT CHARACTERISTICS Common-mode input range Each amplifier ±9.5 ±9 ±8.8 ±8.6 V Min Common-mode rejection ratio Each amplifier 65 53 50 49 dB Min A 500 || 2 kΩ || pF Typ C 50 Ω Typ C Noninverting input resistance Inverting input resistance (1) (2) (3) 4 Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS: VS = ±12V (continued) At TA = +25°C, RF = 1.24kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) ±10.8 ±10.6 ±10.5 ±10.4 RL = 25Ω, each output, linear output ±10.4 ±10.2 ±10.1 RL = 25Ω, each output ±416 ±408 ±404 PARAMETER UNITS MIN/ MAX TEST LEVEL (1) V Typ C V Min A ±10.0 V Min A ±400 mA Min A ±1 A Typ C 0.2 Ω Typ C –90 dB Typ C CONDITIONS +25°C RL = 100Ω, each output, linear output ±10.9 RL = 50Ω, each output, linear output OUTPUT CHARACTERISTICS (4) Output voltage swing Output current (sourcing, sinking) Short-circuit output current Output impedance Crosstalk f = 1MHz, differential f = 1MHz, VOUT = 2VPP Port 1 to port 2 POWER SUPPLY Operating voltage V Typ C Maximum operating voltage ±14 ±14 ±14 V Max A Minimum operating voltage ±5 ±5 ±5 V Min B Maximum IS+ quiescent current Minimum IS+ quiescent current Maximum IS– quiescent current Minimum IS– quiescent current ±12 Per port, full bias (Bias-1 = 0, Bias-2 = 0) 21 22.5 23.5 24 mA Max A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 16.2 17.7 18.5 19 mA Max A Per port, mid bias ; RADJ = 604Ω 12.6 14.1 15 15.5 mA Max A Per port, low bias (Bias-1 = 0, Bias-2 = 1) 11.2 12.7 13.4 13.9 mA Max A Per port, bias off (Bias-1 = 1, Bias-2 = 1) 0.5 0.8 0.9 1 mA Max A Per port, full bias (Bias-1 = 0, Bias-2 = 0) 21 19.5 18.5 17 mA Min A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 16.2 14.7 13.7 13 mA Min A Per port, low bias (Bias-1 = 0, Bias-2 = 1) 11.2 9.7 9.1 7.6 mA Min A Per port, full bias (Bias-1 = 0, Bias-2 = 0) 20.5 21.5 22.5 23 mA Max A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 15.7 16.7 17.4 17.8 mA Max A Per port, mid bias ; RADJ = 604Ω 12.1 13.1 14 14.5 mA Max A Per port, low bias (Bias-1 = 0,Bias-2 = 1) 10.7 11.7 12.1 12.4 mA Max A Per port, bias off (Bias-1 = 1, Bias-2 = 1) 0.1 0.3 0.6 0.8 mA Max A Per port, full bias (Bias-1 = 0, Bias-2 = 0) 20.5 19.5 18.5 17.5 mA Min A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 15.7 14.7 13.8 13.6 mA Min A Per port, low bias (Bias-1 = 0, Bias-2 = 1) 10.7 9.7 9.4 9.1 mA Min A Current through GND pin 0.5 mA Typ C Power-supply rejection ratio (+PSRR) 66 54 53 52 dB Min A Power-supply rejection ratio (–PSRR) 65 52 51 50 dB Min A (4) Test circuit is shown in Figure 2. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 5 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±12V (continued) At TA = +25°C, RF = 1.24kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS Logic 1, with respect to GND (5) 1.9 1.9 1.9 Logic 0, with respect to GND (5) 0.8 0.8 0.8 PARAMETER CONDITIONS +25°C MIN/ MAX TEST LEVEL (1) V Min B V Max B A LOGIC Bias control pin logic threshold Bias pin quiescent current Turn-on time delay (tON) Turn-off time delay (tOFF) Bias-X = 0.5V (logic 0) 20 30 33 35 µA Max Bias-X = 3.3V (logic 1) 0.3 1 1.1 1.2 µA Max A Time for IS to reach 50% of final value 1 µs Typ C Bias pin input impedance Amplifier output impedance (5) Off bias (Bias-1 = 1, Bias-2 = 1) 1 µs Typ C 50 kΩ Typ C 10 || 5 kΩ || pF Typ C The GND pin usable range is from VS– to (VS+ – 5V). Table 1. Logic Table 6 BIAS-1 BIAS-2 FUNCTION DESCRIPTION 0 0 Full bias mode Amplifiers on with lowest distortion possible 1 0 Mid bias mode Amplifiers on with power savings and a reduction in distortion performance 0 1 Low bias mode Amplifiers on with enhanced power savings and a reduction of performance 1 1 Shutdown mode Amplifiers off and output has high impedance (default state if left floating) Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS: VS = ±6V At TA = +25°C, RF = 1.5kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE UNITS MIN/ MAX TEST LEVEL (1) MHz Typ C MHz Min B 12 MHz Typ C G = 10V/V differential, VO = 20VPP 140 MHz Typ C G = 10V/V, VO = 20V step, differential 1600 V/µs Min B G = +5V/V, VO = 2VPP, differential 5 ns Typ C PARAMETER CONDITIONS +25°C Small-signal bandwidth, –3dB (VO = 2VPP) G = 5V/V differential, RF = 1.82kΩ 140 G = 10V/V differential, RF = 1.5kΩ 140 0.1dB bandwidth flatness G = 10V/V differential, RF = 1.5kΩ Large-signal bandwidth +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) 110 100 95 AC PERFORMANCE Slew rate (10% to 90% level) Rise and fall time 1200 1100 1000 Harmonic distortion 2nd harmonic 3rd harmonic 2nd harmonic 3rd harmonic G = 10V/V, VO = 2VPP, f = 1MHz, RL = 100Ω differential G = 10V/V, VO = 2VPP, f = 10MHz, RL = 100Ω differential Full bias –98 Low bias –93 Full bias –93 Low bias –89 –92 –84 –75 –89 –81 –79 Min B dBc Typ C dBc Min B dBc Typ C Full bias –80 –74 Full bias –66 dBc Min B Low bias –55 dBc Typ C –58 –68 dBc Low bias –60 –70 –87 –54 dBc Min B dBc Typ C VDSL2 8b profile +20.5dBm –70 dBc Typ C VDSL2 17a profile +14.5dBm; power supply = ±7.5V –65 dBc Typ C Differential input voltage noise f = 1MHz 2.5 3.0 3.2 3.3 nV/√Hz Max B Differential inverting current noise f = 1MHz 17 20 22 24 pA/√Hz Max B Differential noninverting current noise f = 1MHz 1.2 1.4 1.5 1.6 pA/√Hz Max B RL = 100Ω 650 330 320 300 kΩ Typ A ±10 ±45 ±50 ±55 mV Max A ±110 ±155 µV/°C Max B Multi-tone power ratio (MTPR) G ≈ 11, active termination, SF ≈ 4. DC PERFORMANCE Open-loop transimpedance gain Input offset voltage Input offset voltage drift Input offset voltage matching Channels 1 to 2 and 3 to 4 only Noninverting input bias current ±0.5 ±5 ±6 ±7 mV Max A ±1 ±3 ±4 ±5 µA Max A ±25 ±30 nA/°C Max B ±45 ±50 µA Max A ±115 ±135 nA/°C Max B µA Max A A Noninverting input bias current drift Inverting input bias current ±8 ±40 Inverting input bias current drift Inverting input bias current matching ±8 ±25 ±30 ±35 INPUT CHARACTERISTICS Common-mode input range Each amplifier ±3.0 ±2.9 ±2.8 ±2.7 V Min Common-mode rejection ratio Each amplifier 62 51 48 47 dB Min A 500 || 2 kΩ || pF Typ C 55 Ω Typ C Noninverting input resistance Inverting input resistance (1) (2) (3) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 7 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, RF = 1.5kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) ±4.9 ±4.75 ±4.65 ±4.6 RL = 25Ω, each output, linear output ±4.7 ±4.55 ±4.45 RL = 25Ω, each output ±188 ±182 ±178 PARAMETER UNITS MIN/ MAX TEST LEVEL (1) V Typ C V Min A ±4.4 V Min A ±176 mA Min A ±1 A Typ C 0.2 Ω Typ C –90 dB Typ C CONDITIONS +25°C RL = 100Ω, each output, linear output ±4.9 RL = 50Ω, each output, linear output OUTPUT CHARACTERISTICS (4) Output voltage swing Output current (sourcing, sinking) Short-circuit output current Output impedance f = 1MHz, differential f = 1MHz, VOUT = 2VPP Crosstalk Port 1 to port 2 POWER SUPPLY Operating voltage V Typ C Maximum operating voltage ±14 ±14 ±14 V Max A Minimum operating voltage ±5 ±5 ±5 V Min B Maximum IS+ quiescent current Minimum IS+ quiescent current Maximum IS– quiescent current Minimum IS– quiescent current ±6 Per port, full bias (Bias-1 = 0, Bias-2 = 0) 17 21 21.5 22 mA Max A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 13.2 16.8 16.9 17 mA Max A Per port, low bias (Bias-1 = 0, Bias-2 = 1) 9.4 12.2 12.3 12.4 mA Max A Per port, bias off (Bias-1 = 1, Bias-2 = 1) 0.5 0.8 0.9 0.9 mA Max A Per port, full bias (Bias-1 = 0, Bias-2 = 0) 17 13 11.5 10 mA Min A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 13.2 9.8 9.3 8.9 mA Min A Per port, low bias (Bias-1 = 0, Bias-2 = 1) 9.4 6.7 6.4 6.0 mA Min A Per port, full bias (Bias-1 = 0, Bias-2 = 0) 16.5 20.5 21 21.5 mA Max A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 12.7 16.3 16.4 16.5 mA Max A Per port, low bias (Bias-1 = 0,Bias-2 = 1) 8.9 11.7 11.8 11.9 mA Max A Per port, bias off (Bias-1 = 1, Bias-2 = 1) 0.1 0.3 0.4 0.5 mA Max A Per port, full bias (Bias-1 = 0, Bias-2 = 0) 16.5 12.5 11 9.5 mA Min A Per port, mid bias (Bias-1 = 1, Bias-2 = 0) 12.7 9.3 8.8 8.4 mA Min A Per port, low bias (Bias-1 = 0, Bias-2 = 1) 8.9 6.2 5.9 5.5 mA Min A Current through GND pin 0.5 mA Typ C Power-supply rejection ratio (+PSRR) 64 54 53 52 dB Min A Power-supply rejection ratio (–PSRR) 63 52 51 50 dB Min A (4) 8 Test circuit is shown in Figure 2. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, RF = 1.5kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE –40°C to +85°C (3) UNITS Logic 1, with respect to GND (5) 1.9 Logic 0, with respect to GND (5) 0.8 PARAMETER CONDITIONS +25°C +25°C (2) 0°C to +70°C (3) MIN/ MAX TEST LEVEL (1) V Min B V Max B A LOGIC Bias control pin logic threshold Bias pin quiescent current Turn-on time delay (tON) Turn-off time delay (tOFF) Bias-X = 0.5V (logic 0) 20 30 33 35 µA Max Bias-X = 3.3V (logic 1) 0.3 1 1.1 1.2 µA Max A Time for IS to reach 50% of final value 1 µs Typ C Bias pin input impedance Amplifier output impedance (5) Off bias (Bias-1 = 1, Bias-2 = 1) 1 µs Typ C 50 kΩ Typ C 10 || 5 kΩ || pF Typ C The GND pin usable range is from VS– to (VS+ – 5V). Table 2. Logic Table BIAS-1 BIAS-2 FUNCTION DESCRIPTION 0 0 Full bias mode Amplifiers on with lowest distortion possible 1 0 Mid bias mode Amplifiers on with power savings and a reduction in distortion performance 0 1 Low bias mode Amplifiers on with enhanced power savings and a reduction of performance 1 1 Shutdown mode Amplifiers off and output has high impedance (default state if left floating) Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 9 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, Full Bias At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE vs BIAS MODE SMALL-SIGNAL FREQUENCY RESPONSE 3 3 GDIFF = 5V/V RF = 1.5kW 0 Normalized Gain (dB) Normalized Gain (dB) 0 -3 -6 GDIFF = 10V/V RF = 1.24kW -9 GCM = 1V/V VO = 2VPP RADJ = 0W RL = 100W -12 -15 -18 Full Bias -3 -6 75% Bias -9 -12 -15 -18 10 100 400 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RADJ = 0W RL = 100W 50% Bias 10 100 Frequency (MHz) Frequency (MHz) Figure 2. Figure 3. LARGE SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL AND LARGE-SIGNAL PULSE RESPONSE 12 3 Large-Signal Pulse Response (±10VP) Left Scale Output Voltage (V) -3 -6 VO = 20VPP -9 GDIFF = 10V/V GCM = 1V/V RADJ = 0W RL = 100W -12 -15 VO = 8VPP 4 0.8 0.4 Small-Signal ±500mVP Right Scale 0 0 -4 -0.4 -8 -0.8 -12 -18 0 60 120 180 240 Output Voltage (V) Normalized Gain (dB) 8 VO = 2VPP 1.2 GDIFF = 10V/V GCM = 1V/V RL = 100W RF = 1.2kW VO = 4VPP 0 300 -1.2 Time (10ns/div) 300 Frequency (MHz) Figure 4. Figure 5. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 23 100 RS Optimized for 100% Bias 22pF 20 470pF 17 Gain (dB) RS (W) 100pF 10 14 THS6204 10 100 10 1000 CL VIN 5 1 47pF 11 8 1 39pF RS 1kW VOUT Optional RS THS6204 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 6. Figure 7. Submit Documentation Feedback 300M Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±12V, Full Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 -60 -70 -75 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W GDIFF = 10V/V GCM = 1V/V RL = 100W f = 1MHz 3rd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) -65 2nd Harmonic -80 -85 -90 -95 -100 -70 -80 3rd Harmonic -90 -100 -105 2nd Harmonic -110 -110 400k 10M 1M 0.5 40M 1 10 Figure 8. Figure 9. HARMONIC DISTORTION vs SUPPLY VOLTAGE -75 Harmonic Distortion (dBc) HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -80 -85 3rd Harmonic -90 -95 2nd Harmonic -65 Harmonic Distortion (dBc) -70 -100 -105 GDIFF = 10V/V GCM = 1V/V VO = 2VPP f = 1MHz -75 -85 3rd Harmonic -95 -105 2nd Harmonic -115 -125 4 5 6 7 8 9 10 11 12 50 100 Supply Voltage (±VS) 1k Resistance (W) Figure 10. Figure 11. HARMONIC DISTORTION vs NONINVERTING GAIN 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT 55 -65 50 -75 3rd Harmonic Intercept Point (dBm) Harmonic Distortion (dBc) 20 Output Voltage (VPP) Frequency (Hz) -85 -95 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -105 -115 2nd Harmonic 45 40 35 30 25 GDIFF = 10V/V GCM = 1V/V 20 -125 15 1 10 30 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 11 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, Full Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE DENSITY OUTPUT VOLTAGE AND CURRENT LIMITATIONS Output Voltage (V) Output Voltage Noise Density (nV/ÖHz) Input Current Noise Density (pA/ÖHz) 1000 12 10 GDIFF = 10V/V 8 GCM = 1V/V 6 4 2 0 -2 1W Internal -4 Power Dissipation -6 -8 -10 -12 -14 -200 -600 -400 1W Internal Power Dissipation 50W Load Line 100W Load Line Voltage and current noise contributing to differential noise. 100 Inverting Current Noise (17.4pA/ÖHz) Voltage Noise (2.5nV/ÖHz) 10 1 0 200 400 600 1k 100 10k Output Current (mA) 100k 1M 10M Frequency (Hz) Figure 14. Figure 15. SUPPLY CURRENT FOR FULL BIAS SETTINGS vs RADJ PSRR vs FREQUENCY 25 Power-Supply Rejection Ratio (dB) 60 20 ±IQ (mA) Noninverting Current Noise (1.2pV/ÖHz) 15 +IQ 10 -IQ 5 -PSRR 50 +PSRR 40 30 20 10 0 0 0 1 2 3 4 5 6 1k 10k 100k 1M RADJ (kW) Frequency (Hz) Figure 16. Figure 17. OPEN-LOOP GAIN AND PHASE 10M 100M CLOSED-LOOP OUTPUT IMPEDANCE 140 10 0 100 -90 Phase 80 -135 60 -180 40 -225 20 GDIFF = 10V/V GCM = 1V/V -315 100k 1 0.1 0.01 -270 0 10k Output Impedance (W) -45 Transimpedance Phase (°) Transimpedance Gain (dBW) Gain 120 1M 10M 100M 1G 0.001 100k Frequency (Hz) 10M 100M Frequency (Hz) Figure 18. 12 1M Figure 19. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±12V, 75% Bias At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 3 3 GDIFF = 5V/V RF = 1.5kW VO = 2VPP 0 Normalized Gain (dB) Normalized Gain (dB) 0 -3 GDIFF = 10V/V RF = 1.24kW -6 -9 -12 GCM = 1V/V VO = 2VPP RL = 100W -15 -18 -3 -6 VO = 20VPP VO = 4VPP -9 -12 GCM = 1V/V GDIFF = 10V/V RL = 100W -15 VO = 8VPP -18 10 100 0 300 20 40 60 80 100 120 140 160 180 200 220 240 260 Frequency (MHz) Frequency (MHz) Figure 20. Figure 21. DIFFERENTIAL SMALL-SIGNAL AND LARGE-SIGNAL PULSE RESPONSE SUPPLY CURRENT FOR FULL BIAS SETTINGS vs RADJ 12 1.2 8 0.8 4 0.4 18 16 0 Small-Signal ±500mVP Right Scale -4 -0.4 Large-Signal Pulse Response (±10VP) Left Scale -8 12 ±IQ (mA) 0 Output Voltage (V) Output Voltage (V) 14 10 8 +IQ 6 -IQ 4 -0.8 2 -12 -1.2 0 0 Time (10ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 22. Figure 23. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 23 100 RS Optimized for 100% Bias 22pF 20 470pF 17 Gain (dB) RS (W) 100pF 10 14 THS6204 100 10 1000 CL VIN 5 1 47pF 11 8 1 39pF RS 1kW VOUT Optional RS THS6204 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 300M 13 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, 75% Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 -40 -60 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W GDIFF = 10V/V GCM = 1V/V RL = 100W f = 1MHz -65 -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 3rd Harmonic -80 -90 2nd Harmonic -100 -110 -70 -75 3rd Harmonic -80 -85 -90 2nd Harmonic -95 -100 -105 -120 100k -110 10M 1M 0 30M 4 2 6 Figure 26. 10 12 14 16 Figure 27. HARMONIC DISTORTION vs SUPPLY VOLTAGE HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -75 -80 3rd Harmonic -85 -90 -95 -60 Harmonic Distortion (dBc) -70 Harmonic Distortion (dBc) 8 Output Voltage (VPP) Frequency (Hz) GDIFF = 10V/V GCM = 1V/V VO = 2VPP f = 1MHz -70 -80 3rd Harmonic -90 -100 2nd Harmonic -110 2nd Harmonic -100 -120 4 5 6 7 8 9 10 11 12 10 100 Supply Voltage (±VS) Figure 29. HARMONIC DISTORTION vs NONINVERTING GAIN 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT 55 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -85 -90 50 Intercept Point (dBm) Harmonic Distortion (dBc) Resistance (W) Figure 28. -80 3rd Harmonic -95 45 40 35 30 25 -100 2nd Harmonic GDIFF = 10V/V GCM = 1V/V 20 15 -105 1 10 20 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) Figure 30. 14 1k Figure 31. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±12V, 50% Bias At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. 50% BIAS FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 3 3 0 Normalized Gain (dB) Normalized Gain (dB) VO = 2VPP GDIFF = 5V/V RF = 1.5kW 0 -3 GDIFF = 10V/V RF = 1.24kW -6 -9 -12 GCM = 1V/V VO = 2VPP RL = 100W -15 -18 VO = 4VPP -6 VO = 8VPP -9 VO = 20VPP -12 -18 100 0 300 40 60 80 100 120 140 160 180 200 220 Frequency (MHz) Figure 32. Figure 33. DIFFERENTIAL PULSE RESPONSE SUPPLY CURRENT FOR FULL BIAS SETTINGS vs RADJ 14 8 0.8 12 4 0.4 0 0 -0.4 Large-Signal Pulse Response (±10VP) Left Scale -12 10 ±IQ (mA) Small-Signal ±500mVP Right Scale Output Voltage (V) 1.2 -8 20 Frequency (MHz) 12 -4 GDIFF = 10V/V RL = 100W -15 10 Output Voltage (V) -3 8 6 +IQ 4 -IQ -0.8 2 -1.2 0 0 Time (10ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 34. Figure 35. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 26 100 RS Optimized for 100% Bias 22pF 23 20 Gain (dB) RS (W) 100pF 10 17 39pF RS 470pF THS6204 14 47pF 11 CL VIN 1kW VOUT Optional 8 RS 5 1 1 100 10 1000 THS6204 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 200M 15 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±12V, 50% Bias (continued) At TA = +25°C, GDIFF = +10V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.24kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY -60 -70 HARMONIC DISTORTION vs OUTPUT VOLTAGE -65 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W GDIFF = 10V/V GCM = 1V/V RL = 100W f = 1MHz -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 3rd Harmonic -80 2nd Harmonic -90 -100 -75 3rd Harmonic -80 -85 -90 2nd Harmonic -95 -100 -110 100k -105 10M 1M 0 30M 4 2 6 Figure 38. HARMONIC DISTORTION vs SUPPLY VOLTAGE 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -75 -80 3rd Harmonic -90 -95 -65 GDIFF = 10V/V GCM = 1V/V VO = 2VPP f = 1MHz -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 Figure 39. -70 -85 8 Output Voltage (VPP) Frequency (Hz) 2nd Harmonic -75 -80 -85 3rd Harmonic -90 -95 -100 -105 -110 2nd Harmonic -115 -100 -120 4 5 6 7 8 9 10 11 12 10 100 Supply Voltage (±VS) 1k Resistance (W) Figure 40. Figure 41. HARMONIC DISTORTION vs NONINVERTING GAIN 2-TONE, 3RD-ORDER, INTERMODULATION INTERCEPT 55 -80 3rd Harmonic Intercept Point (dBm) Harmonic Distortion (dBc) 50 -85 -90 -95 GDIFF = 10V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -100 2nd Harmonic 45 40 35 30 25 GDIFF = 10V/V GCM = 1V/V 20 15 -105 1 10 20 0 Figure 42. 16 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) Figure 43. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±6V, Full Bias At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. FULL BIAS FREQUENCY RESPONSE 3 0 0 Normalized Gain (dB) Normalized Gain (dB) SMALL-SIGNAL FREQUENCY RESPONSE 3 -3 -6 GDIFF = 10V/V -9 -12 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W -15 -18 -6 -12 -18 100 75% Bias -9 -15 10 300 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W 50% Bias 10 100 Frequency (MHz) Frequency (MHz) Figure 44. Figure 45. LARGE-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL AND LARGE-SIGNAL PULSE RESPONSE 12 3 GDIFF = 5V/V GCM = 1V/V RL = 100W 0 Output Voltage (V) -3 VO = 4VPP -6 8 VO = 16VPP -9 VO = 2VPP -12 VO = 20VPP -15 Large-Signal Pulse Response (±10VP) Left Scale 4 300 GDIFF = 10V/V GCM = 1V/V RL = 100W RF = 1.2kW Small-Signal ±500mVP Right Scale 0 0 50 100 150 200 250 300 0.8 0.4 0 -4 -0.4 -8 -0.8 -12 -18 1.2 Output Voltage (V) Normalized Gain (dB) Full Bias -3 -1.2 Time (10ns/div) 350 Frequency (MHz) Figure 46. Figure 47. DIFFERENTIAL RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 17 100 RS Optimized for 100% Bias 14 Gain (dB) RS (W) 470pF 10 22pF 11 RS THS6204 100pF 39pF 8 CL VIN 5 1kW VOUT Optional 47pF RS THS6204 1 1 100 10 1000 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 48. Figure 49. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 300M 17 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6V, Full Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY -60 -70 HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 3rd Harmonic -80 -90 2nd Harmonic -100 -110 100k GDIFF = 5V/V GCM = 1V/V RL = 100W f = 1MHz -70 3rd Harmonic -80 -90 2nd Harmonic -100 -110 10M 1M 0 30M 4 2 6 Figure 50. HARMONIC DISTORTION vs SUPPLY VOLTAGE -90 -92 3rd Harmonic -94 -96 2nd Harmonic -98 -75 14 16 GDIFF = 5V/V GCM = 1V/V VO = 2VPP f = 1MHz -80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 12 HARMONIC DISTORTION vs LOAD RESISTANCE GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -85 -90 -95 3rd Harmonic -100 -105 -110 -100 2nd Harmonic -115 4 5 6 7 8 9 10 11 12 10 100 Supply Voltage (±VS) 1k Resistance (W) Figure 52. Figure 53. HARMONIC DISTORTION vs NONINVERTING GAIN 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT 60 -85 50 -90 3rd Harmonic -95 -100 2nd Harmonic -105 1 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz 10 20 Intercept Point (dBm) Harmonic Distortion (dBc) 10 Figure 51. -88 40 30 20 GDIFF = 10V/V GCM = 1V/V 10 0 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) Figure 54. 18 8 Output Voltage (VPP) Frequency (Hz) Figure 55. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±6V, Full Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. SUPPLY CURRENT FOR FULL BIAS SETTING vs RADJ 20 18 16 ±IQ (mA) 14 12 10 8 +IQ 6 -IQ 4 2 0 0 1 2 3 4 5 6 RADJ (kW) Figure 56. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 19 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6V, 75% Bias At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. 75% BIAS FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 3 3 0 Normalized Gain (dB) Normalized Gain (dB) VO = 2VPP GDIFF = 5V/V RF = 1.82kW 0 -3 -6 -9 -12 GCM = 1V/V VO = 2VPP RL = 100W -15 -18 GDIFF = 10V/V RF = 1.5kW VO = 8VPP VO = 4VPP -6 -9 VO = 20VPP -12 GDIFF = 5V/V GCM = 1V/V RL = 100W -15 -18 10 100 300 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 Frequency (MHz) Frequency (MHz) Figure 57. Figure 58. DIFFERENTIAL SMALL-SIGNAL AND LARGE-SIGNAL PULSE RESPONSE 6 1.2 4 0.8 2 0.4 0 0 SUPPLY CURRENT FOR FULL BIAS SETTING vs RADJ 16 14 Small-Signal ±500mVP Right Scale -2 -0.4 Large-Signal Pulse Response (±5VP) Left Scale -4 -6 ±IQ (mA) 12 Output Voltage (V) Output Voltage (V) -3 10 8 +IQ 6 -IQ 4 -0.8 2 -1.2 0 0 Time (10ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 59. Figure 60. DIFFERENTIAL RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 17 100 22pF RS Optimized for 100% Bias 14 470pF 39pF Gain (dB) RS (W) RS 10 11 8 THS6204 CL VIN 1kW VOUT Optional 100pF RS 5 THS6204 47pF 1 1 20 100 10 1000 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 61. Figure 62. Submit Documentation Feedback 200M Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±6V, 75% Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 -40 -60 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 3rd Harmonic -70 -80 -90 2nd Harmonic -100 -110 100k GDIFF = 5V/V GCM = 1V/V RL = 100W f = 1MHz -70 3rd Harmonic -80 -90 2nd Harmonic -100 -110 10M 1M 0 30M 4 2 6 Figure 63. HARMONIC DISTORTION vs SUPPLY VOLTAGE 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE -70 GDIFF = 5V/V GCM = 1V/V VO = 2VPP f = 1MHz -75 3rd Harmonic -92 -94 -96 2nd Harmonic GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -98 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 Figure 64. -88 -90 8 Output Voltage (VPP) Frequency (Hz) -80 -85 -90 -95 3rd Harmonic -100 -105 2nd Harmonic -110 -100 4 5 6 7 8 9 10 11 -115 12 10 100 Supply Voltage (±VS) Resistance (W) Figure 65. Figure 66. HARMONIC DISTORTION vs NONINVERTING GAIN 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT 60 -85 50 -90 3rd Harmonic -95 -100 2nd Harmonic -105 1 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz 10 20 Intercept Point (dBm) Harmonic Distortion (dBc) 1k 40 30 20 10 GDIFF = 10V/V GCM = 1V/V 0 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) Figure 67. Figure 68. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 21 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6V, 50% Bias At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. 50% BIAS FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 3 3 0 Normalized Gain (dB) Normalized Gain (dB) VO = 2VPP GDIFF = 5V/V RF = 1.82kW 0 -3 -6 GDIFF = 10V/V RF = 1.5kW -9 -12 GCM = 1V/V VO = 2VPP RL = 100W -15 -18 VO = 20VPP -6 -9 -12 -18 100 0 300 40 60 80 100 120 140 160 180 200 220 Frequency (MHz) Figure 69. Figure 70. DIFFERENTIAL PULSE RESPONSE SUPPLY CURRENT FPR FULL BIAS SETTING vs RADJ 12 4 0.8 10 2 0.4 0 Small-Signal ±500mVP Right Scale -0.4 Large-Signal Pulse Response (±5VP) Left Scale -6 8 ±IQ (mA) 0 Output Voltage (V) 1.2 -4 20 Frequency (MHz) 6 -2 VO = 8VPP GDIFF = 5V/V GCM = 1V/V RL = 100W -15 10 Output Voltage (V) VO = 4VPP -3 6 +IQ 4 -IQ -0.8 2 -1.2 0 0 Time (10ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 71. Figure 72. DIFFERENTIAL RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 20 100 RS Optimized for 100% Bias 17 100pF 22pF Gain (dB) RS (W) 14 10 470pF RS THS6204 11 39pF 8 CL VIN 1kW VOUT Optional 47pF RS 5 THS6204 1 1 22 100 10 1000 2 10M 100M Capacitive Load (pF) Frequency (Hz) Figure 73. Figure 74. Submit Documentation Feedback 200M Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS: VS = ±6V, 50% Bias (continued) At TA = +25°C, GDIFF = +5V/V, GCM = 1V/V, RADJ = 0Ω, RF = 1.82kΩ, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 -40 -60 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W GDIFF = 5V/V GCM = 1V/V RL = 100W f = 1MHz 3rd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 -70 -80 2nd Harmonic -90 -100 -110 100k -70 3rd Harmonic -80 -90 2nd Harmonic -100 -110 10M 1M 0 30M 4 2 6 Figure 75. HARMONIC DISTORTION vs SUPPLY VOLTAGE 12 14 16 HARMONIC DISTORTION vs LOAD RESISTANCE -70 -86 -75 -88 3rd Harmonic -90 GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -92 -94 2nd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 Figure 76. -84 -96 8 Output Voltage (VPP) Frequency (Hz) -98 GDIFF = 5V/V GCM = 1V/V VO = 2VPP f = 1MHz -80 -85 -90 3rd Harmonic -95 -100 -105 2nd Harmonic -100 -110 4 5 6 7 8 9 10 11 12 10 100 Supply Voltage (±VS) Resistance (W) Figure 77. Figure 78. HARMONIC DISTORTION vs NONINVERTING GAIN 2-TONE, 3RD-ODER INTERMODULATION INTERCEPT 60 -80 50 -85 3rd Harmonic -90 -95 -100 2nd Harmonic GDIFF = 5V/V GCM = 1V/V VO = 2VPP RL = 100W f = 1MHz -105 1 10 20 Intercept Point (dBm) Harmonic Distortion (dBc) 1k 40 30 20 10 GDIFF = 10V/V GCM = 1V/V 0 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) Figure 79. Figure 80. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 23 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com APPLICATION INFORMATION WIDEBAND CURRENT-FEEDBACK OPERATION The THS6204 gives the exceptional ac performance of a wideband current-feedback op amp with a highly linear, high-power output stage. Requiring only 9mA/ch quiescent current, the THS6204 swings to within 1V of either supply rail and delivers in excess of 380mA at room temperature. This low-output headroom requirement, along with supply voltage independent biasing, gives remarkable ±6V supply operation. The THS6204 delivers greater than 145MHz bandwidth driving a 2VPP output into 100Ω on a ±6V supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion as the output current goes through zero. The THS6204 achieves a comparable power gain with much better linearity. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that ac performance (bandwidth and distortion) is relatively independent of signal gain. Figure 81 shows the dc-coupled, gain of +10V/V, dual power-supply circuit configuration used as the basis of the ±12V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the electrical characteristics are taken directly at the input and output pins, whereas load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 81, the total effective load is 100Ω || 1.24kΩ || 1.24kΩ = 86.1Ω. +12V 1/2 THS6204 RF 1.24kW VI RG 274W RF 1.24kW This approach provides for a source termination impedance at the input that is independent of the signal gain. For instance, simple differential filters may be included in the signal path right up to the noninverting inputs without interacting with the gain setting. The differential signal gain for the circuit of Figure 81 is: RF AD = 1 + 2 ´ RG (1) Because the THS6204 is a current feedback (CFB) amplifier, its bandwidth is primarily controlled with the feedback resistor value; Figure 81 shows a value of 274Ω for the AD = +10V/V design. The differential gain, however, may be adjusted with considerable freedom using just the RG resistor. In fact, RG may be a reactive network providing a very isolated shaping to the differential frequency response. Various combinations of single-supply or ac-coupled gain can also be delivered using the basic circuit of Figure 81. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of +1V/V since an equal dc voltage at each inverting node creates no current through RG. This circuit does show a common-mode gain of +1V/V from input to output. The source connection should either remove this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a problem, the output interface may also be used to reject that common-mode. For instance, most modern differential input ADCs reject common-mode signals very well, while a line driver application through a transformer will also attenuate the common-mode signal through to the line. VO RL 1/2 THS6204 GDIFF = 1 + -12V 2 ´ RF RG = VO VI Figure 81. Noninverting Differential I/O Amplifier 24 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 DUAL-SUPPLY VDSL DOWNSTREAM Figure 82 shows an example of a dual-supply VDSL downstream driver. Both channels of the THS6204 are configured as a differential gain stage to provide signal drive to the primary winding of the transformer (here, a step-up transformer with a turns ratio of 1:1.1). The main advantage of this configuration is the cancellation of all even harmonic distortion products. Another important advantage for VDSL is that each amplifier needs only to swing half of the total output required driving the load. +12V 20W 1/4 THS6204 IP = 159mA RS 9.1W RF 2kW 0.1mF RG 1.33kW 2kW 0.1mF 20W ZLINE RP 2.7kW RF 2kW 1/4 THS6204 LINE DRIVER HEADROOM MODEL The first step in a transformer-coupled, twisted-pair driver design is to compute the peak-to-peak output voltage from the target specifications. This is done using the following equations: VRMS2 PL = 10 ´ log (1mW) ´ RL (4) with PL power at the load, VRMS voltage at the load, and RL load impedance; this gives the following: RP 2.7kW 2kW AFE 2VPP Max Assumed 1:1.1 the phone line, and also provide a means of detecting the received signal for the receiver. The value of these resistors (RM) is a function of the line impedance and the transformer turns ratio (n), given by the following equation: ZLINE RM = 2n2 (3) RL 100W RS 9.1W VRMS = (1mW) ´ RL ´ 10 PL 10 (5) VP = CrestFactor ´ VRMS = CF ´ VRMS (6) with VP peak voltage at the load and CF Crest Factor. VLPP = 2 ´ CF ´ VRMS (7) IP = 159mA with VLPP: peak-to-peak voltage at the load. -12V Figure 82. Dual-Supply VDSL Downstream Driver The analog front end (AFE) signal is ac-coupled to the driver, and the noninverting input of each amplifier is biased to the mid-supply voltage (ground in this case). In addition to providing the proper biasing to the amplifier, this approach also provides a high-pass filtering with a corner frequency, set here at 5kHz. As the signal bandwidth starts at 26kHz, this high-pass filter does not generate any problem and has the advantage of filtering out unwanted lower frequencies. The input signal is amplified with a gain set by the following equation: 2 ´ RF GD = 1 + RG (2) Consolidating Equation 4 through Equation 7 allows expressing the required peak-to-peak voltage at the load as a function of the crest factor, the load impedance, and the power at the load. Thus, VLPP = 2 ´ CF ´ (1mW) ´ RL ´ 10 PL 10 (8) This VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target. The next step in the design is to compute the individual amplifier output voltage and currents as a function of VPP on the line and transformer turns ratio. As this turns ratio changes, the minimum allowed supply voltage changes along with it. The peak current in the amplifier output is given by: 2 ´ VLPP 1 1 ±IP = ´ ´ n 2 4RM (9) With RF = 2kΩ and RG = 1.33kΩ, the gain for this differential amplifier is RP = 2.1kΩ. This gain boosts the AFE signal, assumed to be a maximum of 2VPP, to a maximum of 3VPP. The two back-termination resistors (9.1Ω each) added at each terminal of the transformer make the impedance of the modem match the impedance of Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 25 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com with VPP as defined in Equation 8, and RM as defined in Equation 3 and shown in Figure 83. V1, V2, R1, and R2 are given in Table 3 for ±12V operation. Table 3. Line Driver Headroom Model Values RM ±12V VPP = 2VLPP n VLPP n RL VLPP R1 V2 R2 0.6V 1V 1.2V When using a synthetic output impedance circuit, such as the one shown in Figure 82, a significant drop is noticed in bandwidth from the bandwidth appearing in the Electrical Characteristics tables. This apparent drop in bandwidth for the differential signal is a result of the apparent increase in the feedback transimpedance as seen for each amplifier. This feedback transimpedance equation is given below. RM Figure 83. Driver Peak Output Voltage With the previous information available, it is now possible to select a supply voltage and the turns ratio desired for the transformer as well as calculate the headroom for the THS6204. The model, shown in Figure 84, can be described with the following set of equations: 1. As available output swing: VPP = VCC - (V1 + V2) - IP ´ (R1 + R2) (10) 2. Or as required supply voltage: VCC = VPP + (V1 + V2) + IP ´ (R1 + R2) V1 1V 1+2´ ZFB = RF ´ RS 1+2´ RS + RL + RS RP RL RS RP - RF RP (12) To increase 0.1dB flatness to the frequency of interest, adding a serial R-C in parallel with the gain resistor may be needed, as shown in Figure 85. RS 1/4 THS6204 (11) RF The minimum supply voltage for a power and load requirement is given by Equation 11. RP RM +VCC ZLINE VIN RG RP 100W CM R1 RF V1 1/4 THS6204 RS VO IP Figure 85. 0.1dB Flatness Compensation Circuit V2 R2 Figure 84. Line Driver Headroom Model 26 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 TOTAL DRIVER POWER FOR xDSL APPLICATIONS PTOT = 21mA (24V) + The total internal power dissipation for the THS6204 in an xDSL line driver application will be the sum of the quiescent power and the output stage power. The THS6204 holds a relatively constant quiescent current versus supply voltage—giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage will be greater than the solution given in Equation 11). The total output stage power may be computed with reference to Figure 86. +VCC IAVG = IP CF RT Figure 86. Output Stage Power Model The two output stages used to drive the load of Figure 83 can be seen as an H-Bridge in Figure 86. The average current drawn from the supply into this H-Bridge and load will be the peak current in the load given by Equation 9 divided by the crest factor (CF) for the xDSL modulation. This total power from the supply is then reduced by the power in RT to leave the power dissipated internal to the drivers in the four output stage transistors. That power is simply the target line power used in Equation 4 plus the power lost in the matching elements (RM). In the examples here, a perfect match is targeted giving the same power in the matching elements as in the load. The output stage power is then set by Equation 12. IP POUT = ´ VCC - 2PL CF (13) The total amplifier power is then: IP PTOT = IQ ´ VCC + ´ VCC - 2PL CF (14) For the ADSL CO driver design of Figure 82, the peak current is 159mA for a signal that requires a crest factor of 5.6 with a target line power of 20.5dBm into 100Ω (115mW). With a typical quiescent current of 21mA and a nominal supply voltage of ±12V, the total internal power dissipation for the solution of Figure 82 will be: 159mA (24V) - 2(115mW) = 955mW 5.6 (15) OUTPUT CURRENT AND VOLTAGE The THS6204 provides output voltage and current capabilities that are unsurpassed in a low-cost dual monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1.1V to either supply rail; tested at +25°C swing limit is within 1.4V of either rail into a 100Ω differential load. Into a 25Ω load (the minimum tested load), it delivers more than ±408mA continuous and > ±1A peak output current. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage times current (or V-I product) that is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot (Figure 14) in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the THS6204 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation (in this case for 1 channel only). Superimposing resistor load lines onto the plot shows that the THS6204 can drive ±10.9V into 100Ω or ±10.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±12V output swing capability, as shown in the Electrical Characteristics tables. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristics tables. As the output transistors deliver power, the junction temperatures increases, decreasing the VBEs (increasing the available output voltage swing), and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. To maintain maximum output stage linearity, no output short-circuit protection is provided. This is normally not a problem because most applications include a series-matching resistor at the output that limits the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power-supply pin (24-pin package), will in most cases, destroy the amplifier. If additional short-circuit protection is required, a small Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 27 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com series resistor may be included in the supply lines. Under heavy output loads this will reduce the available output voltage swing. A 5Ω series resistor in each power-supply lead will limit the internal power dissipation to less than 1W for an output short circuit while decreasing the available output voltage swing only 0.5V for up to 100mA desired load currents. Always place the 0.1µF power-supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain amplifier such as the THS6204 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the THS6204. Long printed-circuit board (PCB) traces, unmatched cables, and 28 connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the THS6204 output pin (see the Board Layout Guidelines section). DISTORTION PERFORMANCE The THS6204 provides good distortion performance into a 100Ω load on ±12V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operation on a dual ±6V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the second harmonic dominates the distortion with a negligible third harmonic component. Focusing then on the second harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 81), this is the sum of RF + RG, whereas in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the second-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the second harmonic increasing at a little less than the expected 2x rate whereas the third harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the difference between it and the second harmonic decreases less than the expected 6dB, whereas the difference between it and the third harmonic decreases by less than the expected 12dB. This also shows up in the two-tone, third-order intermodulation spurious (IM3) response curves. The third-order spurious levels are extremely low at low-output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 DIFFERENTIAL NOISE PERFORMANCE As the THS6204 is used as a differential driver in xDSL applications, it is important to analyze the noise in such a configuration. Figure 87 shows the op amp noise model for the differential configuration. Dividing this expression by the differential noise gain (GD = (1 + 2RF/RG)) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 18. EO = 2 2 2 ´ eN + (iN ´ RS) + 4kTRS + 2 iIRF 2 +2 4kTRF GD IN (18) Evaluating these equations for the THS6204 ADSL circuit and component values of Figure 82 gives a total output spot noise voltage of 38.9nV/√Hz and a total equivalent input spot noise voltage of 7nV/√Hz. Driver EN RS IN ERS RF In order to minimize the output noise due to the noninverting input bias current noise, it is recommended to keep the noninverting source impedance as low as possible. Ö4kTRF Ö4kTRS RG 2 EO Ö4kTRG RF Ö4kTRF IN EN RS IN ERS Ö4kTRS Figure 87. Differential Op Amp Noise Analysis Model As a reminder, the differential gain is expressed as: 2 ´ RF GD = 1 + RG (16) The output noise can be expressed as shown below: EO = 2 GD 2 DC ACCURACY AND OFFSET CONTROL A current-feedback op amp such as the THS6204 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate dc accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers; however, the two input bias currents are somewhat higher and are unmatched. While bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output dc offset for wideband current-feedback op amps. Because the two input bias currents are unrelated in both magnitude and polarity, matching the input source impedance to reduce error contribution to the output is ineffective. Evaluating the configuration of Figure 81, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: VOFF = ± (NG × VOS(MAX)) + (IBN × RS/2 × NG) ± (IBI × RF) where NG = noninverting signal gain = ± (10 × 5mV) + (3µA × 25Ω × 10) ± (1.24kΩ × 40µA) 2 2 ´ GD2 ´ eN + (iN ´ RS) + 4kTRS + 2(iIRF) + 2(4kTRFGD) (17) = ±50mV + 0.75mV ± 49.6mV VOFF = –98.85mV to +100.35mV Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 29 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com POWER CONTROL OPERATION The THS6204 provides a power control feature that may be used to reduce system power. The four modes of operation for this power control feature are full-power, power cutback, idle state, and power shutdown. These four operating modes are set through two logic lines A0 and A1. Table 4 shows the different modes of operation. Table 4. Power Control Mode of Operation MODE OF OPERATION BIAS 1 BIAS 2 Full bias mode 0 0 Mid bias mode 1 0 Low bias mode 0 1 Shutdown 1 1 The full-power mode is used for normal operating condition. The power cutback mode brings the quiescent power to 13.5mA. The idle state mode keeps a low output impedance but reduces output power and bandwidth. The shutdown mode has a high output impedance as well as the lowest quiescent power (0.5mA). If the Bias 1 and Bias 2 pins are left unconnected, the THS6204 shuts down. DEVICE PROTECTION FEATURE The THS6204 has a built-in thermal protection feature. Should the internal junction temperature rise above approximately +160°C, the device automatically shuts down. Such a condition could exist with improper heat sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown circuit automatically turns the device back on. This occurs at approximately +145°C, junction temperature. Note that the THS6204 does not have short-circuit protection and care should be taken to minimize the output current below the absolute maximum ratings. THERMAL INFORMATION The THS6204 is available in thermally-enhanced RHF and PWP packages, which are members of the PowerPAD family of packages. These packages are constructed using leadframes upon which the dies are mounted (see Figure 88 for the RHF package and Figure 89 for the PWP package). This arrangement results in the lead frames being exposed as thermal pads on the underside of their respective packages. Because a thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that the PowerPAD is electronically isolated from the active circuitry and any pins. Thus, the PowerPAD can be connected to any potential voltage within the absolute maximum voltage range. Ideally, connection of the PAD to the most negative supply plane is preferred. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. This is discussed in more detail in the PCB design considerations section of this document. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) (1) The thermal pad is electrically isolated from all terminals in the package. Figure 88. Views of Thermally-Enhanced RHF Package (Representative Only—Not to Scale) 30 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) (1) The thermal pad is electrically isolated from all terminals in the package. Figure 89. Views of Thermally-Enhanced PWP Package (Representative Only—Not to Scale) THERMAL ANALYSIS BOARD LAYOUT GUIDELINES Due to the high output power capability of the THS6204, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature sets the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +130°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipation in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. A PDL depends on the required output signal and load; using the previously developed model described in the Total Driver Power for xDSL Applications section, compute the maximum TJ using a THS6204 QFN-24 in the circuit of Figure 81 operating at the maximum specified ambient temperature of +85°C. Maximum TJ = +85°C + (0.955 ´ 32°C/W) = 115.5°C Achieving optimum performance with a high-frequency amplifier like the THS6204 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: (19) Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower tested junction temperatures. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The output V-I plot shown in the Typical Characteristics includes a boundary for 1W maximum internal power dissipation under these conditions. a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves second-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These can be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 31 THS6204 SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com c) Careful selection and placement of external components preserve the high-frequency performance of the THS6204. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency performance. Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing the value reduces the bandwidth, whereas decreasing it gives a more peaked frequency response. The 1.24kΩ feedback resistor used in the Typical Characteristics at a gain of +10V/V on ±12V supplies is a good starting point for design. Note that a 1.5kΩ feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (Figure 6, Figure 24, and Figure 36). Low parasitic capacitive loads (< 5pF) may not need an RS because the THS6204 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board; in fact, a higher impedance environment improves 32 distortion (see the distortion versus load plots). With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS6204 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device. This total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the THS6204 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load (Figure 6, Figure 24, and Figure 36). However, this does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the THS6204 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS6204 directly onto the board. f) Use the –VS plane to conduct heat out of the QFN-24 and TSSOP-24 PowerPAD packages. These packages attach the die directly to an exposed thermal pad on the bottom, which should be soldered to the board. This pad must be connected electrically to the same voltage plane as the most negative supply applied to the THS6204 (in Figure 82, this would be –12V). Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 INPUT AND ESD PROTECTION +VS The THS6204 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices and are reflected in the absolute maximum ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 90. Internal Circuitry External Pin These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the THS6204), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. -VS Figure 90. Internal ESD Protection Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2008) to Revision C ..................................................................................................... Page • • • • • • • • • • • Added TSSOP package operating junction temperature row to Absolute Maximum Ratings table...................................... 2 Added TSSOP package operating junction temperature row to Recommended Operating Conditions table ...................... 3 Changed footnote 2 of Pin Configurations............................................................................................................................. 3 Updated Figure 13 ............................................................................................................................................................... 11 Updated Figure 14 ............................................................................................................................................................... 12 Updated Figure 18 ............................................................................................................................................................... 12 Updated Figure 31 ............................................................................................................................................................... 14 Updated Figure 43 ............................................................................................................................................................... 16 Updated Figure 55 ............................................................................................................................................................... 18 Updated Figure 68 ............................................................................................................................................................... 21 Updated Figure 80 ............................................................................................................................................................... 23 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): THS6204 33 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS6204IPWP ACTIVE HTSSOP PWP 24 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6204 THS6204IRHFR ACTIVE VQFN RHF 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6204 THS6204IRHFT ACTIVE VQFN RHF 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6204 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of