THS7368IPW

THS7368 www.ti.com SBOS497 – DECEMBER 2009 6-Channel Video Amplifier with 3-SD and 3-SD/ED/HD/Full-HD Filters and 6-dB Gain Check for Samples: THS7368 FEATURES DESCRIPTION • Three SDTV Video Amplifiers for CVBS, S-Video, Y’/P’B/P’R, 480i/576i, Y’U’V’, or G'B'R' • Three SD/ED/HD/Full-HD Selectable Filters for Y’/P’B/P’R, G’B’R’, or Computer RGB • Bypassable Sixth-Order Low-Pass Filters: – Fixed SD Channels: 9.5-MHz – Selectable Channels: 9.5-MHz/18-MHz/36-MHz/72-MHz • Versatile Input Biasing: – DC-Coupled with 300-mV Output Shift – AC-Coupled with Sync-Tip Clamp or Bias • Built-in 6-dB Gain (2 V/V) • +2.7-V to +5-V Single-Supply Operation • Rail-to-Rail Output: – Output Swings Within 100 mV from the Rails: Allows AC or DC Output Coupling – Supports Driving Two Video Lines/Channel • Low Total Quiescent Current: 23.4 mA at 3.3 V • Disabled Supply Current Function: 0.1 μA • Low Differential Gain/Phase: 0.2%/0.35° Fabricated using the revolutionary, complementary Silicon-Germanium (SiGe) BiCom3X process, the THS7368 is a low-power, single-supply, 2.7-V to 5-V, six-channel integrated video buffer. It incorporates three SDTV filters and three selectable SD/ED/HD/Full-HD (also known as True-HD) HDTV filters. All filters feature bypassable sixth-order Butterworth characteristics that are useful as digital-to-analog converter (DAC) reconstruction filters or as analog-to-digital converter (ADC) anti-aliasing filters. 1 2345 APPLICATIONS • • • Set Top Box Output Video Buffering PVR/DVDR Output Buffering BluRay™ Output Video Buffer The THS7368 has flexible input coupling capabilities that can be configured for either ac- or dc-coupled inputs. The 300-mV output level shift allows for a full sync dynamic range at the output with 0-V input. The ac-coupled modes include a transparent sync-tip clamp for CVBS, Y', and G'B'R' signals. AC-coupled biasing for C'/P'B/P'R channels can easily be achieved by adding an external resistor to VS+. The THS7368 is an ideal choice for all video buffer applications. Its rail-to-rail output stage with 6-dB gain allows for both ac and dc line driving. The ability to drive two lines, or 75-Ω loads, allows for maximum flexibility as a video line driver. The 23.4-mA total quiescent current at 3.3 V and 0.1 μA (disabled mode) makes it a good choice for systems that must meet power-sensitive Energy Star® standards. The THS7368 is available in a TSSOP-20 package that is lead-free and green (RoHS-compliant). THS7368 CVBS 75 W CVBS SOC/DAC/Encoder R S-Video C’ SD1 IN SD1 OUT 20 2 SD2 IN SD2 OUT 19 3 SD3 IN SD3 OUT 18 Disable SD 17 S-Video Y' Out R S-Video Y’ 1 Filter 2 4 Filter 2 +2.7 V to +5 V 5 VS+ Filter 1 6 Filter 1 Disable SF 15 7 SF1 IN SF1 OUT 14 8 SF2 IN SF2 OUT 13 9 SF3 IN SF3 OUT 12 10 Bypass SD R 75 W 75 W S-Video C' Out Disable SD 75 W 75 W GND 16 75 W Disable SF Y'/G' Out 75 W Y'/G' R P'B/B' Bypass SF 11 P'R/R' Out Bypass SD LPF Bypass SF LPF 75 W 75 W 75 W R P'R/R' P'B/B' Out 75 W 75 W R Figure 1. Single-Supply, DC-Input/DC-Output Coupled Video Line Driver 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BluRay is a trademark of Blu-ray Disc Association (BDA). Energy Star is a registered trademark of Energy Star. Macrovision is a registered trademark of Macrovision Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated THS7368 SBOS497 – DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD THS7368IPW (1) (2) TRANSPORT MEDIA, QUANTITY Rails, 70 TSSOP-20 THS7368IPWR (2) Tape and Reel, 2000 ECO STATUS (2) Pb-Free, Green For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content can be accessed at www.ti.com/leadfree. GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage, VS+ to GND Input voltage, VI Output current, IO Continuous power dissipation (2) , TJ –0.4 to VS+ V ±90 mA °C +125 °C –60 to +150 °C Human body model (HBM) 4000 V Charge device model (CDM) 1000 V Machine model (MM) 200 V Storage temperature range, TSTG (2) (3) V +150 Maximum junction temperature, continuous operation, long-term reliability (3), TJ (1) UNIT 5.5 See the Dissipation Ratings Table Maximum junction temperature, any condition ESD rating: THS7368 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATINGS (1) PACKAGE θJC (°C/W) θJA (°C/W) AT TA ≤ +25°C POWER RATING AT TA = +85°C POWER RATING TSSOP-20 (PW) 32.3 83 (1) 1.2 W 0.48 W These data were taken with the JEDEC High-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the θJA is 130°C/W. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage, VS+ 2.7 5 V Ambient temperature, TA –40 +85 °C 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 6.6 8.2 10 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 8 9.5 11 MHz B –3 dB; VO = 0.2 VPP 85 150 MHz B Bypass mode; VO = 2 VPP 75 125 V/μs B –0.9 0.2 dB B 42 54 dB B f = 100 kHz 74 ns C f = 5.1 MHz with respect to 100 kHz 10.5 ns C 0.3 ns C PARAMETER AC PERFORMANCE (SD CHANNELS) Bypass mode bandwidth Slew rate With respect to 500 kHz Attenuation (2) , f = 6.75 MHz With respect to 500 kHz (2), f = 27 MHz Group delay Group delay variation Channel-to-channel delay 1.2 Differential gain NTSC/PAL 0.2/0.35 % C Differential phase NTSC/PAL 0.35/0.5 Degrees C Total harmonic distortion Signal-to-noise ratio Gain f = 1 MHz, VO = 1.4 VPP –69 dB C 100 kHz to 6 MHz, non-weighted 70 dB C 100 kHz to 6 MHz, unified weighting 78 dB C 6.3 dB A 6.35 dB B Ω C All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 f = 6.75 MHz, Filter mode Output impedance Return loss Crosstalk AC PERFORMANCE (SF (3) 6 0.7 f = 6.75 MHz, Bypass mode 0.6 Ω C Disabled 20 || 3 kΩ || pF C f = 6.75 MHz, Filter mode 46 dB C f = 1 MHz, SD to SD channels –70 dB C CHANNELS, SD FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 6.6 8.2 9.6 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 7.8 9.5 11 MHz B –0.9 0.2 1.2 dB B 42 50 dB B f = 100 kHz 62 ns C f = 5.1 MHz with respect to 100 kHz 10.5 ns C 0.3 ns C f = 1 MHz, VO = 1.4 VPP –54 dB C 100 kHz to 6 MHz, non-weighted 65 dB C Attenuation With respect to 500 kHz , f = 6.75 MHz With respect to 500 kHz (2), f = 27 MHz Group delay Group delay variation (2) Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain 100 kHz to 6 MHz, unified weighting 75 All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 dB C 6.3 dB A 6.35 dB B Output impedance f = 6.75 MHz 0.7 Ω C Return loss f = 6.75 MHz 46 dB C f = 1 MHz, SF to SD channels –69 dB C f = 1 MHz, SD to SF channels –70 dB C f = 1 MHz, SF to SF channels –66 dB C Crosstalk (1) (2) (3) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation only. (C) Typical value only for information. 3.3-V supply filter specifications are ensured by 100% testing at 5-V supply along with design and characterization. SF indicates selectable filter. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 3 THS7368 SBOS497 – DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V (continued) At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) AC PERFORMANCE (SF CHANNELS, ED FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 11 16 18.5 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 15 18 21 MHz B , f = 11 MHz –1 –0.2 1 dB B With respect to 500 kHz (4), f = 54 MHz 42 54 dB B 36 ns C Attenuation With respect to 500 kHz Group delay (4) f = 100 kHz Group delay variation f = 11 MHz with respect to 100 kHz 9 ns C 0.3 ns C f = 5 MHz, VO = 1.4 VPP –47 dB C 100 kHz to 12 MHz, non-weighted 64.5 dB C 100 kHz to 12 MHz, unified weighting 73.5 dB C 6.3 dB A 6.35 dB B Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 Output impedance f = 12 MHz 0.7 Ω C Return loss f = 12 MHz 46 dB C f = 10 MHz, SF to SD channels –66 dB C f = 10 MHz, SD to SF channels –66 dB C f = 10 MHz, SF to SF channels –49 dB C Crosstalk AC PERFORMANCE (SF CHANNELS, HD FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 26 29 33 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 30 36 40 MHz B With respect to 500 kHz (4), f = 27 MHz –0.5 0.7 2 dB B With respect to 500 kHz (4), f = 74 MHz 33 40 dB B f = 100 kHz 20 ns C f = 27 MHz with respect to 100 kHz 7.5 ns C 0.3 ns C Attenuation Group delay Group delay variation Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio f = 10 MHz, VO = 1.4 VPP –50 dB C 100 kHz to 30 MHz, non-weighted 61.5 dB C 100 kHz to 30 MHz, unified weighting 71.5 dB C 6.3 dB A 6.35 dB B Gain All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 Output impedance f = 30 MHz 1 Ω C Return loss f = 30 MHz 43 dB C f = 25 MHz, SF to SD channels –56 dB C f = 25 MHz, SD to SF channels –70 dB C f = 25 MHz, SF to SF channels –40 dB C Crosstalk (4) 4 3.3-V supply filter specifications are ensured by 100% testing at 5-V supply along with design and characterization. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V (continued) At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) AC PERFORMANCE (SF CHANNELS, FULL-HD/TRUE-HD FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 53 58 66 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 60 72 83 MHz B –0.5 0.7 2 dB B 33 40 dB B 11.5 ns C Attenuation With respect to 500 kHz , f = 54 MHz With respect to 500 kHz (5), f = 148 MHz Group delay Group delay variation (5) f = 100 kHz f = 54 MHz with respect to 100 kHz 4 ns C 0.3 ns C f = 20 MHz, VO = 1.4 VPP –57 dB C 100 kHz to 60 MHz, non-weighted 60 dB C Unified weighting 70 dB C 6.3 dB A 6.35 dB B Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 Output impedance f = 60 MHz 1.5 Ω C Return loss f = 60 MHz 40 dB C f = 50 MHz, SF to SD channels –63 dB C f = 50 MHz, SD to SF channels –68 dB C f = 50 MHz, SF to SF channels –50 dB C Crosstalk AC PERFORMANCE (SF CHANNELS, BYPASS) Passband bandwidth –1 dB; VO = 0.2 VPP 190 275 MHz B Small-signal bandwidth –3 dB; VO = 0.2 VPP 260 350 MHz B VO = 0.2 VPP 450 600 V/µs B f = 100 kHz 2.4 ns C 0.3 ns C f = 20 MHz, VO = 1.4 VPP –67 dB C 100 kHz to 100 MHz, non-weighted 60 dB C Slew rate Group delay Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain 100 kHz to 100 MHz, unified weighting 5.7 All channels, TA = –40°C to +85°C 5.65 dB C 6.3 dB B 6.35 dB B 3 Ω C Disabled 2 || 3 kΩ || pF C f = 100 MHz 34 dB C f = 50 MHz, SF to SD channels –50 dB C f = 50 MHz, SD to SF channels –66 dB C f = 50 MHz, SF to SF channels –50 dB C Return loss (5) 6 f = 100 MHz Output impedance Crosstalk 70 All channels, TA = +25°C 3.3-V supply filter specifications are ensured by 100% testing at 5-V supply along with design and characterization. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 5 THS7368 SBOS497 – DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V (continued) At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) VIN = 0 V, SD channels 200 305 400 mV A VIN = 0 V, SF channels 200 300 400 mV A DC PERFORMANCE Biased output voltage Input voltage range DC input, limited by output Sync-tip clamp charge current –0.1/1.46 V C VIN = –0.1 V, SD channels 140 200 μA A VIN = –0.1 V, SF channels 280 400 μA A 800 || 2 kΩ || pF C 3.15 V C 3.1 V A 3.1 V C Input impedance OUTPUT CHARACTERISTICS RL = 150 Ω to +1.65 V RL = 150 Ω to GND High output voltage swing 2.85 RL = 75 Ω to +1.65 V RL = 75 Ω to GND 3 V C RL = 150 Ω to +1.65 V (VIN = –0.2 V) 0.06 V C RL = 150 Ω to GND (VIN = –0.2 V) 0.05 V A RL = 75 Ω to +1.65 V (VIN = –0.2 V) 0.1 V C RL = 75 Ω to GND (VIN = –0.2 V) 0.05 V C Output current (sourcing) RL = 10 Ω to +1.65 V 80 mA C Output current (sinking) RL = 10 Ω to +1.65 V 70 mA C Low output voltage swing 0.12 POWER SUPPLY Operating voltage Total quiescent current, no load 2.6 3.3 5.5 V B VIN = 0 V, all channels on 18.8 23.4 28.5 mA A VIN = 0 V, SD channels on, SF channels off 5.6 6.9 9 mA A VIN = 0 V, SD channels off, SF channels on 13.2 16.5 19.5 mA A VIN = 0 V, all channels off, VDISABLE = 3 V 0.1 10 μA A At dc 52 dB C V A Power-supply rejection ratio (PSRR) LOGIC CHARACTERISTICS (6) VIH Disabled or Bypass engaged VIL Enabled or Bypass disengaged 1.6 0.75 1.4 IIH Applied voltage = 3.3 V IIL Applied voltage = 0 V 0.6 V A 1 μA C 1 μA C Disable time 150 ns C Enable time 150 ns C Bypass/filter switch time 15 ns C (6) The logic input pins default to a logic '0' condition when left floating. Table 1. TRUTH TABLE: VS+ = +3.3 V (1) (1) (2) 6 FILTER 1 FILTER 2 BYPASS SF (2) 0 0 0 Selects the standard definition filter (9.5 MHz) for the SF channels 0 1 0 Selects the enhanced definition filter (18 MHz) for the SF channels 1 0 0 Selects the high definition filter (36 MHz) for the SF channels 1 1 0 Selects the full/true high-definition filter (72 MHz) for the SF channels X X 1 Bypasses the filters for the SF channels DESCRIPTION The logic input pins default to a logic '0' condition when left floating. SF indicates selectable filter. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 ELECTRICAL CHARACTERISTICS: VS+ = +5 V At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 6.6 8.2 10.2 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 8 9.5 11.3 MHz B –3 dB; VO = 0.2 VPP 85 150 MHz B Bypass mode; VO = 2 VPP 75 125 V/μs B With respect to 500 kHz, f = 6.75 MHz –0.9 0.25 dB A With respect to 500 kHz, f = 27 MHz 42 54 dB A f = 100 kHz 74 ns C f = 5.1 MHz with respect to 100 kHz 10.5 ns C 0.3 ns C PARAMETER AC PERFORMANCE (SD CHANNELS) Bypass mode bandwidth Slew rate Attenuation Group delay Group delay variation Channel-to-channel delay 1.2 Differential gain NTSC/PAL 0.2/0.35 % C Differential phase NTSC/PAL 0.35/0.5 Degrees C Total harmonic distortion Signal-to-noise ratio Gain f = 1 MHz, VO = 1.4 VPP –71 dB C 100 kHz to 6 MHz, non-weighted 70 dB C 100 kHz to 6 MHz, unified weighting 78 dB C 6.3 dB A 6.35 dB B Ω C All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 f = 6.75 MHz, Filter mode Output impedance Return loss Crosstalk AC PERFORMANCE (SF (2) 6 0.7 f = 6.75 MHz, Bypass mode 0.6 Ω C Disabled 20 || 3 kΩ || pF C f = 6.75 MHz, Filter mode 46 dB C f = 1 MHz, SD to SD channels –70 dB C CHANNELS, SD FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 6.6 8.2 9.6 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 7.8 9.5 11 MHz B With respect to 500 kHz, f = 6.75 MHz –0.9 0.2 1.2 dB A With respect to 500 kHz, f = 27 MHz 42 50 dB A f = 100 kHz 62 ns C f = 5.1 MHz with respect to 100 kHz 10.5 ns C 0.3 ns C f = 1 MHz, VO = 1.4 VPP –56 dB C 100 kHz to 6 MHz, non-weighted 65 dB C Attenuation Group delay Group delay variation Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain 100 kHz to 6 MHz, unified weighting 75 All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 dB C 6.3 dB A 6.35 dB B Output impedance f = 6.75 MHz 0.7 Ω C Return loss f = 6.75MHz 46 dB C f = 1 MHz, SF to SD channels –70 dB C f = 1 MHz, SD to SF channels –70 dB C f = 1 MHz, SF to SF channels –66 dB C Crosstalk (1) (2) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation only. (C) Typical value only for information. SF indicates selectable filter. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 7 THS7368 SBOS497 – DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ = +5 V (continued) At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) AC PERFORMANCE (SF CHANNELS, ED FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 11 16 18.5 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 15 18 21 MHz B With respect to 500 kHz, f = 11 MHz –1 –0.2 1 dB A With respect to 500 kHz, f = 54 MHz 42 54 dB A 36 ns C Attenuation Group delay f = 100 kHz Group delay variation f = 11 MHz with respect to 100 kHz 9 ns C 0.3 ns C f = 5 MHz, VO = 1.4 VPP –49 dB C 100 kHz to 12 MHz, non-weighted 64.5 dB C 100 kHz to 12 MHz, unified weighting 73.5 dB C 6.3 dB A 6.35 dB B Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 Output impedance f = 12 MHz 0.7 Ω C Return loss f = 12 MHz 46 dB C f = 10 MHz, SF to SD channels –50 dB C f = 10 MHz, SD to SF channels –66 dB C f = 10 MHz, SF to SF channels –50 dB C Crosstalk AC PERFORMANCE (SF CHANNELS, HD FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 26 30 33 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 30 36 40 MHz B With respect to 500 kHz, f = 27 MHz –0.5 0.5 2 dB A With respect to 500 kHz, f = 74 MHz 33 40 dB A f = 100 kHz 20 ns C f = 27MHz with respect to 100 kHz 7.5 ns C 0.3 ns C Attenuation Group delay Group delay variation Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio f = 10 MHz, VO = 1.4 VPP –52 dB C 100 kHz to 30 MHz, non-weighted 61.5 dB C 100 kHz to 30 MHz, unified weighting 71.5 dB C 6.3 dB A 6.35 dB B Gain All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 Output impedance f = 30 MHz 1 Ω C Return loss f = 30 MHz 43 dB C f = 25 MHz, SF to SD channels –55 dB C f = 25 MHz, SD to SF channels –70 dB C f = 25 MHz, SF to SF channels –40 dB C Crosstalk 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 ELECTRICAL CHARACTERISTICS: VS+ = +5 V (continued) At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) AC PERFORMANCE (SF CHANNELS, FULL/TRUE-HD FILTER) Passband bandwidth –1 dB; VO = 0.2 VPP and 2 VPP 53 60 66 MHz B Small- and large-signal bandwidth –3 dB; VO = 0.2 VPP and 2 VPP 60 72 83 MHz B With respect to 500 kHz, f = 54 MHz –0.5 0.5 2 dB A With respect to 500 kHz, f = 148 MHz 33 40 dB A 11 ns C Attenuation Group delay Group delay variation f = 100 kHz f = 54 MHz with respect to 100 kHz 4 ns C 0.3 ns C f = 20 MHz, VO = 1.4 VPP –57 dB C 100 kHz to 60 MHz, non-weighted 60 dB C Unified weighting 70 dB C 6.3 dB A 6.35 dB B Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain All channels, TA = +25°C 5.7 All channels, TA = –40°C to +85°C 5.65 6 Output impedance f = 60 MHz 1.5 Ω C Return loss f = 60 MHz 40 dB C f = 50 MHz, SF to SD channels –63 dB C f = 50 MHz, SD to SF channels –68 dB C f = 50 MHz, SF to SF channels –50 dB C Crosstalk AC PERFORMANCE (SF CHANNELS, BYPASS) Passband bandwidth –1 dB; VO = 0.2 VPP 190 300 MHz B Small-signal bandwidth –3 dB; VO = 0.2 VPP 260 375 MHz B Slew rate VO = 2 VPP 460 600 V/µs B Group delay f = 100 kHz 2.4 ns C 0.3 ns C f = 20 MHz, VO = 1.4 VPP –68 dB C 100 kHz to 100 MHz, non-weighted 60 dB C Channel-to-channel delay Total harmonic distortion Signal-to-noise ratio Gain 100 kHz to 100 MHz, unified weighting 5.7 All channels, TA = –40°C to +85°C 5.65 6 dB C 6.3 dB B 6.35 dB B f = 100 MHz 3 Ω C Disabled 2 || 3 kΩ || pF C f = 100 MHz 34 dB C f = 50 MHz, SF to SD channels –50 dB C f = 50 MHz, SD to SF channels –66 dB C f = 50 MHz, SF to SF channels –40 dB C Output impedance Return loss Crosstalk 70 All channels, TA = +25°C Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 9 THS7368 SBOS497 – DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ = +5 V (continued) At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted. THS7368 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TEST LEVEL (1) VIN = 0 V, SD channels 200 305 400 mV A VIN = 0 V, SF channels 200 300 400 mV A DC PERFORMANCE Biased output voltage Input voltage range DC input, limited by output Sync-tip clamp charge current –0.1/2.3 V C VIN = –0.1 V, SD channels 140 200 μA A VIN = –0.1 V, SF channels 280 400 μA A 800 || 2 kΩ || pF C 4.85 V C 4.75 V A 4.7 V C Input impedance OUTPUT CHARACTERISTICS RL = 150 Ω to +2.5 V RL = 150 Ω to GND High output voltage swing 4.4 RL = 75 Ω to +2.5V RL = 75 Ω to GND 4.5 V C RL = 150 Ω to +2.5 V (VIN = –0.2 V) 0.06 V C RL = 150 Ω to GND (VIN = –0.2 V) 0.05 V A RL = 75 Ω to +2.5 V (VIN = –0.2 V) 0.1 V C RL = 75 Ω to GND (VIN = –0.2 V) 0.05 V C Output current (sourcing) RL = 10 Ω to +2.5 V 90 mA C Output current (sinking) RL = 10 Ω to +2.5 V 85 mA C Low output voltage swing 0.12 POWER SUPPLY Operating voltage Total quiescent current, no load 2.6 5 5.5 V B VIN = 0 V, all channels on 19.7 24.5 30.2 mA A VIN = 0 V, SD channels on, SF channels off 6 7.2 9.5 mA A VIN = 0 V, SD channels off, SF channels on 13.7 17.3 20.7 mA A VIN = 0 V, all channels off, VDISABLE = 3 V 1 10 μA A At dc 52 dB C V A Power-supply rejection ratio (PSRR) LOGIC CHARACTERISTICS (3) VIH Disabled or Bypass engaged VIL Enabled or Bypass disengaged 2.1 1.9 1.2 IIH Applied voltage = 3.3 V IIL Applied voltage = 0 V 1 V A 1 μA C 1 μA C Disable time 100 ns C Enable time 100 ns C Bypass/filter switch time 10 ns C (3) The logic input pins default to a logic '0' condition when left floating. Table 2. TRUTH TABLE: VS+ = +5 V (1) (1) (2) 10 FILTER 1 FILTER 2 BYPASS SF (2) 0 0 0 Selects the standard definition filter (9.5 MHz) for the SF channels 0 1 0 Selects the enhanced definition filter (18 MHz) for the SF channels 1 0 0 Selects the high definition filter (36 MHz) for the SF channels 1 1 0 Selects the full/true high-definition filter (72 MHz) for the SF channels X X 1 Bypasses the filters for the SF channels DESCRIPTION The logic input pins default to a logic '0' condition when left floating. SF indicates selectable filter. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 PIN CONFIGURATION PW PACKAGE TSSOP-20 (TOP VIEW) SD1 IN 1 20 SD1 OUT SD2 IN 2 19 SD2 OUT SD3 IN 3 18 SD3 OUT Filter 2 4 17 Disable SD VS+ 5 16 GND Filter 1 6 15 Disable SF SF1 IN 7 14 SF1 OUT SF2 IN 8 13 SF2 OUT SF3 IN 9 12 SF3 OUT Bypass SD 10 11 Bypass SF NOTE: NC = No connection. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O SD1 IN 1 I Standard-definition video input, channel 1; LPF = 9.5 MHz SD2 IN 2 I Standard-definition video input, channel 2; LPF = 9.5 MHz SD3 IN 3 I Standard-definition video input, channel 3; LPF = 9.5 MHz Filter 2 4 I Used in conjunction with Filter 1 for selecting the LPF on SF channels VS+ 5 I Positive power-supply pin; connect to +2.7 V up to +5 V Filter 1 6 I Used in conjunction with Filter 2 for selecting the LPF on SF channels SF1 IN 7 I Component or RGB video input, channel 1 SF2 IN 8 I Component or RGB video input, channel 2 SF3 IN 9 I Component or RGB video input, channel 3 Bypass SD 10 I Bypass all SD channel filters. Logic high bypasses the internal filters and logic low engages the internal filters. Bypass SF 11 I Bypass all SF channel filters. Logic high bypasses the internal filters and logic low engages the internal filters. SF3 OUT (1) 12 O Component or RGB video output, channel 3 SF2 OUT 13 O Component or RGB video output, channel 2 SF1 OUT 14 O Component or RGB video output, channel 1 Disable SF 15 I Disable selectable filter channels. Logic high disables the SF channels and logic low enables the SF channels. GND 16 I Ground pin for all internal circuitry Disable SD 17 I Disable standard definition channels. Logic high disables the SD channels and logic low enables the SD channels. SD3 OUT 18 O Standard-definition video output, channel 3; LPF = 9.5 MHz SD2 OUT 19 O Standard-definition video output, channel 2; LPF = 9.5 MHz SD1 OUT 20 O Standard-definition video output, channel 1; LPF = 9.5 MHz (1) DESCRIPTION SF indicates selectable filter. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 11 THS7368 SBOS497 – DECEMBER 2009 www.ti.com FUNCTIONAL BLOCK DIAGRAM +VS gm SD Channel 1 Input (CVBS) Level Shift LPF Sync-Tip Clamp (DC Restore) 800 kW Bypass SD 6 dB SD Channel 1 Output (CVBS) 6 dB SD Channel 2 Output (S-Video Y) 6 dB SD Channel 3 Output (S-Video C) 6-Pole 9.5 MHz +VS gm SD Channel 2 Input (S-Video Y) Level Shift LPF Sync-Tip Clamp (DC Restore) 800 kW Bypass SD 6-Pole 9.5 MHz +VS gm SD Channel 3 Input (S-Video C) Level Shift LPF Sync-Tip Clamp (DC Restore) 800 kW Bypass SD 6-Pole 9.5 MHz Bypass SD Disable SD +VS Bypass SF Disable SF gm SD/ED/HD/Full-HD Channel 1 Input (Y’) Level Shift LPF Sync-Tip Clamp (DC Restore) 800 kW Bypass SF 6 dB SD/ED/HD/Full-HD Channel 1 Output (Y’) 6 dB SD/ED/HD/Full-HD Channel 2 Output (P’B) 6 dB SD/ED/HD/Full-HD Channel 3 Output (P’R) 6-Pole 9.5/18/36/72 MHz +VS gm SD/ED/HD/Full-HD Channel 2 Input (P’B) Level Shift LPF Sync-Tip Clamp (DC Restore) 800 kW Bypass SF 6-Pole 9.5/18/36/72 MHz +VS gm SD/ED/HD/Full-HD Channel 3 Input (P’R) 800 kW Sync-Tip Clamp (DC Restore) +3 V to +5 V Level Shift Bypass SF LPF 6-Pole 9.5/18/36/72 MHz Filter Selection (1) SF indicates selectable filter. 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 TYPICAL CHARACTERISTICS Table 3. Table of Graphs: 3.3 V, Standard-Definition (SD) Channels TITLE FIGURE SD Channels Small-Signal Gain vs Frequency Response Figure 2, Figure 3, Figure 6, Figure 7 SD Channels Large-Signal Gain vs Frequency Response Figure 4, Figure 5 SD Channels Phase vs Frequency Response Figure 8 SD Channels Group Delay vs Frequency Response Figure 9 SD Channels Second-Order Harmonic Distortion vs Frequency Figure 10, Figure 12 SD Channels Third-Order Harmonic Distortion vs Frequency Figure 11, Figure 13 Table 4. Table of Graphs: 5 V, Standard-Definition (SD) Channels TITLE FIGURE SD Channels Small-Signal Gain vs Frequency Response Figure 19, Figure 20, Figure 23, Figure 24 SD Channels Large-Signal Gain vs Frequency Response Figure 21, Figure 22 SD Channels Phase vs Frequency Response Figure 25 SD Channels Group Delay vs Frequency Response Figure 26 SD Channels Second-Order Harmonic Distortion vs Frequency Figure 27, Figure 29 SD Channels Third-Order Harmonic Distortion vs Frequency Figure 28, Figure 30 Table 5. Table of Graphs: 3.3 V, Selectable Filter (SF) Channels TITLE FIGURE SF Channels Small-Signal Gain vs Frequency Response Figure 14, Figure 15 SF Channels Phase vs Frequency Response Figure 16 SF Channels Group Delay vs Frequency Response Figure 17, Figure 18 Table 6. Table of Graphs: 5 V, Selectable Filter (SF) Channels TITLE FIGURE SF Channels Small-Signal Gain vs Frequency Response SF Channels Phase vs Frequency Response Figure 31, Figure 32 Figure 33 SF Channels Group Delay vs Frequency Response Figure 34, Figure 35 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 13 THS7368 SBOS497 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted. SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 10 SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 6.5 RL = 150 W Small-Signal Gain (dB) Small-Signal Gain (dB) RL = 75 W -10 Bypass Mode -20 Filter Mode -30 -40 -50 Bypass Mode 6.0 0 RL = 150 W VS = +3.3 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP -60 100 k 10 M 100 M Filter Mode RL = 75 W 4.5 RL = 75 W and 150 W 4.0 3.5 VS = +3.3 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP 2.5 100 k 1G 1M 10 M Figure 3. SD CHANNELS LARGE-SIGNAL GAIN vs FREQUENCY RESPONSE SD CHANNELS LARGE-SIGNAL GAIN vs FREQUENCY RESPONSE 6.5 0 Bypass Mode VO = 1 VPP VO = 2 VPP VO = 2 VPP VO = 0.2 VPP VO = 0.2 VPP -10 -20 -30 Filter Mode -40 -50 VS = +3.3 V Load = 150 W || 10 pF DC-Coupled Output -60 100 k 1M 100 M VO = 1 VPP VO = 2 VPP VO = 2 VPP VO = 0.2 VPP VO = 0.2 VPP 5.5 5.0 4.5 4.0 Filter Mode 3.5 3.0 10 M Bypass Mode 6.0 Large-Signal Gain (dB) Large-Signal Gain (dB) 1G Figure 2. 10 VS = +3.3 V Load = 150 W || 10 pF DC-Coupled Output 2.5 100 k 1G 1M 10 M 100 M 1G Frequency (Hz) Frequency (Hz) Figure 4. Figure 5. SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 10 Filter Mode AC -20 -30 -50 AC VS = +3.3 V Load = 150 W || 10 pF AC- vs DC-Coupled Output VO = 0.2 VPP -60 100 k 1M 10 M 100 M 6.0 5.5 1G Filter Mode DC 5.0 AC or DC 4.5 4.0 3.5 3.0 DC Bypass Mode AC 6.5 Small-Signal Gain (dB) DC -10 -40 7.0 Bypass Mode 0 Small-Signal Gain (dB) 100 M Frequency (Hz) Frequency (Hz) VS = +3.3 V Load = 150 W || 10 pF AC- vs DC-Coupled Output VO = 0.2 VPP 2.5 100 k 1M 10 M 100 M 1G Frequency (Hz) Frequency (Hz) Figure 6. 14 RL = 150 W 5.0 3.0 RL = 75 W 1M 5.5 Figure 7. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels (continued) With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted. SD CHANNELS PHASE vs FREQUENCY RESPONSE SD CHANNELS GROUP DELAY vs FREQUENCY RESPONSE 120 45 0 -45 Group Delay (ns) Filter Mode -90 Phase (°) 110 RL = 75 W and 150 W Bypass Mode -135 RL = 75 W and 150 W -180 -225 VS = +3.3 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP -270 -315 -360 100 k 1M 100 VS = +3.3 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP 90 80 70 RL = 75 W and 150 W 60 10 M 100 M Filter Mode 50 100 k 1G 1M 10 M 100 M Frequency (Hz) Frequency (Hz) SD CHANNELS SECOND-ORDER HARMONIC DISTORTION vs FREQUENCY SD CHANNELS THIRD-ORDER HARMONIC DISTORTION vs FREQUENCY -30 VS = +3.3 V DC-Coupled Output RL = 150 W || 10 pF -40 Third-Order Harmonic Distortion (dBc) Figure 9. Second-Order Harmonic Distortion (dBc) Figure 8. VO = 2.5 VPP VO = 2 VPP -50 VO = 1.4 VPP -60 VO = 1 VPP -70 -80 VO = 0.5 VPP -90 -30 VS = +3.3 V DC-Coupled Output RL = 150 W || 10 pF -40 VO = 2.5 VPP -50 VO = 2 VPP -60 -70 VO = 1.4 VPP -80 -90 VO = 1 VPP VO = 0.5 VPP -100 1 1 7 7 Frequency (MHz) Frequency (MHz) SD CHANNELS SECOND-ORDER HARMONIC DISTORTION vs FREQUENCY SD CHANNELS THIRD-ORDER HARMONIC DISTORTION vs FREQUENCY -30 VS = +3.3 V Filter Bypass DC-Coupled Output RL = 150 W || 5 pF -40 Third-Order Harmonic Distortion (dBc) Figure 11. Second-Order Harmonic Distortion (dBc) Figure 10. VO = 2.5 VPP -50 -60 VO = 0.5 VPP VO = 2 VPP -70 VO = 1 VPP -80 VO = 1.4 VPP -90 1 -30 VS = +3.3 V Filter Bypass DC-Coupled Output RL = 150 W || 5 pF -40 -50 VO = 0.5 VPP -60 VO = 1 VPP -70 VO = 2.5 VPP VO = 1.4 VPP -80 VO = 2 VPP -90 -100 10 60 1 Frequency (MHz) 10 60 Frequency (Hz) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 15 THS7368 SBOS497 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: 3.3 V, Selectable Filter (SF) Channels With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted. SF CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 10 6.5 0 6.0 Bypass SD Filter Small-Signal Gain (dB) Small-Signal Gain (dB) SF CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE -10 Full-HD Filter -20 ED Filter HD Filter -30 -40 VS = +3.3 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP -50 -60 1M 5.5 ED Filter 4.5 4.0 3.5 2.5 100 M Full-HD Filter SD Filter 5.0 3.0 10 M Bypass 1M 1G HD Filter VS = +3.3 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 10 M 1G Figure 14. Figure 15. SF CHANNELS PHASE vs FREQUENCY RESPONSE SF CHANNELS GROUP DELAY vs FREQUENCY RESPONSE 45 100 0 90 Full-HD Filter -45 ED Filter -180 -225 -270 -315 -360 Bypass SD Filter -135 Group Delay (ns) 80 -90 Phase (°) 100 M Frequency (Hz) Frequency (Hz) HD Filter VS = +3.3 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 1M VS = +3.3 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 70 60 SD Filter 50 40 30 10 M 100 M ED Filter 20 100 k 1G 1M 10 M 100 M Frequency (Hz) Frequency (Hz) Figure 16. Figure 17. SF CHANNELS GROUP DELAY vs FREQUENCY RESPONSE 35 Group Delay (ns) 30 25 VS = +3.3 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 20 HD Filter 15 10 Full-HD Filter 5 1 10 100 Frequency (MHz) Figure 18. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted. SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 10 SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 6.5 RL = 150 W Bypass Mode -20 -30 RL = 150 W -50 VS = +5 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP -60 100 k 10 M 100 M 5.5 5.0 4.0 3.5 VS = +5 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP 2.5 100 k 1G 1M 10 M 1G Figure 19. Figure 20. SD CHANNELS LARGE-SIGNAL GAIN vs FREQUENCY RESPONSE SD CHANNELS LARGE-SIGNAL GAIN vs FREQUENCY RESPONSE 10 -20 -30 6.0 Large-Signal Gain (dB) -10 6.5 Bypass Mode VO = 1 VPP VO = 2 VPP VO = 2 VPP VO = 0.2 VPP VO = 0.2 VPP 0 Large-Signal Gain (dB) 100 M Frequency (Hz) Frequency (Hz) Filter Mode -40 -50 VS = +5 V Load = 150 W || 10 pF DC-Coupled Output -60 100 k 1M 5.0 4.5 4.0 3.5 3.0 10 M Filter Mode VS = +5 V Load = 150 W || 10 pF DC-Coupled Output 2.5 100 k 1G 100 M Bypass Mode VO = 1 VPP VO = 2 VPP VO = 2 VPP VO = 0.2 VPP VO = 0.2 VPP 5.5 1M 10 M 100 M 1G Frequency (Hz) Frequency (Hz) Figure 21. Figure 22. SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE SD CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 10 -10 AC Filter Mode -30 -40 -50 DC VS = +5 V Load = 150 W || 10 pF AC- vs DC-Coupled Output VO = 0.2 VPP -60 100 k 1M 10 M 5.0 4.5 4.0 3.5 1G Bypass Mode VO = 1 VPP VO = 2 VPP VO = 2 VPP VO = 0.2 VPP VO = 0.2 VPP 5.5 3.0 AC 100 M 6.0 Large-Signal Gain (dB) DC -20 6.5 Bypass Mode 0 Small-Signal Gain (dB) RL = 75 W RL = 75 W and 150 W 4.5 3.0 RL = 75 W 1M RL = 150 W Filter Mode RL = 75 W Small-Signal Gain (dB) Small-Signal Gain (dB) Filter Mode -10 -40 Bypass Mode 6.0 0 Filter Mode VS = +5 V Load = 150 W || 10 pF DC-Coupled Output 2.5 100 k 1M 10 M 100 M 1G Frequency (Hz) Frequency (Hz) Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 17 THS7368 SBOS497 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels (continued) With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted. SD CHANNELS PHASE vs FREQUENCY RESPONSE SD CHANNELS GROUP DELAY vs FREQUENCY RESPONSE 120 45 RL = 75 W and 150 W 0 110 Phase (°) Bypass Mode Filter Mode -90 -135 RL = 75 W and 150 W -180 -225 VS = +5 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP -270 -315 -360 100 k 1M Group Delay (ns) -45 100 VS = +5 V Load = RL || 10 pF DC-Coupled Output VO = 200 mVPP 90 Filter Mode 80 70 RL = 75 W and 150 W 60 10 M 100 M 50 100 k 1G 1M 10 M 100 M Frequency (Hz) Frequency (Hz) SD CHANNELS SECOND-ORDER HARMONIC DISTORTION vs FREQUENCY SD CHANNELS THIRD-ORDER HARMONIC DISTORTION vs FREQUENCY -30 VS = +5 V DC-Coupled Output RL = 150 W || 10 pF -40 -50 Third-Order Harmonic Distortion (dBc) Figure 26. Second-Order Harmonic Distortion (dBc) Figure 25. VO = 2.5 VPP VO = 2 VPP VO = 1.4 VPP -60 VO = 1 VPP -70 -80 VO = 0.5 VPP -90 -30 VS = +5 V DC-Coupled Output RL = 150 W || 10 pF -40 VO = 2.5 VPP -50 VO = 2 VPP -60 VO = 1.4 VPP VO = 1 VPP -70 -80 -90 VO = 0.5 VPP -100 1 1 7 7 Frequency (MHz) Frequency (MHz) SD CHANNELS SECOND-ORDER HARMONIC DISTORTION vs FREQUENCY SD CHANNELS THIRD-ORDER HARMONIC DISTORTION vs FREQUENCY -30 VS = +5 V Filter Bypass DC-Coupled Output RL = 150 W || 5 pF -40 Third-Order Harmonic Distortion (dBc) Figure 28. Second-Order Harmonic Distortion (dBc) Figure 27. VO = 2.5 VPP -50 -60 VO = 0.5 VPP VO = 2 VPP -70 VO = 1 VPP -80 VO = 1.4 VPP -90 1 -30 VS = +5 V Filter Bypass DC-Coupled Output RL = 150 W || 5 pF -40 -50 VO = 0.5 VPP -60 VO = 1 VPP -70 VO = 2.5 VPP VO = 2 VPP -90 -100 10 60 1 Frequency (MHz) 10 60 Frequency (MHz) Figure 29. 18 VO = 1.4 VPP -80 Figure 30. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 TYPICAL CHARACTERISTICS: 5 V, Selectable Filter (SF) Channels With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted. SF CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE 10 6.5 0 6.0 Bypass SD Filter Small-Signal Gain (dB) Small-Signal Gain (dB) SF CHANNELS SMALL-SIGNAL GAIN vs FREQUENCY RESPONSE -10 Full-HD Filter -20 ED Filter HD Filter -30 -40 VS = +5 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP -50 -60 1M 5.5 ED Filter 4.5 4.0 3.5 2.5 100 M Full-HD Filter SD Filter 5.0 3.0 10 M Bypass 1M 1G HD Filter VS = +5 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 10 M 1G Figure 31. Figure 32. SF CHANNELS PHASE vs FREQUENCY RESPONSE SF CHANNELS GROUP DELAY vs FREQUENCY RESPONSE 45 100 0 90 Full-HD Filter -45 ED Filter -180 -225 -270 -315 -360 Bypass SD Filter -135 Group Delay (ns) 80 -90 Phase (°) 100 M Frequency (Hz) Frequency (Hz) HD Filter VS = +5 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 1M VS = +5 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 70 60 SD Filter 50 40 30 10 M 100 M ED Filter 20 100 k 1G 1M 10 M 100 M Frequency (Hz) Frequency (Hz) Figure 33. Figure 34. SF CHANNELS GROUP DELAY vs FREQUENCY RESPONSE 35 Group Delay (ns) 30 25 VS = +5 V Load = 150 W || 5 pF DC-Coupled Output VO = 200 mVPP 20 HD Filter 15 10 Full-HD Filter 5 1 10 100 Frequency (MHz) Figure 35. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 19 THS7368 SBOS497 – DECEMBER 2009 www.ti.com APPLICATION INFORMATION The THS7368 is targeted for six-channel video output applications that require three standard-definition (SD) video output buffers and three selectable filter (SF) output buffers. Although it can be used for numerous other applications, the needs and requirements of the video signal are the most important design parameters of the THS7368. Built on the revolutionary, complementary Silicon Germanium (SiGe) BiCom3X process, the THS7368 incorporates many features not typically found in integrated video parts while consuming very low power. The THS7368 includes the following features: • Single-supply 2.7-V to 5-V operation with low total quiescent current of 23.4 mA at 3.3 V and 24.5 mA at 5 V • Disable mode allows for shutting down individual SD/SF blocks of amplifiers to save system power in power-sensitive applications • Input configuration accepting dc + level shift, ac sync-tip clamp, or ac-bias – AC-biasing is allowed with the use of external pull-up resistors to the positive power supply • Sixth-order, low-pass filter for DAC reconstruction or ADC image rejection: – 9.5 MHz for NTSC, PAL, SECAM, composite video (CVBS), S-Video Y’/C’, 480i/576i, Y’/P’B/P’R, and G’B’R’ (R’G’B’) signals – Selectable 9.5-MHz/18-MHz/36-MHz/72-MHz for 480i/576i, 480p/576p, 720p/1080i/1080p24/1080p30, or 1080p60 Y’/P’ B/P’R or G’B’R’ signals; also allows up to QXGA (1600 × 1200 at 60 Hz) R'G'B' video • Individually-controlled Bypass mode bypasses the low-pass filters for each SD/SF block of amplifiers – SD bypass mode features 150-MHz and 125-V/μs performance – SF bypass mode features 375-MHz and 600-V/μs performance • Individually-controlled Disable mode shuts down all amplifiers in each SD/SF block to reduce quiescent current to 0.1 μA • Internally-fixed gain of 2-V/V (+6-dB) buffer that can drive two video lines with dc-coupling or traditional ac-coupling • Flow-through configuration using a TSSOP-20 package that complies with the latest lead-free (RoHS-compatible) and green manufacturing requirements OPERATING VOLTAGE The THS7368 is designed to operate from 2.7 V to 5 V over a –40°C to +85°C temperature range. The impact on performance over the entire temperature range is negligible as a result of the implementation 20 of thin film resistors and high-quality, low-temperature coefficient capacitors. The design of the THS7368 allows operation down to 2.6 V, but it is recommended to use at least a 3-V supply to ensure that no issues arise with headroom or clipping with 100% color-saturated CVBS signals. If only 75% color saturated CVBS is supported, then the output voltage requirements are reduced to 2 VPP on the output, allowing a 2.7-V supply to be utilized without issues. A 0.1-μF to 0.01-μF capacitor should be placed as close as possible to the power-supply pins. Failure to do so may result in the THS7368 outputs ringing or oscillating. Additionally, a large capacitor (such as 22 μF to 100 μF) should be placed on the power-supply line to minimize interference with 50-/60-Hz line frequencies. INPUT VOLTAGE The THS7368 input range allows for an input signal range from –0.2 V to approximately (VS+ – 1.5 V). However, because of the internal fixed gain of 2 V/V (+6 dB) and the internal input level shift of 150 mV (typical), the output is generally the limiting factor for the allowable linear input range. For example, with a 5-V supply, the linear input range is from –0.2 V to 3.5 V. However, because of the gain and level shift, the linear output range limits the allowable linear input range to approximately –0.1 V to 2.3 V. INPUT OVERVOLTAGE PROTECTION The THS7368 is built using a very high-speed, complementary, bipolar, and CMOS process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 36. +VS External Input/Output Pin Internal Circuitry Figure 36. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. The protection diodes can typically support 30 mA of continuous current when overdriven. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 TYPICAL CONFIGURATION AND VIDEO TERMINOLOGY departs from true luminance because a nonlinear term, gamma, is added to the true RGB signals to form R’G’B’ signals. These R’G’B’ signals are then used to mathematically create luma (Y’). Thus, luminance (Y) is not maintained, providing a difference in terminology. A typical application circuit using the THS7368 as a video buffer is shown in Figure 37. It shows a DAC or encoder driving the input channels of the THS7368. One channel is a CVBS connection while two other channels are for the S-Video Y’/C’ signals of an SD video system. These signals can be NTSC, PAL, or SECAM signals. The other three channels are the component video Y’/P’B/P’R (sometimes labeled Y’U’V’ or incorrectly labeled Y’/C’B/C’R) signals. These signals are typically 480i, 576i, 480p, 576p, 720p, 1080i, or up to 1080p60 signals. Because the filters can be bypassed, other formats such as R'G'B' video up to QXGA or UWXGA can also be supported with the THS7368. This rationale is also used for the chroma (C’) term. Chroma is derived from the nonlinear R’G’B’ terms and, thus, it is nonlinear. Chominance (C) is derived from linear RGB, giving the difference between chroma (C’) and chrominance (C). The color difference signals (P’B/P’R/U’/V’) are also referenced in this manner to denote the nonlinear (gamma corrected) signals. Note that the Y’ term is used for the luma channels throughout this document rather than the more common luminance (Y) term. This usage accounts for the definition of luminance as stipulated by the International Commission on Illumination (CIE). Video THS7368 CVBS 75 W CVBS R SD1 IN SD1 OUT 20 2 SD2 IN SD2 OUT 19 3 SD3 IN SD3 OUT 18 75 W S-Video Y' Out 75 W S-Video Y’ R SOC/DAC/Encoder 1 +2.7 V to +5 V S-Video C’ R Y'/G' 4 NC Disable SD 17 5 VS+ GND 16 6 NC Disable SF 15 7 SF1 IN SF1 OUT 14 8 SF2 IN SF2 OUT 13 9 SF3 IN SF3 OUT 12 10 Bypass SD Bypass SF 11 Disable SD 75 W Disable SF S-Video C' Out 75 W 75 W Y'/G' Out 75 W R 75 W Bypass SD LPF P'B/B' Bypass SF LPF P'B/B' Out 75 W R 75 W P'R/R' Out P'R/R' 75 W R 75 W (1) SF indicates selectable filter. Figure 37. Typical Six-Channel System Inputs from DC-Coupled Encoder/DAC with DC-Coupled Line Driving Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 21 THS7368 SBOS497 – DECEMBER 2009 www.ti.com R’G’B’ (commonly mislabeled RGB) is also called G’B’R’ (again commonly mislabeled as GBR) in professional video systems. The Society of Motion Picture and Television Engineers (SMPTE) component standard stipulates that the luma information is placed on the first channel, the blue color difference is placed on the second channel, and the red color difference signal is placed on the third channel. This practice is consistent with the Y'/P'B/P'R nomenclature. Because the luma channel (Y') carries the sync information and the green channel (G') also carries the sync information, it makes logical sense that G' be placed first in the system. Because the blue color difference channel (P'B) is next and the red color difference channel (P'R) is last, then it also makes logical sense to place the B' signal on the second channel and the R' signal on the third channel, respectfully. Thus, hardware compatibility is better achieved when using G'B'R' rather than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels, but this configuration may not always be the case in all systems. INPUT MODE OF OPERATION: DC The inputs to the THS7368 allow for both ac- and dc-coupled inputs. Many DACs or video encoders can be dc-connected to the THS7368. One of the drawbacks to dc-coupling is when 0 V is applied to the input. Although the input of the THS7368 allows for a 0-V input signal without issue, the output swing of a traditional amplifier cannot yield a 0-V signal resulting in possible clipping. This limitation is true for any single-supply amplifier because of the characteristics of the output transistors. Neither CMOS nor bipolar transistors can achieve 0 V while sinking current. This transistor characteristic is also the same reason why the highest output voltage is always less than the power-supply voltage when sourcing current. This output clipping can reduce the sync amplitudes (both horizontal and vertical sync) on the video signal. A problem occurs if the video signal receiver uses an automatic gain control (AGC) loop to account for losses in the transmission line. Some video AGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then the AGC circuit can increase the gain too much—resulting in too much luma and/or chroma amplitude gain correction. This correction may result in a picture with an overly bright display with too much color saturation. 22 Other AGC circuits use the chroma burst amplitude for amplitude control; reduction in the sync signals does not alter the proper gain setting. However, it is good engineering design practice to ensure that saturation/clipping does not take place. Transistors always take a finite amount of time to come out of saturation. This saturation could possibly result in timing delays or other aberrations on the signals. To eliminate saturation or clipping problems, the THS7368 has a 150-mV input level shift feature. This feature takes the input voltage and adds an internal +150-mV shift to the signal. Because the THS7368 also has a gain of 6 dB (2 V/V), the resulting output with a 0-V applied input signal is approximately 300 mV. The THS7368 rail-to-rail output stage can create this output level while connected to a typical video load. This configuration ensures that no saturation or clipping of the sync signals occur. This shift is constant, regardless of the input signal. For example, if a 1-V input is applied, the output is 2.3 V. Because the internal gain is fixed at +6 dB, the gain dictates what the allowable linear input voltage range can be without clipping concerns. For example, if the power supply is set to 3 V, the maximum output is approximately 2.9 V while driving a significant amount of current. Thus, to avoid clipping, the allowable input is ([2.9 V/2] – 0.15 V) = 1.3 V. This range is valid for up to the maximum recommended 5-V power supply that allows approximately a ([4.9 V/2] – 0.15 V) = 2.3 V input range while avoiding clipping on the output. The input impedance of the THS7368 in this mode of operation is dictated by the internal, 800-kΩ pull-down resistor, as shown in Figure 38. Note that the internal voltage shift does not appear at the input pin; it only shows at the output pin. +VS Internal Circuitry Input Pin 800 kW Level Shift Figure 38. Equivalent DC Input Mode Circuit Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 INPUT MODE OF OPERATION: AC SYNC TIP CLAMP Some video DACs or encoders are not referenced to ground but rather to the positive power supply. The resulting video signals are generally at too great a voltage for a dc-coupled video buffer to function properly. To account for this scenario, the THS7368 incorporates a sync-tip clamp circuit. This function requires a capacitor (nominally 0.1 μF) to be in series with the input. Although the term sync-tip-clamp is used throughout this document, it should be noted that the THS7368 would probably be better termed as a dc restoration circuit based on how this function is performed. This circuit is an active clamp circuit and not a passive diode clamp function. The input to the THS7368 has an internal control loop that sets the lowest input applied voltage to clamp at ground (0 V). By setting the reference at 0 V, the THS7368 allows a dc-coupled input to also function. Therefore, the sync-tip-clamp (STC) is considered transparent because it does not operate unless the input signal goes below ground. The signal then goes through the same 150-mV level shifter, resulting in an output voltage low level of 300 mV. If the input signal tries to go below 0 V, the THS7368 internal control loop sources up to 6 mA of current to increase the input voltage level on the THS7368 input side of the coupling capacitor. As soon as the voltage goes above the 0-V level, the loop stops sourcing current and becomes very high impedance. As a result of this delay, sync may have an apparent voltage shift. The amount of shift depends on the amount of droop in the signal as dictated by the input capacitor and the STC current flow. Because sync is used primarily for timing purposes with syncing occurring on the edge of the sync signal, this shift is transparent in most systems. +VS Internal Circuitry STC LPF +VS gm Input 0.1 mF Input Pin 800 kW Level Shift Figure 39. Equivalent AC Sync-Tip-Clamp Input Circuit While this feature may not fully eliminate overshoot issues on the input signal, in cases of extreme overshoot and/or ringing, the STC system should help minimize improper clamping levels. As an additional method to help minimize this issue, an external capacitor (for example, 10 pF to 47 pF) to ground in parallel with the external termination resistors can help filter overshoot problems. One of the concerns about the sync-tip-clamp level is how the clamp reacts to a sync edge that has overshoot—common in VCR signals, noise, DAC overshoot, or reflections found in poor printed circuit board (PCB) layouts. Ideally, the STC should not react to the overshoot voltage of the input signal. Otherwise, this response could result in clipping on the rest of the video signal because it may raise the bias voltage too much. It should be noted that this STC system is dynamic and does not rely upon timing in any way. It only depends on the voltage that appears at the input pin at any given point in time. The STC filtering helps minimize level shift problems associated with switching noises or very short spikes on the signal line. This architecture helps ensure a very robust STC system. To help minimize this input signal overshoot problem, the control loop in the THS7368 has an internal low-pass filter, as shown in Figure 39. This filter reduces the response time of the STC circuit. This delay is a function of how far the voltage is below ground, but in general it is approximately a 400-ns delay for the SD channel filters and approximately a 150-ns delay for the SF filters. The effect of this filter is to slow down the response of the control loop so as not to clamp on the input overshoot voltage but rather the flat portion of the sync signal. When the ac STC operation is used, there must also be some finite amount of discharge bias current. As previously described, if the input signal goes below the 0-V clamp level, the internal loop of the THS7368 sources current to increase the voltage appearing at the input pin. As the difference between the signal level and the 0-V reference level increases, the amount of source current increases proportionally—supplying up to 6 mA of current. Thus, the time to re-establish the proper STC voltage can be very fast. If the difference is very small, then the source current is also very small to account for minor voltage droop. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 23 THS7368 SBOS497 – DECEMBER 2009 www.ti.com However, what happens if the input signal goes above the 0-V input level? The problem is the video signal is always above this level and must not be altered in any way. Thus, if the sync level of the input signal is above this 0-V level, then the internal discharge (sink) current reduces the ac-coupled bias signal to the proper 0-V level. This discharge current must not be large enough to alter the video signal appreciably or picture quality issues may arise. This effect is often seen by looking at the tilt (droop) of a constant luma signal being applied and the resulting output level. The associated change in luma level from the beginning and end of the video line is the amount of line tilt (droop). If the discharge current is very small, the amount of tilt is very low, which is a generally a good thing. However, the amount of time for the system to capture the sync signal could be too long. This effect is also termed hum rejection. Hum arises from the ac line voltage frequency of 50 Hz or 60 Hz. The value of the discharge current and the ac-coupling capacitor combine to dictate the hum rejection and the amount of line tilt. To allow for both dc- and ac-coupling in the same part, the THS7368 incorporates an 800-kΩ resistor to ground. Although a true constant current sink is preferred over a resistor, there can be issues when the voltage is near ground. This configuration can cause the current sink transistor to saturate and cause potential problems with the signal. The 800-kΩ resistor is large enough to not impact a dc-coupled DAC termination. For discharging an ac-coupled source, Ohm’s Law is used. If the video signal is 1 V, then there is 1 V/800 kΩ = 1.25-μA of discharge current. If more hum rejection is desired or there is a loss of sync occurring, then simply decrease the 0.1-μF input coupling capacitor. A decrease from 0.1 μF to 0.047 μF increases the hum rejection by a factor of 2.1. Alternatively, an external pull-down resistor to ground may be added that decreases the overall resistance and ultimately increases the discharge current. To ensure proper stability of the ac STC control loop, the source impedance must be less than 1-kΩ with the input capacitor in place. Otherwise, there is a possibility of the control loop ringing, which may appear on the output of the THS7368. Because most DACs or encoders use resistors to establish the voltage, which are typically less than 300-Ω, meeting the less than 1-kΩ requirement is easily done. However, if the source impedance looking from the THS7368 input perspective is very high, then simply adding a 1-kΩ resistor to GND ensures proper operation of the THS7368. 24 INPUT MODE OF OPERATION: AC BIAS Sync-tip clamps work very well for signals that have horizontal and/or vertical syncs associated with them; however, some video signals do not have a sync embedded within the signal. If ac-coupling of these signals is desired, then a dc bias is required to properly set the dc operating point within the THS7368. This function is easily accomplished with the THS7368 by simply adding an external pull-up resistor to the positive power supply, as shown in Figure 40. +3.3 V +3.3 V CIN 0.1 mF Input Internal Circuitry RPU Input Pin 800 kW Level Shift Figure 40. AC-Bias Input Mode Circuit Configuration The dc voltage appearing at the input pin is equal to Equation 1: VDC = VS 800 kW 800 kW + RPU (1) The THS7368 allowable input range is approximately 0 V to (VS+ – 1.5 V), allowing for a very wide input voltage range. As such, the input dc bias point is very flexible, with the output dc bias point being the primary factor. For example, if the output dc bias point is desired to be 1.6 V on a 3.3-V supply, then the input dc bias point should be (1.6 V – 300 mV)/2 = 0.65 V. Thus, the pull-up resistor calculates to approximately 3.3 MΩ, resulting in 0.644 V. If the output dc-bias point is desired to be 1.6 V with a 5-V power supply, then the pull-up resistor calculates to approximately 5.36 MΩ. Keep in mind that the internal 800-kΩ resistor has approximately a ±20% variance. As such, the calculations should take this variance into account. For the 0.644-V example above, using an ideal 3.3-MΩ resistor, the input dc bias voltage is approximately 0.644 V ± 0.1 V. The value of the output bias voltage is very flexible and is left to each individual design. It is important to ensure that the signal does not clip or saturate the video signal. Thus, it is recommended to ensure the output bias voltage is between 0.9 V and (VS+ – 1 V). For 100% color saturated CVBS or signals with Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 Macrovision®, the CVBS signal can reach up to 1.23 VPP at the input, or 2.46 VPP at the output of the THS7368. In contrast, other signals are typically 1 VPP or 0.7 VPP at the input which translate to an output voltage of 2 VPP or 1.4 VPP. The output bias voltage must account for a worst-case situation, depending on the signals involved. One other issue that must be taken into account is the dc-bias point is a function of the power supply. As such, there is an impact on system PSRR. To help reduce this impact, the input capacitor combines with the pull-up resistance to function as a low-pass filter. Additionally, the time to charge the capacitor to the final dc bias point is a function of the pull-up resistor and the input capacitor size. Lastly, the input capacitor forms a high-pass filter with the parallel impedance of the pull-up resistor and the 800-kΩ resistor. In general, it is good to have this high-pass filter at approximately 3 Hz to minimize any potential droop on a P’B or P’R signal. A 0.1-μF input capacitor with a 3.3-MΩ pull-up resistor equates to approximately a 2.5-Hz high-pass corner frequency. This mode of operation is recommended for use with chroma (C’), P’B, P’R, U’, and V’ signals. This method can also be used with sync signals if desired. The benefit of using the STC function over the ac-bias configuration on embedded sync signals is that the STC maintains a constant back-porch voltage as opposed to a back-porch voltage that fluctuates depending on the video content. Because the high-pass corner frequency is a very low 2.5 Hz, the impact on the video signal is negligible relative to the STC configuration. One question may arise over the P’B and P’R channels. For 480i, 576i, 480p, and 576p signals, a sync may or may not be present. If no sync exists within the signal, then it is obvious that ac-bias is the preferred method of ac-coupling the signal. For 720p, 1080i, and 1080p signals, or for the the 480i, 576i, 480p, and 576p signals with sync present on the P’B and P’R channels, the lowest voltage of the sync is –300 mV below the midpoint reference voltage of 0 V. The P’B and P’R signals allow a signal to be as low as –350 mV below the midpoint reference voltage of 0 V. This allowance corresponds to 100% yellow for P’B signal or 100% cyan for P’R signal . Because the P’B and P’R signal voltage can be lower than the sync voltage, there exists a potential for clipping of the signal for a short period of time if the signals drop below the sync voltage. The THS7368 does include a 150-mV input level shift, or 300 mV at the output, that should mitigate any clipping issues. For example, if a STC is used, then the bottom of the sync is 300 mV at the output. If the signal does go the lowest level, or 50 mV lower than the sync at the input, then the instantaneous output is (–50 mV + 150 mV) × 2 = 200 mV at the output. Another potential risk is that if this signal (100% yellow for P’B or 100% cyan for P’R) exists for several pixels, then the STC circuit engages to raise the voltage back to 0 V at the input. This function can cause a 50-mV level shift at the input midway through the active video signal. This effect is undesirable and can cause errors in the decoding of the signal. It is therefore recommended to use ac bias mode for component P’B and P’R signals when ac-coupling is desired. OUTPUT MODE OF OPERATION: DC-COUPLED The THS7368 incorporates a rail-to-rail output stage that can be used to drive the line directly without the need for large ac-coupling capacitors. This design offers the best line tilt and field tilt (droop) performance because no ac-coupling occurs. Keep in mind that if the input is ac-coupled, then the resulting tilt as a result of the input ac-coupling continues to be seen on the output, regardless of the output coupling. The 80-mA output current drive capability of the THS7368 is designed to drive two video lines simultaneously—essentially, a 75-Ω load—while keeping the output dynamic range as wide as possible. Figure 41 shows the THS7368 driving two video lines while keeping the output dc-coupled. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 25 THS7368 SBOS497 – DECEMBER 2009 www.ti.com CVBS 1 Out 75 W THS7368 CVBS R S-Video Y’ SOC/DAC/Encoder R +2.7 V to +5 V S-Video C’ R Y'/G' CVBS 1 Out 75 W 1 SD1 IN SD1 OUT 20 2 SD2 IN SD2 OUT 19 3 SD3 IN SD3 OUT 18 4 NC Disable SD 17 75 W 75 W S-Video Y' 1 Out 75 W Disable SD S-Video Y' 1 Out 75 W 75 W 5 VS+ GND 16 6 NC Disable HD 15 7 SF1 IN SF1 OUT 14 8 SF2 IN SF2 OUT 13 S-Video C' 1 Out 9 SF3 IN SF3 OUT 12 75 W 10 Bypass SD Disable SF 75 W S-Video C' 1 Out 75 W Bypass SF 11 75 W 75 W R Y'/G' 1 Out 75 W Bypass SD LPF P'B/B' Y'/G' 1 Out Bypass SF LPF 75 W 75 W R 75 W P'B/B' 1 Out 75 W P'R/R' R P’B/B' 1 Out 75 W 75 W 75 W P’R/R' 1 Out 75 W P'R/R' 1 Out 75 W 75 W 75 W (1) SF indicates selectable filter. Figure 41. Typical Six-Channel System with DC-Coupled Line Driving and Two Outputs Per Channel One concern of dc-coupling, however, arises if the line is terminated to ground. If the ac-bias input configuration is used, the output of the THS7368 has a dc bias on the output, such as 1.6 V. With two lines terminated to ground, this configuration allows a dc current path to flow, such as 1.6 V/75-Ω = 21.3 mA. The result of this configuration is a slightly decreased high output voltage swing and an increase in power dissipation of the THS7368. While the THS7368 was designed to operate with a junction temperature of up to +125°C, care must be taken to ensure that the junction temperature does not exceed this level or else long-term reliability could suffer. Using a 5-V supply, this configuration can result in an additional dc power dissipation of (5 V – 1.6 V) × 21.3 mA = 72.5 mW per channel. With a 3.3-V supply, this dissipation reduces to 36.2 mW per channel. The overall low quiescent current of the THS7368 design minimizes potential thermal issues even when using the TSSOP package at high ambient temperatures, 26 but power and thermal analysis should always be examined in any system to ensure that no issues arise. Be sure to utilize RMS power and not instantaneous power when evaluating the thermal performance. Note that the THS7368 can drive the line with dc-coupling regardless of the input mode of operation. The only requirement is to make sure the video line has proper termination in series with the output (typically 75 Ω). This requirement helps isolate capacitive loading effects from the THS7368 output. Failure to isolate capacitive loads may result in instabilities with the output buffer, potentially causing ringing or oscillations to appear. The stray capacitance appearing directly at the THS7368 output pins should be kept below 20 pF for the fixed SD filter channels and below 15 pF for the selectable filter Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 channels. One way to help ensure this condition is satisfied is to make sure the 75-Ω source resistor is placed next to each THS7368 output pin. If a large ac-coupling capacitor is used, the capacitor should be placed after this resistor. There are many reasons dc-coupling is desirable, including reduced costs, PCB area, and no line tilt. A common question is whether or not there are any drawbacks to using dc-coupling. There are some potential issues that must be examined, such as the dc current bias as discussed above. Another potential risk is whether this configuration meets industry standards. EIA-770 stipulates that the back-porch shall be 0 V ± 1 V as measured at the receiver. With a double-terminated load system, this requirement implies a 0 V ± 2 V level at the video amplifier output. The THS7368 can easily meet this requirement without issue. However, in Japan, the EIAJ CP-1203 specification stipulates a 0 V ± 0.1 V level with no signal. This requirement can be met with the THS7368 in shutdown mode, but while active it cannot meet this specification without output ac-coupling. AC-coupling the output essentially ensures that the video signal works with any system and any specification. For many modern systems, however, dc-coupling can satisfy most needs. OUTPUT MODE OF OPERATION: AC-COUPLED A very common method of coupling the video signal to the line is with a large capacitor. This capacitor is typically between 220 μF and 1000 μF, although 470 μF is very typical. The value of this capacitor must be large enough to minimize the line tilt (droop) and/or field tilt associated with ac-coupling as described previously in this document. AC-coupling is performed for several reasons, but the most common is to ensure full interoperability with the receiving video system. This approach ensures that regardless of the reference dc voltage used on the transmitting side, the receiving side re-establishes the dc reference voltage to its own requirements. In the same way as the dc output mode of operation discussed previously, each line should have a 75-Ω source termination resistor in series with the ac-coupling capacitor. This 75-Ω resistor should be placed next to the THS7368 output to minimize capacitive loading effects. If two lines are to be driven, it is best to have each line use its own capacitor and resistor rather than sharing these components. This configuration helps ensure line-to-line dc isolation and eliminates the potential problems as described previously. Using a single, 1000-μF capacitor for two lines is permissible, but there is a chance for interference between the two receivers. Lastly, because of the edge rates and frequencies of operation, it is recommended (but not required) to place a 0.1-μF to 0.01-μF capacitor in parallel with the large 220-μF to 1000-μF capacitor. These large value capacitors are most commonly aluminum electrolytic. It is well-known that these capacitors have significantly large equivalent series resistance (ESR), and the impedance at high frequencies is rather large as a result of the associated inductances involved with the leads and construction. The small 0.1-μF to 0.01-μF capacitors help pass these high-frequency signals (greater than 1 MHz) with much lower impedance than the large capacitors. Although it is common to use the same capacitor values for all the video lines, the frequency bandwidth of the chroma signal in a S-Video system is not required to go as low (or as high of a frequency) as the luma channels. Thus, the capacitor values of the chroma line(s) can be smaller, such as 0.1 μF. Figure 42 shows a typical configuration where the input is ac-coupled and the output is also ac-coupled. AC-coupled inputs are generally required when current-sink DACs are used or the input is connected to an unknown source, such as when the THS7368 is used as an input device. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 27 THS7368 SBOS497 – DECEMBER 2009 www.ti.com THS7368 (1) 0.1 mF R (1) 0.1 mF +2.7 V to +5 V R (1) 0.1 mF R (1) 0.1 mF +V Y'/G' SD2 OUT 19 3 SD3 IN SD3 OUT 18 4 NC Disable SD 17 5 VS+ GND 16 6 NC Disable HD 15 7 SF1 IN SF1 OUT 14 8 SF2 IN SF2 OUT 13 9 SF3 IN SF3 OUT 12 10 Bypass SD 75 W (2) Y' Out 330 mF 75 W Disable SD To GPIO or GND/VS+ 75 W Disable SF (2) 330 mF 75 W P’B Out + S-Video C’ SD2 IN 75 W 75 W (2) 330 mF Y' Out + SOC/DAC/Encoder +V SD1 IN 2 + RPU S-Video Y’ 1 + CVBS +V (2) 330 mF 75 W SD1 OUT 20 Bypass SF 11 75 W R (1) 75 W (2) 330 mF P'B Out + Bypass SF LPF Bypass SD LPF 0.1 mF +V P'B/B' 75 W R To GPIO or GND/VS+ (1) 0.1 mF 75 W P'R/R' R RPU (2) 330 mF P'R Out + +V 75 W RPU +V +2.7 V to +5 V (1) AC-coupled input is shown in this example. DC-coupling is also allowed as long as the DAC output voltage is within the allowable linear input and output voltage range of the THS7368. To apply dc-coupling, remove the 0.1-μF input capacitors and the RPU pull-up resistors along with connecting the DAC termination resistors (R) to ground. (2) This example shows an ac-coupled output. DC-coupling is also allowed by simply removing these capacitors. (3) SF indicates selectable filter. Figure 42. Typical AC Input System Driving AC-Coupled Video Lines LOW-PASS FILTER Each channel of the THS7368 incorporates a sixth-order, low-pass filter. These video reconstruction filters minimize DAC images from being passed onto the video receiver. Depending on the receiver design, failure to eliminate these DAC images can cause picture quality problems because of aliasing of the ADC in the receiver. Another benefit of the filter is to smooth out aberrations in the signal that some DACs can have if the internal filtering is not very good. This benefit helps with picture quality and ensures that the signal meets video bandwidth requirements. Each filter has an associated Butterworth characteristic. The benefit of the Butterworth response is that the frequency response is flat with a relatively steep initial attenuation at the corner frequency. The problem with this characteristic is that the group delay rises near the corner frequency. Group delay is defined as the change in phase (radians/second) divided by a change in frequency. An increase in group delay corresponds to a time domain pulse response that has overshoot and some possible ringing associated with the overshoot. 28 The use of other type of filters, such as elliptic or chebyshev, are not recommended for video applications because of the very large group delay variations near the corner frequency resulting in significant overshoot and ringing. While these filters may help meet the video standard specifications with respect to amplitude attenuation, the group delay is well beyond the standard specifications. Considering this delay with the fact that video can go from a white pixel to a black pixel over and over again, it is easy to see that ringing can occur. Ringing typically causes a display to have ghosting or fuzziness appear on the edges of a sharp transition. On the other hand, a Bessel filter has ideal group delay response, but the rate of attenuation is typically too low for acceptable image rejection. Thus, the Butterworth filter is a respectable compromise for both attenuation and group delay. The THS7368 SD filters have a nominal corner (–3 dB) frequency at 9.5MHz and a –1-dB passband typically at 8.2MHz. This 9.5-MHz filter is ideal for SD NTSC, PAL, and SECAM composite video (CVBS) signals. It is also useful for S-Video signals (Y’C’), 480i/576i Y’/P’B/P’R, Y’U’V’, broadcast G’B’R’ signals, and computer R'G'B' video signals. The 9.5-MHz, Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 –3-dB corner frequency was designed to achieve 54 dB of attenuation at 27 MHz—a common sampling frequency between the DAC/ADC second and third Nyquist zones found in many video systems. This consideration is important because any signal that appears around this frequency can also appear in the baseband as a result of aliasing effects of an ADC found in a receiver. The THS7368 SF filters have a nominal corner (–3 dB) frequency at 9.5 MHz, 18 MHz, 36 MHz, or 72 MHz and a –1-dB passband typically at 8.2 MHz, 16 MHz, 30 MHz, or 60 MHz. The 9.5-MHz filter is ideal for component 480i or 576i video. The 18-MHz filter is ideal for component 480p or 576p component video. The 36-MHz filter is ideal for HD 720p, 1080i, 1080p24, or 1080p30 component video. The 72-MHz filter is ideal for 1080p50 or 1080p60 component video. These filters can also be utilized for some computer R’G’B’ video signals including VGA, SVGA, XGA, SXGA, and QXGA. Keep in mind that images do not stop at the DAC sampling frequency, fS (for example, 27 MHz for traditional SD DACs); they continue around the sampling frequencies of 2x fS, 3x fS, 4x fS, and so on (that is, 54-MHz, 81-MHz, 108-MHz, etc.). Because of these multiple images, an ADC can fold down into the baseband signal, meaning that the low-pass filter must also eliminate these higher-order images. The THS7368 filters are Butterworth filters and, as such, do not bounce at higher frequencies, thus maintaining good attenuation performance. The filter frequencies were chosen to account for process variations in the THS7368. To ensure the required video frequencies are effectively passed, the filter corner frequency must be high enough to allow component variations. The other consideration is that the attenuation must be large enough to ensure the anti-aliasing/reconstruction filtering is sufficient to meet the system demands. Thus, the selection of the filter frequencies was not arbitrarily selected and is a good compromise that should meet the demands of most systems. One of the features of the THS7368 is that these filters can be bypassed. Bypassing the SD filters results in an amplifier with 150-MHz bandwidth and 125-V/μs slew rate. This configuration can be helpful when diagnosing potential system issues or when simply wishing to pass higher frequency signals through the system. Bypassing the SF filters results in a amplifier supporting 375-MHz bandwidth and 600-V/μs slew rate. This configuration supports computer R'G'B' signals up to UWXGA resolution. BENEFITS OVER PASSIVE FILTERING Two key benefits of using an integrated filter system, such as the THS7368, over a passive system are PCB area and filter variations. The small TSSOP-20 package for six video channels is much smaller over a passive RLC network, especially a six-pole passive network. Additionally, consider that inductors have at best ±10% tolerances (normally, ±15% to ±20% is common) and capacitors typically have ±10% tolerances. Using a Monte Carlo analysis shows that the filter corner frequency (–3 dB), flatness (–1 dB), Q factor (or peaking), and channel-to-channel delay have wide variations. These variances can lead to potential performance and quality issues in mass-production environments. The THS7368 solves most of these problems with the corner frequency being essentially the only variable. Another concern about passive filters is the use of inductors. Inductors are magnetic components, and are therefore susceptible to electromagnetic coupling/interference (EMC/EMI). Some common coupling can occur because of other video channels nearby using inductors for filtering, or it can come from nearby switched-mode power supplies. Some other forms of coupling could be from outside sources with strong EMI radiation and can cause failure in EMC testing such as required for CE compliance. One concern about an active filter in an integrated circuit is the variation of the filter characteristics when the ambient temperature and the subsequent die temperature changes. To minimize temperature effects, the THS7368 uses low-temperature coefficient resistors and high-quality, low-temperature coefficient capacitors found in the BiCom3X process. These filters have been specified by design to account for process variations and temperature variations to maintain proper filter characteristics. This approach maintains a low channel-to-channel time delay that is required for proper video signal performance. Another benefit of the THS7368 over a passive RLC filter is the input and output impedance. The input impedance presented to the DAC varies significantly, from 35 Ω to over 1.5 kΩ with a passive network, and may cause voltage variations over frequency. The THS7368 input impedance is 800 kΩ, and only the 2-pF input capacitance plus the PCB trace capacitance impact the input impedance. As such, the voltage variation appearing at the DAC output is better controlled with a fixed termination resistor and the high input impedance buffer of the THS7368. On the output side of the filter, a passive filter again has a large impedance variation over frequency. The EIA770 specifications require the return loss to be at least 25 dB over the video frequency range of usage. For a video system, this requirement implies the Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 29 THS7368 SBOS497 – DECEMBER 2009 www.ti.com source impedance (which includes the source, series resistor, and the filter) must be better than 75 Ω, +9/–8 Ω. The THS7368 is an operational amplifier that approximates an ideal voltage source, which is desirable because the output impedance is very low and can source and sink current. To properly match the transmission line characteristic impedance of a video line, a 75-Ω series resistor is placed on the output. To minimize reflections and to maintain a good return loss meeting EIA specifications, this output impedance must maintain a 75-Ω impedance. A wide impedance variation of a passive filter cannot ensure this level of performance. On the other hand, the THS7368 has approximately 0.7 Ω of output impedance, or a return loss of 46 dB, at 6.75 MHz for the SD filters and approximately 1.7 Ω of output impedance, or a return loss of 39 dB, at 30 MHz for the SF-HD filters. Thus, the system is matched significantly better with a THS7368 compared to a passive filter. One final benefit of the THS7368 over a passive filter is power dissipation. A DAC driving a video line must be able to drive a 37.5-Ω load: the receiver 75-Ω resistor and the 75-Ω impedance matching resistor next to the DAC to maintain the source impedance requirement. This requirement forces the DAC to 30 drive at least 1.25 VP (100% saturation CVBS)/37.5 Ω = 33.3 mA. A DAC is a current-steering element, and this amount of current flows internally to the DAC even if the output is 0 V. Thus, power dissipation in the DAC may be very high, especially when six channels are being driven. Using the THS7368 with a high input impedance and the capability to drive up to two video lines per channel can reduce DAC power dissipation significantly. This outcome is possible because the resistance that the DAC drives can be substantially increased. It is common to set this resistance in a DAC by a current-setting resistor on the DAC itself. Thus, the resistance can be 300 Ω or more, substantially reducing the current drive demands from the DAC and saving significant amounts of power. For example, a 3.3-V, six-channel DAC dissipates 660 mW alone for the steering current capability (six channels × 33.3 mA × 3.3 V) if it must drive a 37.5-Ω load. With a 300-Ω load, the DAC power dissipation as a result of current steering current would only be 82 mW (six channels × 4.16 mA × 3.3 V). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 EVALUATION MODULE To evaluate the THS7368, an evaluation module (EVM) is available. The THS7368EVM allows for testing the THS7368 in many different configurations. Inputs and outputs include BNC connectors and RCA connectors commonly found in video systems, along with 75-Ω input termination resistors, 75-Ω series source termination resistors, and 75-Ω characteristic impedance traces. Several unpopulated component pads are found on the EVM to allow for different input and output configurations as dictated by the user. This EVM is designed to be used with a single supply from 2.6 V up to 5 V. The EVM default input configuration sets all channels for dc input coupling. The input signal must be within 0 V to approximately 1.4 V for proper operation. Failure to be within this range saturates and/or clips the output signal. If the input range is beyond this, if the signal voltage is unknown, or if coming from a current sink DAC, then ac input configuration is desired. This option is easily accomplished with the EVM by simply replacing the Z1 through Z6 0-Ω resistors with 0.1-μF capacitors. For an ac-coupled input and sync-tip clamp (STC) functionality commonly used for CVBS, s-video Y', component Y' signals, and R'G'B' signals, no other changes are needed. However, if a bias voltage is needed after the input capacitor which is commonly needed for s-video C', component P'B, and P'R, then a pull-up resistor should be added to the signal on the EVM. This configuration is easily achieved by simply adding a resistor to any of the following resistor pads; RX7 to RX12. A common value to use is 3.3 MΩ. Note that even signals with embedded sync can also use bias mode if desired. The EVM default output configuration sets all channels for ac output coupling. The 470-μF and 0.1-μF capacitors work well for most ac-coupled systems. However, if dc-coupled output is desired, then replacing the 0.1-μF capacitors (C20, C22, C24, C26, C28, and/or C30) with 0-Ω resistors works well. Removing the 470-μF capacitors is optional, but removing them from the EVM eliminates a few picofarads of stray capacitance on each signal path which may be desirable. The THS7368 incorporates an easy method to configure the bypass modes and the disable modes. The use of JP4 controls the SD channels disable feature; JP6 controls the SF channels disable feature; JP3 controls the SD channels filter/bypass mode; and JP5 controls the SF channels filter/bypass mode. Note that the EVM silkscreen shows HD rather than SF. Connection of JP4 and JP6 to GND applies 0 V to the disable pins and the THS7368 operates normally. Moving JP4 to +VS causes the THS7368 SD channels to be in disable mode, while moving JP6 to +VS causes the THS7368 SF channels to be in disable mode. Connection of JP3 to GND places the THS7368 SD channels in filter mode while moving JP3 to +VS places the THS7368 SD channels in bypass mode. Connection of JP5 to GND places the THS7368 SF channels in filter mode while moving JP5 to +VS places the THS7368 SF channels in bypass mode. The filter selection is also easily accomplished by using jumpers JP1 and JP2. JP1 controls the logic voltage for the filter 1 pin while JP2 controls the logic voltage for the filter 2 pin. Table 1 and Table 2 show the truth table for the filter selection and the appropriate logic. The EVM also has a truth table printed on it for easy reference. Figure 43 shows the THS7368EVM schematic. Figure 44 and Figure 45 illustrate the two layers of the EVM PCB, incorporating standard high-speed layout practices. Table 7 lists the bill of materials as the board comes supplied from Texas Instruments. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 31 THS7368 www.ti.com + + SBOS497 – DECEMBER 2009 Figure 43. THS7368 EVM Schematic 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 Figure 44. THS7368 EVM PCB Top Layer Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 33 THS7368 SBOS497 – DECEMBER 2009 www.ti.com Figure 45. THS7368 EVM PCB Bottom Layer 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 THS7368 www.ti.com SBOS497 – DECEMBER 2009 THS7368EVM Bill of Materials Table 7. THS7368 EVM ITEM REF DES QTY DESCRIPTION SMD SIZE 1 FB1, FB2 2 Bead, ferrite, 2.5 A, 330 Ω 2 C12 1 Capacitor, 100 µF, tantalum, 10V, 10%, low ESR 3 C40 1 Capacitor, 22 µF, tantalum, 16V, 10%, low ESR 4 C1-C6, C13-C18, C31-C36 18 Open 0805 5 C37 1 Capacitor, 0.01 µF, ceramic, 100 V, X7R 6 C8, C10, C11, C20, C22, C24, C26, C28, C30, C38, C39, C41-C52 23 7 C7, C9 8 MANUFACTURER PART NUMBER DISTRIBUTOR PART NUMBER (TDK) MPZ2012S331A (DIGI-KEY) 445-1569-1-ND C (AVX) TPSC107K010R0100 (DIGI-KEY) 478-1765-1-ND C (AVX) TPSC226K016R0375 (DIGI-KEY) 478-1767-1-ND 0805 (AVX) 08051C103KAT2A (DIGI-KEY) 478-1358-1-ND Capacitor, 0.1 µF, ceramic, 50 V, X7R 0805 (AVX) 08055C104KAT2A (DIGI-KEY) 478-1395-1-ND 2 Capacitor, 0.1 µF, ceramic, 50 V, X7R 1206 (AVX) 12065C104KAT2A (DIGI-KEY) 478-1556-1-ND C19, C21, C23, C25, C27, C29 6 Capacitor, aluminum, 470 µF, 10 V, 20% (PANASONIC) EEE-FP1A471AP (DIGI-KEY) PCE4526CT-ND 9 RX1-RX12 12 Open 0603 10 Z1-R9, R19-R21, R26-R28, R35-R37 18 Resistor, 0 Ω 0805 (ROHM) MCR10EZHJ000 (DIGI-KEY) RHM0.0ACT-ND 11 R1-R6, R29-R34 12 Resistor, 75 Ω, 1/8W, 1% 0805 (ROHM) MCR10EZHF75.0 (DIGI-KEY) RHM75.0CCT-ND 12 R14 1 Resistor, 100 Ω, 1/8W, 1% 0805 (ROHM) MCR10EZHF1000 (DIGI-KEY) RHM100CCT-ND 13 R10, R11, R15, R17, R24, R25 6 Resistor, 1k Ω, 1/8W, 1% 0805 (ROHM) MCR10EZHF1001 (DIGI-KEY) RHM1.00KCCT-ND 14 R12, R13, R16, R18, R22, R23 6 Resistor, 100k Ω, 1/8W, 1% 0805 (ROHM) MCR10EZHF1003 (DIGI-KEY) RHM100KCCT-ND 15 R38 1 Resistor, 1k Ω, 1/4W, 1% 1206 (ROHM) MCR18EZHF1001 (DIGI-KEY) RHM1.00KFCT-ND 16 D1-D12 12 Diode, ultrafast (FAIRCHILD) BAV99 (DIGI-KEY) BAV99FSCT-ND 17 J10, J11 2 Jack, banana receptance, 0.25" diameter hole (SPC) 813 (NEWARK) 39N867 18 J1-J6, J13-J18 12 Connector, BNC, jack, 75 Ω (AMPHENOL) 31-5329-72RFX (NEWARK) 93F7554 19 J8, J20 2 Connector, mini circular DIN (CUI) MD-40SM (DIGI-KEY) CP-2240-ND 20 J7, J19 2 Connector, RCA jack, yellow (CUI) RCJ-044 (DIGI-KEY) CP-1421-ND 21 J9, J12 2 Connector, RCA, jack, R/A (CUI) RCJ-32265 (DIGI-KEY) CP-1446-ND 22 TP1, TP2 2 Test point, black (KEYSTONE) 5001 (DIGI-KEY) 5001K-ND 23 JP1-JP6 6 Header, 0.1" CTRS, 0.025" square pins (SULLINS) PBC36SAAN (DIGI-KEY) S1011E-36-ND 24 JP1-JP6 6 Shunts (SULLINS) SSC02SYAN (DIGI-KEY) S9002-ND 25 U1 1 IC, THS7368 26 — 4 Standoff, 4-40 hex, 0.625" length (KEYSTONE) 1808 (DIGI-KEY) 1808K-ND 27 — 4 Screw, Phillips, 4-40, .250" (BF) PMS 440 0031 PH (DIGI-KEY) H343-ND 28 — 1 Board, printed circuit Edge # 6510793 Rev. A 805 F 3 pos. PW (TI) THS7368IPW Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 35 THS7368 SBOS497 – DECEMBER 2009 www.ti.com EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 2.6 V to 5.5 V single-supply and the output voltage range of 0 V to 5.5 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2009, Texas Instruments Incorporated 36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): THS7368 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS7368IPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS7368 THS7368IPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS7368 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of