SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
D Trimmed Offset Voltage:
D
D
D
D
D
D
D
D
1OUT
1IN −
1IN +
VDD
2IN +
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN +
GND
3IN +
3IN −
3OUT
FK PACKAGE
(TOP VIEW)
1IN −
1OUT
NC
4OUT
4IN −
D
D, J, N, OR PW PACKAGE
(TOP VIEW)
1IN +
NC
VDD
NC
2IN +
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4IN +
NC
GND
NC
3IN +
2IN −
2OUT
NC
3OUT
3IN −
D
TLC279 . . . 900 µV Max at 25°C,
VDD = 5 V
Input Offset Voltage Drift . . . Typically
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix
and I-Suffix Versions)
Low Noise . . . Typically 25 nV/√Hz
at f = 1 kHz
Output Voltage Range Includes Negative
Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up Immunity
description
NC − No internal connection
The TLC274 and TLC279 quad operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high
input impedance, low noise, and speeds
approaching that of general-purpose BiFET
devices.
The extremely high input impedance, low bias
currents, and high slew rates make these
cost-effective devices ideal for applications which
have previously been reserved for BiFET and
NFET products. Four offset voltage grades are
available (C-suffix and I-suffix types), ranging
from the low-cost TLC274 (10 mV) to the highprecision TLC279 (900 µV). These advantages, in
combination with good common-mode rejection
and supply voltage rejection, make these devices
a good choice for new state-of-the-art designs as
well as for upgrading existing designs.
30
25
Percentage of Units − %
These devices use Texas Instruments silicongate LinCMOS technology, which provides
offset voltage stability far exceeding the stability
available
with
conventional
metal-gate
processes.
DISTRIBUTION OF TLC279
INPUT OFFSET VOLTAGE
290 Units Tested From 2 Wafer Lots
VDD = 5 V
TA = 25°C
N Package
20
15
10
5
0
−1200
−600
0
600
VIO − Input Offset Voltage − µV
1200
LinCMOS is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
! "# $
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
description (continued)
In general, many features associated with bipolar technology are available on LinCMOS operational
amplifiers, without the power penalties of bipolar technology. General applications such as transducer
interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the
TLC274 and TLC279. The devices also exhibit low voltage single-supply operation, making them ideally suited
for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the
negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC274 and TLC279 incorporate internal ESD-protection circuits that prevent functional failures at voltages
up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling
these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from − 40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)
CHIP
FORM
(Y)
0°C to 70°C
900 µV
2 mV
5 mV
10 mV
TLC279CD
TLC274BCD
TLC274ACD
TLC274CD
—
—
—
—
—
—
—
—
TLC279CN
TLC274BCN
TLC274ACN
TLC274CN
—
—
—
TLC274CPW
—
—
—
TLC274Y
−40°C to 85°C
900 µV
2 mV
5 mV
10 mV
TLC279ID
TLC274BID
TLC274AID
TLC274ID
—
—
—
—
—
—
—
—
TLC279IN
TLC274BIN
TLC274AIN
TLC274IN
—
—
—
—
—
—
—
—
−55°C to 125°C
900 µV
10 mV
TLC279MD
TLC274MD
TLC279MFK
TLC274MFK
TLC279MJ
TLC274MJ
TLC279MN
TLC274MN
—
—
—
—
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC279CDR).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
equivalent schematic (each amplifier)
VDD
P3
P4
R6
R1
R2
IN −
N5
P5
P6
P2
P1
IN +
C1
R5
OUT
N3
N1
R3
N4
N2
D1
R4
N6
N7
R7
D2
GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TLC274Y chip information
These chips, when properly assembled, display characteristics similar to the TLC274C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(14)
(13)
(12) (11)
(10)
(9)
(8)
(3)
1IN +
1IN −
(2)
VDD
(4)
+
(1)
1OUT
−
(5)
+
(7)
2OUT
(10)
68
3IN +
(9)
3IN −
4OUT
(6)
−
+
2IN +
2IN −
(8)
3OUT
−
+
(14)
−
(12)
(13)
4IN +
4IN −
11
(1)
(2)
(3)
(4)
(5)
(6)
(7)
GND
108
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACK SIDE OF CHIP.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, lO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input with respect to the inverting input.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
950 mW
7.6 mW/°C
608 mW
494 mW
—
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
J
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
N
1575 mW
12.6 mW/°C
1008 mW
819 mW
—
PW
700 mW
5.6 mW/°C
448 mW
—
—
recommended operating conditions
Supply voltage, VDD
Common-mode input voltage, VIC
VDD = 5 V
VDD = 10 V
Operating free-air temperature, TA
POST OFFICE BOX 655303
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MAX
MIN
MAX
MIN
MAX
3
16
4
16
4
16
−0.2
3.5
−0.2
3.5
0
3.5
−0.2
8.5
−0.2
8.5
0
8.5
0
70
−40
85
−55
125
• DALLAS, TEXAS 75265
UNIT
V
V
°C
5
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC274C, TLC274AC,
TLC274BC, TLC279C
MIN
TLC274C
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274AC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC279C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (see Note 4)
IIB
Input bias current (see Note 4)
VO = 2.5 V,
VICR
VOH
VOL
VIC = 2.5 V
25°C
Low-level output voltage
VID = 100 mV,
RL = 10 kΩ
VID = − 100 mV,
IOL = 0
CMRR
kSVR
Large-signal differential voltage
amplification
Common-mode rejection ratio
VO = 0.25 V to 2 V,
RL = 10 kΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (four amplifiers)
VO = 2.5 V,
No load
VO = 1.4 V
1.1
10
0.9
5
340
2000
Full range
Full range
3000
25°C
320
Full range
900
1.8
25°C
0.1
60
70°C
7
300
25°C
0.6
60
70°C
40
600
25°C
−0.2
to
4
Full range
−0.2
to
3.5
25°C
3.2
3.8
0°C
3
3.8
70°C
3
3.8
µV/°C
−0.3
to
4.2
V
25°C
0
50
0°C
0
50
0
50
25°C
5
23
0°C
4
27
70°C
4
20
25°C
65
80
0°C
60
84
70°C
60
85
25°C
65
95
0°C
60
94
70°C
60
96
mV
V/mV
dB
dB
3.1
7.2
70°C
2.3
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
5.2
• DALLAS, TEXAS 75265
pA
V
0°C
POST OFFICE BOX 655303
pA
V
6.4
6
µV
V
1500
25°C to
70°C
2.7
VIC = 2.5 V,
mV
6.5
25°C
25°C
IDD
UNIT
12
25°C
70°C
AVD
MAX
Full range
Common-mode input voltage range
(see Note 5)
High-level output voltage
TYP
mA
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC274C, TLC274AC,
TLC274BC, TLC279C
MIN
TLC274C
VIO
VO = 1.4 V,
RS = 50 Ω,
TLC274AC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC279C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
αVIO
Average temperature coefficient of
input offset voltage
IIO
Input offset current (see Note 4)
IIB
Input bias current (see Note 4)
VOH
VOL
25°C
VIC = 5 V
Low-level output voltage
VID = 100 mV,
VID = − 100 mV,
RL = 10 kΩ
IOL = 0
CMRR
kSVR
Large-signal differential voltage
amplification
Common-mode rejection ratio
VO = 1 V to 6 V,
RL = 10 kΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (four amplifiers)
VO = 5 V,
No load
VO = 1.4 V
10
0.9
5
390
2000
Full range
Full range
3000
25°C
370
Full range
1200
µV/°C
2
25°C
0.1
60
70°C
7
300
25°C
0.7
60
70°C
50
600
25°C
−0.2
to
9
Full range
−0.2
to
8.5
−0.3
to
9.2
25°C
8
8.5
0°C
7.8
8.5
70°C
7.8
8.4
V
25°C
0
50
0°C
0
50
0
50
25°C
10
36
0°C
7.5
42
70°C
7.5
32
25°C
65
85
0°C
60
88
70°C
60
88
25°C
65
95
0°C
60
94
70°C
60
96
mV
V/mV
dB
dB
0°C
4.5
8.8
70°C
3.2
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6.8
• DALLAS, TEXAS 75265
pA
V
8
POST OFFICE BOX 655303
pA
V
3.8
VIC = 5 V,
µV
V
1900
25°C
IDD
mV
6.5
25°C
70°C
AVD
1.1
UNIT
12
25°C
Common-mode input voltage range
(see Note 5)
High-level output voltage
MAX
Full range
25°C to
70°C
VO =.5 V,
VICR
VIC = 0,
RL = 10 kΩ
TYP
mA
7
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC274I, TLC274AI,
TLC274BI, TLC279I
MIN
TLC274I
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274AI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC279I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (see Note 4)
IIB
Input bias current (see Note 4)
VO = 2.5 V,
VICR
VOH
VOL
VIC = 2.5 V
25°C
Low-level output voltage
VID = 100 mV,
RL = 10 kΩ
VID = −100 mV,
IOL = 0
CMRR
kSVR
IDD
Large-signal differential voltage
amplification
Common-mode rejection ratio
VO = 0.25 V to 2 V,
RL = 10 kΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (four amplifiers)
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
1.1
10
0.9
5
340
2000
Full range
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
7
25°C
Full range
3500
25°C
320
Full range
900
µV
V
2000
25°C to
85°C
1.8
25°C
0.1
60
85°C
24
1000
25°C
0.6
60
85°C
200
2000
25°C
−0.2
to
4
Full range
−0.2
to
3.5
µV/°C
−0.3
to
4.2
pA
pA
V
V
25°C
3.2
3.8
−40°C
3
3.8
85°C
3
3.8
V
25°C
0
50
−40°C
0
50
0
50
25°C
5
23
−40°C
3.5
32
85°C
3.5
19
25°C
65
80
−40°C
60
81
85°C
60
86
25°C
65
95
−40°C
60
92
85°C
60
96
mV
V/mV
dB
dB
25°C
2.7
6.4
−40°C
3.8
8.8
85°C
2.1
4.8
† Full range is − 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
8
UNIT
13
25°C
85°C
AVD
MAX
Full range
Common-mode input voltage range
(see Note 5)
High-level output voltage
TYP
mA
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC274I, TLC274AI,
TLC274BI, TLC279I
MIN
TLC274I
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274AI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC274BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC279I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (see Note 4)
IIB
Input bias current (see Note 4)
VO = 5 V,
VICR
VOH
VOL
VIC = 5 V
25°C
Low-level output voltage
VID = 100 mV,
RL = 10 kΩ
VID = − 100 mV,
IOL = 0
CMRR
kSVR
Large-signal differential voltage
amplification
Common-mode rejection ratio
VO = 1 V to 6 V,
RL = 10 kΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (four amplifiers)
VO = 5 V,
No load
VO = 1.4 V
1.1
10
0.9
5
390
2000
Full range
Full range
3500
25°C
370
Full range
1200
2
25°C
0.1
60
85°C
26
1000
25°C
0.7
60
85°C
220
2000
25°C
−0.2
to
9
Full range
−0.2
to
8.5
µV/°C
−0.3
to
9.2
pA
V
25°C
8
8.5
−40°C
7.8
8.5
85°C
7.8
8.5
V
25°C
0
50
−40°C
0
50
0
50
25°C
10
36
−40°C
7
47
85°C
7
31
25°C
65
85
−40°C
60
87
85°C
60
88
25°C
65
95
−40°C
60
92
85°C
60
96
mV
V/mV
dB
dB
−40°C
5.5
10
85°C
2.9
† Full range is − 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6.4
• DALLAS, TEXAS 75265
pA
V
8
POST OFFICE BOX 655303
µV
V
2900
25°C to
85°C
3.8
VIC = 5 V,
mV
7
25°C
25°C
IDD
UNIT
13
25°C
85°C
AVD
MAX
Full range
Common-mode input voltage range
(see Note 5)
High-level output voltage
TYP
mA
9
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Full range
TLC279M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Full range
Input offset voltage
Average temperature coefficient of input
offset voltage
IIO
Input offset current (see Note 4)
VO = 2.5 V,
VICR
VOH
VOL
VIC = 2.5 V
Input bias current (see Note 4)
Low-level output voltage
VID = 100 mV,
RL = 10 kΩ
VID = − 100 mV,
IOL = 0
MIN
CMRR
kSVR
Large-signal differential voltage
amplification
Common-mode rejection ratio
VO = 0.25 V to 2 V,
RL = 10 kΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (four amplifiers)
VO = 2.5 V,
No load
VO = 1.4 V
MAX
1.1
10
320
900
3750
25°C
0.1
60
pA
125°C
1.4
15
nA
25°C
0.6
60
pA
125°C
9
35
nA
25°C
0
to
4
Full range
0
to
3.5
−0.3
to
4.2
V
V
25°C
3.2
3.8
−55°C
3
3.8
125°C
3
3.8
V
25°C
0
50
−55°C
0
50
0
50
25°C
5
23
−55°C
3.5
35
125°C
3.5
16
25°C
65
80
−55°C
60
81
125°C
60
84
25°C
65
95
−55°C
60
90
125°C
60
97
dB
dB
−55°C
4
10
125°C
1.9
† Full range is − 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
4.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
V/mV
6.4
10
µV
V
µV/°C
2.7
VIC = 2.5 V,
mV
2.1
25°C
IDD
UNIT
25°C to
125°C
125°C
AVD
TYP
12
25°C
Common-mode input voltage range
(see Note 5)
High-level output voltage
TLC274M, TLC279M
25°C
TLC274M
αVIO
IIB
TA†
mA
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, VDD = 10 V (unless) otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
TLC274M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC279M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (see Note 4)
VO = 5 V,
IIB
VICR
VOH
VOL
AVD
CMRR
kSVR
VIC = 5 V
Input bias current (see Note 4)
TA†
Low-level output voltage
Large-signal differential voltage
amplification
Common-mode rejection ratio
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VID = 100 mV,
RL = 10 kΩ
VID = − 100 mV,
VO = 1 V to 6 V,
IOL = 0
RL = 10 kΩ
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 1.4 V
MIN
25°C
TYP
MAX
1.1
10
Full range
12
25°C
370
Full range
1200
4300
25°C to
125°C
2.2
0.1
60
pA
1.8
15
nA
25°C
0.7
60
pA
125°C
10
35
nA
25°C
0
to
9
Full range
0
to
8.5
−0.3
to
9.2
V
V
25°C
8
8.5
−55°C
7.8
8.5
125°C
7.8
8.4
V
25°C
0
50
−55°C
0
50
125°C
0
50
25°C
10
36
−55°C
7
50
125°C
7
27
25°C
65
85
−55°C
60
87
125°C
60
86
25°C
65
95
−55°C
60
90
125°C
60
dB
dB
97
8
6.0
12
125°C
2.5
† Full range is − 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
5.6
POST OFFICE BOX 655303
VIC = 5 V,
• DALLAS, TEXAS 75265
mV
V/mV
−55°C
VO = 5 V,
No load
µV
V
25°C
3.8
Supply current (four amplifiers)
mV
µV/°C
25°C
IDD
UNIT
125°C
Common-mode input voltage range
(see Note 5)
High-level output voltage
TLC274M, TLC279M
mA
11
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC274C, TLC274AC,
TLC274AC,
TLC274BC, TLC279C
MIN
SR
Slew rate at unity gain
RL = 10 Ω,,
CL = 20 PF,
See Figure 1
VIPP = 1 V
VIPP = 2.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω ,
Maximum output-swing bandwidth
VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 PF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 PF,
f = B1,
TYP
25°C
3.6
0°C
4
70°C
3
25°C
2.9
0°C
3.1
70°C
2.5
25°C
25
25°C
320
0°C
340
70°C
260
25°C
1.7
0°C
2
70°C
1.3
25°C
46°
0°C
47°
70°C
44°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC274C, TLC274AC,
TLC274AC,
TLC274BC, TLC279C
MIN
SR
Slew rate at unity gain
RL = 10 Ω,,
CL = 20 PF,
See Figure 1
VIPP = 1 V
VIPP = 5.5 V
Vn
BOM
B1
φm
12
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 PF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 PF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
5.3
0°C
5.9
70°C
4.3
25°C
4.6
0°C
5.1
70°C
3.8
25°C
25
25°C
200
0°C
220
70°C
140
25°C
2.2
0°C
2.5
70°C
1.8
25°C
49°
0°C
50°
70°C
46°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC274I, TLC274AI,
TLC274BI, TLC279I
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
k ,
CL = 20 PF,
See Figure 1
VIPP = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 PF,
B1
φm
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 PF,
f = B1,
See Figure 3
TYP
25°C
3.6
−40°C
4.5
85°C
2.8
25°C
2.9
−40°C
3.5
85°C
2.3
25°C
25
25°C
320
−40°C
380
85°C
250
25°C
1.7
−40°C
2.6
85°C
1.2
25°C
46°
−40°C
49°
85°C
43°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC274I, TLC274AI,
TLC274BI, TLC279I
MIN
SR
Slew rate at unity gain
RL = 10 Ω,,
CL = 20 PF,
See Figure 1
VIPP = 1 V
VIPP = 5.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 PF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 PF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
5.3
−40°C
6.7
85°C
4
25°C
4.6
−40°C
5.8
85°C
3.5
25°C
25
25°C
200
−40°C
260
85°C
130
25°C
2.2
−40°C
3.1
85°C
1.7
25°C
49°
−40°C
52°
85°C
46°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
13
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TLC274M, TLC279M
TEST CONDITIONS
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
k ,
CL = 20 PF,
See Figure 1
VIPP = 2.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 PF,
Phase margin
CL = 20 PF,
f = B1,
See Figure 3
TA
MIN
TYP
25°C
3.6
−55°C
4.7
125°C
2.3
25°C
2.9
−55°C
3.7
125°C
2
25°C
25
25°C
320
−55°C
400
125°C
230
25°C
1.7
−55°C
2.9
125°C
1.1
25°C
46°
−55°C
49°
125°C
41°
MAX
UNIT
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
SR
Slew rate at unity gain
TLC274M, TLC279M
TEST CONDITIONS
RL = 10 Ω ,
CL = 20 PF,
See Figure 1
VIPP = 1 V
VIPP = 5.5 V
Vn
BOM
B1
φm
14
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 10 kΩ,
CL = 20 PF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 PF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 PF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TA
MIN
TYP
25°C
5.3
−55°C
7.1
125°C
3.1
25°C
4.6
−55°C
6.1
125°C
2.7
25°C
25
25°C
200
−55°C
280
125°C
110
25°C
2.2
−55°C
3.4
125°C
1.6
25°C
49°
−55°C
52°
125°C
44°
MAX
UNIT
V/ s
V/µs
nV/√Hz
kHz
MHz
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
TLC274Y
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
IIO
IIB
Input offset current (see Note 4)
VICR
Common-mode input voltage range (see Note 5)
VOH
VOL
High-level output voltage
AVD
CMRR
Large-signal differential voltage amplification
kSVR
Supply-voltage rejection ratio (∆VDD /∆VIO)
IDD
Supply current (four amplifiers)
Input bias current (see Note 4)
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
VO = 2.5 V,
VIC = 2.5 V
VID = 100 mV,
VID = −100 mV,
Low-level output voltage
Common-mode rejection ratio
VO = 0.25 V to 2 V,
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VO = 1.4 V
VIC = 2.5 V,
MIN
TYP
MAX
1.1
10
UNIT
mV
0.1
pA
0.6
pA
−0.2
to
4
−0.3
to
4.2
V
3.2
3.8
0
V
50
mV
5
23
V/mV
65
80
dB
65
95
dB
2.7
6.4
mA
electrical characteristics, VDD = 10 V, TA = 25°C (unless otherwise noted)
TLC274Y
PARAMETER
VIO
Input offset voltage
IIO
IIB
Input offset current (see Note 4)
TEST CONDITIONS
Input bias current (see Note 4)
VICR
Common-mode input voltage range (see Note 5)
VOH
VOL
High-level output voltage
AVD
CMRR
Large-signal differential voltage amplification
kSVR
Supply-voltage rejection ratio (∆VDD /∆VIO)
IDD
Supply current (four amplifiers)
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
VO = 5 V,
VIC = 5 V
VID = 100 mV,
VID = −100 mV,
Low-level output voltage
Common-mode rejection ratio
VO = 1 V to 6 V,
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 5 V,
No load
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VO = 1.4 V
VIC = 5 V,
MIN
TYP
MAX
1.1
10
UNIT
mV
0.1
pA
0.7
pA
−0.2
to
9
−0.3
to
9.2
V
8
8.5
0
V
50
mV
10
36
V/mV
65
85
dB
65
95
dB
3.8
8
mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics, VDD = 5 V, TA = 25°C
TLC274Y
PARAMETER
TEST CONDITIONS
MAX
UNIT
3.6
RS = 20 Ω,
See Figure 2
25
nV/√Hz
CL = 20 PF,
RL = 10 kΩ,
320
kHz
CL = 20 PF,
See Figure 3
1.7
MHz
f = B1,
CL = 20 PF,
46°
Slew rate at unity gain
RL = 10 kΩ,
See Figure 1
CL = 20 PF,
Vn
Equivalent input noise voltage
f = 1 kHz,
BOM
Maximum output-swing bandwidth
VO = VOH,
See Figure 1
B1
Unity-gain bandwidth
VI = 10 mV,
VI = 10 mV,
See Figure 3
Phase margin
TYP
VIPP = 1 V
VIPP = 2.5 V
SR
φm
MIN
V/ s
V/µs
2.9
operating characteristics, VDD = 10 V, TA = 25°C
TLC274Y
PARAMETER
TEST CONDITIONS
See Figure 2
25
nV/√Hz
CL = 20 PF,
RL = 10 kΩ,
200
kHz
CL = 20 PF,
See Figure 3
2.2
MHz
f = B1,
CL = 20 PF,
49°
CL = 20 PF,
Vn
Equivalent input noise voltage
f = 1 kHz,
BOM
Maximum output-swing bandwidth
VO = VOH,
See Figure 1
B1
Unity-gain bandwidth
VI = 10 mV,
VI = 10 mV,
See Figure 3
POST OFFICE BOX 655303
UNIT
RS = 20 Ω,
RL = 10 kΩ,
See Figure 1
16
MAX
5.3
Slew rate at unity gain
Phase margin
TYP
VIPP = 1 V
VIPP = 5.5 V
SR
φm
MIN
• DALLAS, TEXAS 75265
4.6
V/ s
V/µs
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC274 and TLC279 are optimized for single-supply operation, circuit configurations used for the
various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.
VDD
VDD +
−
−
VO
+
CL
VO
VI
RL
+
VI
CL
RL
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
2 kΩ
VDD +
VDD
−
20 Ω
−
VO
VO
20 Ω
+
+
1/2 VDD
2 kΩ
20 Ω
20 Ω
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 2. Noise-Test Circuit
10 kΩ
VDD
−
VI
100 Ω
VDD +
−
VI
100 Ω
10 kΩ
VO
VO
+
+
1/2 VDD
CL
CL
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC274 and TLC279 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
7
1
V = VIC
8
14
Figure 4. Isolation Metal Around Device Inputs (J and N packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz
(b) BOM > f > 1 kHz
(c) f = BOM
(d) f > BOM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
20
VIO
αVIO
Input offset voltage
Distribution
6, 7
Temperature coefficient of input offset voltage
Distribution
8, 9
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
vs Free-air temperature
10, 11
12
13
VOL
Low-level output voltage
vs Common-mode input voltage
vs Differential input voltage
vs Free-air temperature
vs Low-level output current
14, 15
16
17
18, 19
AVD
Large-signal differential voltage amplification
vs Supply voltage
vs Free-air temperature
vs Frequency
20
21
32, 33
IIB
IIO
Input bias current
vs Free-air temperature
22
Input offset current
vs Free-air temperature
22
VIC
Common-mode input voltage
vs Supply voltage
23
IDD
Supply current
vs Supply voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Supply voltage
vs Free-air temperature
26
27
Normalized slew rate
vs Free-air temperature
28
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
29
B1
Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
30
31
φm
Phase margin
vs Supply voltage
vs Free-air temperature
vs Load capacitance
34
35
36
Vn
Equivalent input noise voltage
vs Frequency
37
Phase shift
vs Frequency
32, 33
POST OFFICE BOX 655303
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC274
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC274
INPUT OFFSET VOLTAGE
Percentage of Units − %
50
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
60
753 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA= 25°C
N Package
753 Amplifiers Tested From 6 Wafer Lots
VDD = 10 V
TA = 25°C
N Package
50
Percentage of Units − %
60
40
30
20
40
30
20
10
10
0
0
−5
−4
−3 −2 −1 0
1
2
3
VIO − Input Offset Voltage − mV
4
−5
5
−4
Figure 6
40
5
DISTRIBUTION OF TLC274 AND TLC279
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑ
60
324 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
N Package
Outliers:
(1) 20.5 V/°C
50
Percentage of Units − %
Percentage of Units − %
50
4
Figure 7
DISTRIBUTION OF TLC274 AND TLC279
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
60
−3 −2 −1 0
1
2
3
VIO − Input Offset Voltage − mV
30
20
10
40
324 Amplifiers Tested From 8 Wafer Lots
VDD = 10 V
TA = 25°C to 125°C
N Package
Outliers:
(1) 21.2 V/C
30
20
10
0
2
4
6
8
−10 −8 −6 −4 −2 0
αVIO − Temperature Coefficient − µV/°C
10
0
−10 −8 −6 −4 −2 0
2
4
6
8
αVIO − Temperature Coefficient − µV/°C
10
Figure 9
Figure 8
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21
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
Q
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
16
VID = 100 mV
TA = 25°C
4
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
2
1
0
VDD = 16 V
12
10
8
VDD = 10 V
6
4
2
0
0
−2
−4
−6
−8
−10
0
−10 −15
−5
IOH − High-Level Output Current − mA
−20 −25
−30
−35
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VDD −1.6
16
12
VOH − High-Level Output Voltage − V
VID = 100 mV
RL = 10 kΩ
TA = 25°C
14
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
IOH = − 5 mA
VID = 100 mA
VDD −1.7
VDD = 5 V
VDD −1.8
VDD −1.9
VDD −2
VDD = 10 V
VDD −2.1
VDD −2.2
VDD −2.3
VDD −2.4
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
VDD − Supply Voltage − V
Figure 12
Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
−40
IOH − High-Level Output Current − mA
Figure 10
VOH − High-Level Output Voltage − V
VID = 100 mV
TA = 25°C
14
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
5
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125
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
500
VDD = 5 V
IOL = 5 mA
TA = 25°C
650
VOL − Low-Level Output Voltage − mV
VOL − Low-Level Output Voltage − mV
700
600
550
VID = − 100 mV
500
450
400
VID = − 1 V
350
450
400
VID = − 100 mV
0
1
2
3
VIC − Common-Mode Input Voltage − V
VID = − 1 V
350
VID = − 2.5 V
300
250
300
VDD = 10 V
IOL = 5 mA
TA = 25°C
4
0
2
4
6
8
1
3
5
7
9
VIC − Common-Mode Input Voltage − V
Figure 15
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
800
900
IOL = 5 mA
VIC = |VID/2|
TA = 25°C
700
VOL − Low-Level Output Voltage − mV
VOL − Low-Level Output Voltage − mV
10
600
500
VDD = 5 V
400
300
VDD = 10 V
200
100
0
0
−1
−2 −3 −4 −5 −6 −7 −8 −9
VID − Differential Input Voltage − V
−10
800
700
IOL = 5 mA
VID = − 1 V
VIC = 0.5 V
VDD = 5 V
600
500
400
VDD = 10 V
300
200
100
0
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 17
Figure 16
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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23
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1
3
VOL − Low-Level Output Voltage − V
0.9
0.8
VOL − Low-Level Output Voltage − V
VID = − 1 V
VIC = 0.5 V
TA = 25°C
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
IOL − Low-Level Output Current − mA
2.5
VDD = 10 V
1.5
1
0.5
0
8
0
5
10
15
20
25
IOL − Low-Level Output Current − mA
50
ÑÑÑ
TA = 0°C
40
ÑÑÑÑ
ÑÑÑÑ ÁÁ
ÑÑÑÑ ÁÁ
ÁÁ
30
TA = 25°C
TA = 85°C
20
TA = 125°C
10
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
RL = 10 kΩ
45
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
ÁÁ
ÁÁ
ÁÁ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
TA = − 55°C
RL = 10 kΩ
40
VDD = 10 V
35
30
25
20
VDD = 5 V
15
10
5
0
−75
−50
Figure 20
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
30
Figure 19
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
50
VDD = 16 V
2
Figure 18
60
ÑÑÑÑÑ
ÑÑÑÑÑ
VID = − 1 V
VIC = 0.5 V
TA = 25°C
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125
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
10000
VDD = 10 V
VIC = 5 V
See Note A
16
ÑÑÑ
ÑÑÑ
1000
IIB
100
VIC − Common-Mode Input Voltage − V
I IB and I IO − Input Bias and Offset Currents − pA
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
ÑÑ
ÑÑ
IIO
10
1
0.1
25
45
65
85
105
TA − Free-Air Temperature − °C
125
TA = 25°C
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
16
Figure 23
Figure 22
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
10
8
VO = VDD/2
No Load
9
7
VO = VDD/2
No Load
TA = − 55°C
8
7
ÑÑÑÑ
ÑÑÑÑ
6
TA = 25°C
5
4
3
ÑÑÑ
TA = 0°C
ÑÑÑÑ
ÑÑÑÑ
ÑÑÑÑÑ
ÑÑÑÑÑ
2
TA = 70°C
1
I DD − Supply Current − mA
I DD − Supply Current − mA
14
6
5
VDD = 10 V
4
3
VDD = 5 V
2
1
TA = 125°C
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
0
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 24
125
Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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25
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
FREE-AIR TEMPERATURE
8
6
5
7
VDD = 10 V
VIPP = 5.5 V
6
SR − Slew Rate − V/ µs
7
SR − Slew Rate − V/ µs
ÑÑÑÑÑ
ÑÑÑÑÑ
8
AV = 1
VIPP = 1 V
RL = 10 k Ω
CL = 20 pF
TA = 25°C
See Figure 1
4
3
2
VDD = 10 V
VIPP = 1 V
5
4
3
VDD = 5 V
VIPP = 1 V
2
1
VDD = 5 V
VIPP = 2.5 V
1
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
0
−75
16
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
1.5
VDD = 10 V
Normalized Slew Rate
1.3
AV = 1
VIPP = 1 V
RL = 10 kΩ
CL = 20 pF
1.2
1.1
VDD = 5 V
1
0.9
0.8
0.7
0.6
0.5
−75
−50
125
Figure 27
Figure 26
1.4
AV = 1
RL = 10 k Ω
CL = 20 pF
See Figure 1
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
10
VDD = 10 V
9
8
TA = 125°C
TA = 25°C
TA = − 55°C
7
6
5
VDD = 5 V
4
3
RL = 10 k Ω
See Figure 1
2
1
0
10
Figure 28
100
1000
f − Frequency − kHz
10000
Figure 29
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
26
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TYPICAL CHARACTERISTICS†
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
3
2.5
B1 − Unity-Gain Bandwidth − MHz
B1 − Unity-Gain Bandwidth − MHz
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
2.5
2
1.5
1
−75
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
2
1.5
1
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
0
125
2
4
6
8
10
12
VDD − Supply Voltage − V
Figure 30
14
16
Figure 31
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
VDD = 5 V
RL = 10 k Ω
TA = 25°C
ÁÁ
ÁÁ
105
0°
104
30°
AVD
103
60°
102
90°
Phase Shift
10
120°
1
150°
0.1
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification
106
180°
10 M
Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
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27
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
VDD = 10 V
RL = 10 k Ω
TA = 25°C
ÁÁ
ÁÁ
ÁÁ
105
0°
104
30°
AVD
103
60°
102
90°
Phase Shift
10
120°
1
150°
0.1
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification
106
180°
10 M
Figure 33
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
53°
50°
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
52°
48°
φ m − Phase Margin
φ m − Phase Margin
51°
50°
49°
48°
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
47°
46°
2
4
6
8
10
12
VDD − Supply Voltage − V
14
44°
42°
45°
0
46°
16
40°
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 35
Figure 34
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
28
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
VDD = 5 V
VI = 10 mV
TA = 25°C
See Figure 3
φ m − Phase Margin
45°
40°
35°
30°
25°
0
10
20
30 40 50 60 70 80
CL − Capacitive Load − pF
90 100
Vn − Equivalent Input Noise Voltage − nV/ Hz
400
50°
VDD = 5 V
RS = 20 Ω
TA = 25°C
See Figure 2
300
200
100
0
1
10
100
f − Frequency − Hz
1000
Figure 37
Figure 36
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29
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
single-supply operation
While the TLC274 and TLC279 perform well using dual power supplies (also called balanced or split supplies),
the design is optimized for single-supply operation. This design includes an input common-mode voltage range
that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage
range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for
TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC274 and TLC279 permits the use of very large resistive values to implement
the voltage divider, thus minimizing power consumption.
The TLC274 and TLC279 work well in conjunction with digital logic; however, when powering both linear devices
and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
VREF = VDD
R2
VI
−
R3
R4 + V
VO = (VREF − VI )
REF
R2
VO
+
VREF
R3
R1 + R3
C
0.01 µF
Figure 38. Inverting Amplifier With Voltage Reference
−
VO
Logic
Logic
Logic
Power
Supply
+
(a) COMMON SUPPLY RAILS
−
Logic
Logic
Logic
+
VO
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common Versus Separate Supply Rails
30
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Power
Supply
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
input characteristics
The TLC274 and TLC279 are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially
in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD − 1 V at TA = 25°C and at VDD − 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC274 and TLC279 very
good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift
in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC274 and
TLC279 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC274 and TLC279 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
VO
+
(b) INVERTING AMPLIFIER
VI
+
−
−
+
(a) NONINVERTING AMPLIFIER
VI
−
VI
VO
VO
(c) UNITY-GAIN AMPLIFIER
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC274 and TLC279 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC274 and TLC279 were measured using a 20-pF load. The devices drive
higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at
lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding
a small amount of resistance in series with the load capacitance alleviates the problem.
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
output characteristics (continued)
(a) CL = 20 pF, RL = NO LOAD
(b) CL = 130 pF, RL = NO LOAD
2.5 V
−
VO
+
VI
CL
TA = 25°C
f = 1 kHz
VIPP = 1 V
−2.5 V
(c) CL = 150 pF, RL = NO LOAD
(d) TEST CIRCUIT
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC274 and TLC279 possess excellent high-level output voltage and current capability, methods
for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor
(RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the
use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between
approximately 60 Ω and 180 Ω, depending on how hard the op amp input is driven. With very low values of RP,
a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain load to N4 and the gain
of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current.
32
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APPLICATION INFORMATION
output characteristics (continued)
VDD
C
+
IP
RP
VO
−
−
VI
IF
Rp =
+
R2
R1
VO
IL
RL
VDD − VO
IF + IL + IP
Figure 43. Compensation for
Input Capacitance
IP = Pullup current required
by the operational amplifier
(typically 500 µA)
Figure 42. Resistive Pullup to Increase VOH
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic discharge protection
The TLC274 and TLC279 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents
functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be
exercised, however, when handling these devices as exposure to ESD may result in the degradation of the
device parametric performance. The protection circuit also causes the input bias currents to be
temperature-dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC274 and
TLC279 inputs and outputs were designed to withstand − 100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
10 kΩ
10 kΩ
0.016 µF
−
10 kΩ
1/4
TLC274
10 kΩ
1/4
TLC274
5V
−
10 kΩ
−
VI
0.016 µF
1/4
TLC274
Low Pass
+
+
+
HIgh Pass
5 kΩ
Band Pass
R = 5 kΩ (3/d−1)
(see Note A)
NOTE A: d = damping factor, 1/Q
Figure 44. State-Variable Filter
12 V
VI
+
1/4
TLC274
H.P.
5082 - 2835
+
1/4
TLC274
−
0.5 µF
Mylar
N.O.
Reset
−
Figure 45. Positive-Peak Detector
34
POST OFFICE BOX 655303
VO
• DALLAS, TEXAS 75265
100 kΩ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
VI
(see Note A)
100 kΩ
1.2 kΩ
4.7 kΩ
−
TL431
1 kΩ
1/4
TLC274
20 kΩ
0.1 µF
0.47 µF
TIP31
15 Ω
+
TIS193
250 µF,
25 V
+
−
VO
(see Note B)
10 kΩ
47 kΩ
0.01 µF
110 Ω
22 kΩ
NOTES: B. VI = 3.5 V to 15 V
C. VO = 2 V, 0 to 1 A
Figure 46. Logic-Array Power Supply
VO (see Note A)
9V
10 kΩ
0.1 µF
9V
C
100 kΩ
−
1/4
TLC274
R2
1/4
TLC274
10 kΩ
VO (see Note B)
+
100 kΩ
fO =
R1
47 kΩ
R1
1
4C(R2) R2
R3
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 47. Single-Supply Function Generator
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
5V
VI −
+
10 kΩ
1/4
TLC279
100 kΩ
−
−
1/4
TLC279
VO
+
10 kΩ
−
10 kΩ
1/4
TLC279
R1, 10 kΩ
(see Note A)
+
VI +
95 kΩ
−5 V
NOTE C: CMRR adjustment must be noninductive.
Figure 48. Low-Power Instrumentation Amplifier
5V
−
R
10 MΩ
R
10 MΩ
1/4
TLC274
VO
+
VI
2C
540 pF
f NOTCH +
R/2
5 MΩ
C
270 pF
1
2pRC
C
270 pF
Figure 49. Single-Supply Twin-T Notch Filter
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC274ACD
ACTIVE
SOIC
D
14
50
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274AC
Samples
TLC274ACDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274AC
Samples
TLC274ACN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC274ACN
Samples
TLC274ACNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC274ACN
Samples
TLC274AID
ACTIVE
SOIC
D
14
50
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274AI
Samples
TLC274AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274AI
Samples
TLC274AIN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC274AIN
Samples
TLC274BCD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274BC
Samples
TLC274BCDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274BC
Samples
TLC274BCDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274BC
Samples
TLC274BCN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC274BCN
Samples
TLC274BCNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC274BCN
Samples
TLC274BCNS
ACTIVE
SO
NS
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274B
Samples
TLC274BID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274BI
Samples
TLC274BIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274BI
Samples
TLC274BIDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274BI
Samples
TLC274BIN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC274BIN
Samples
TLC274CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274C
Samples
TLC274CDB
ACTIVE
SSOP
DB
14
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P274
Samples
TLC274CDBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P274
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC274CDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274C
Samples
TLC274CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274C
Samples
TLC274CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC274CN
Samples
TLC274CNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC274CN
Samples
TLC274CNS
ACTIVE
SO
NS
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274
Samples
TLC274CNSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC274
Samples
TLC274CPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P274
Samples
TLC274CPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P274
Samples
TLC274CPWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P274
Samples
TLC274ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274I
Samples
TLC274IDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274I
Samples
TLC274IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC274I
Samples
TLC274IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC274IN
Samples
TLC274INE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC274IN
Samples
TLC274IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
P274
Samples
TLC274IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y274
Samples
TLC274MD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
TLC274M
Samples
TLC274MDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
TLC274M
Samples
TLC274MDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
TLC274M
Samples
TLC279CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC279C
Samples
TLC279CDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC279C
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC279CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC279C
Samples
TLC279CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC279CN
Samples
TLC279ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC279I
Samples
TLC279IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC279I
Samples
TLC279IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC279IN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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