SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
D Input Offset Voltage Drift . . . Typically
D
D
D
D Low Noise . . . 68 nV/√Hz Typically at
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 5 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix
and I-Suffix Types)
D
D
D
D
D
f = 1 kHz
Output Voltage Range Includes Negative
Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up Immunity
description
The TLC27L1 operational amplifier combines a wide range of input offset-voltage grades with low offset-voltage
drift and high input impedance. In addition, the TLC27L1 is a low-bias version of the TLC271 programmable
amplifier. These devices use the Texas Instruments silicon-gate LinCMOS technology, which provides
offset-voltage stability far exceeding the stability available with conventional metal-gate processes.
Three offset-voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27L1
(10 mV) to the TLC27L1B (2 mV) low-offset version. The extremely high input impedance and low bias currents,
in conjunction with good common-mode rejection and supply voltage rejection, make these devices a good
choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are all easily designed with the TLC27L1. The
devices also exhibit low-voltage single-supply operation, making them ideally suited for remote and
inaccessible battery-powered applications. The common-mode input-voltage range includes the negative rail.
The device inputs and output are designed to withstand − 100-mA surge currents without sustaining latch-up.
The TLC27L1 incorporates internal electrostatic-discharge (ESD) protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric
performance.
AVAILABLE OPTIONS
PACKAGE
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
0°C
0
C to 70
70°C
C
2 mV
5 mV
10 mV
TLC27L1BCD
TLC27L1ACD
TLC27L1CD
PLASTIC
DIP
(P)
TLC27L1BCP
TLC27L1ACP
TLC27L1CP
−40°C
−40
C to 85°C
85 C
2 mV
5 mV
10 mV
TLC27L1BID
TLC27L1AID
TLC27L1ID
TLC27L1BIP
TLC27L1AIP
TLC27L1IP
−55°C to 125°C
10 mV
TLC27L1MD
TLC27L1MP
D OR P PACKAGE
(TOP VIEW)
OFFSET N1
IN −
IN +
GND
1
8
2
7
3
6
4
5
VDD
VDD
OUT
OFFSET N2
The D package is available taped and reeled. Add R suffix to the device type
(e.g., TLC27L1BCDR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments.
Copyright 1995 − 2005, Texas Instruments Incorporated
!"# $"%&
!
' #(
'"! ! $#!
!
$# )# # #* " #
' ' + ,( '"!
$!#
- '# #!#
&,
!&"'#
#
- && $ # # (
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
description (continued)
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from − 40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of − 55°C to 125°C.
equivalent schematic
VDD
P3
P12
P9A
R6
P4
P2
P1
P5
P9B
P11
R2
IN −
R1
P10
N5
IN +
N11
P6A
C1
R5
P6B
P7B
P7A
P8
N12
N3
N9
N6
N7
N1
N2
N4
R3
D1
D2
N13
R7
R4
OFFSET OFFSET
N1
N2
2
N10
OUT
POST OFFICE BOX 655303
GND
• DALLAS, TEXAS 75265
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
145 mW
P
1000 mW
8.0 mW/°C
640 mW
520 mW
200 mW
recommended operating conditions
Supply voltage, VDD
Common-mode input voltage, VIC
VDD = 5 V
VDD = 10 V
Operating free-air temperature, TA
POST OFFICE BOX 655303
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MAX
MIN
MAX
MIN
MAX
3
16
4
16
5
16
−0.2
3.5
−0.2
3.5
0
3.5
−0.2
8.5
−0.2
8.5
0
8.5
0
70
−40
85
−55
125
• DALLAS, TEXAS 75265
UNIT
V
V
°C
3
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
electrical characteristics at specified free-air temperature (unless otherwise noted)
TLC27L1C, TLC27L1AC, TLC27L1BC
TEST
CONDITIONS
PARAMETER
TA†
MIN
VDD = 5 V
TYP MAX
25°C
TLC27L1C
VIO
Input offset voltage
TLC27L1AC
VO = 1.4 V,
VIC = 0 V,
RS = 50 Ω,,
RI = 1 MΩ
TLC27L1BC
1.1
Full range
VDD = 10 V
TYP MAX
10
1.1
12
25°C
0.9
Full range
0.24
Full range
0.9
2
0.26
3
αVIO
0.1
60
0.1
60
Input offset current (see Note 4)
VO = VDD /2,
VIC = VDD /2
25°C
IIO
70°C
7
300
8
300
0.6
60
0.7
60
Input bias current (see Note 4)
VO = VDD /2,
VIC = VDD /2
25°C
IIB
70°C
40
600
50
600
VOH
VOL
AVD
CMRR
25°C
−0.2
to
4
Full range
−0.2
to
3.5
25°C
3.2
4.1
8
8.9
0°C
3
4.1
7.8
8.9
70°C
3
4.2
7.8
8.9
Common-mode input
voltage range (see Note 5)
High-level output voltage
Low-level output voltage
Large-signal differential
voltage amplification
Common-mode rejection ratio
VID = 100 mV,
RL= 1 MΩ
VID = −100 mV,
IOL = 0
RL= 1 MΩ,
MΩ
See Note 6
VIC = VICRmin
µV/°C
1
−0.3
to
4.2
−0.2
to
9
−0.3
to
9.2
−0.2
to
8.5
V
25°C
0
50
0
50
0°C
0
50
0
50
70°C
0
50
0
50
25°C
50
520
50
870
0°C
50
700
50
1030
70°C
50
380
50
660
25°C
65
94
65
97
0°C
60
95
60
97
70°C
60
95
60
97
25°C
70
97
70
97
0°C
60
97
60
97
70°C
60
98
60
98
dB
VI(SEL) = VDD
25°C
65
VO = VDD /2,
VIC = VDD /2,
No load
25°C
10
17
14
23
0°C
12
21
18
33
70°C
8
14
11
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
20
4
Supply current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
V/mV
Input current (BIAS SELECT)
IDD
pA
V
VDD = 5 V to 10 V,
VO = 1.4 V
II(SEL)
pA
V
Supply-voltage rejection ratio
(∆VDD /∆VIO)
kSVR
mV
2
Average temperature coefficient of
input offset voltage
VICR
1.1
5
6.5
3
25°C to
70°C
10
12
5
6.5
25°C
UNIT
MIN
dB
95
nA
µA
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
electrical characteristics at specified free-air temperature (unless otherwise noted)
TLC27L1I, TLC27L1AI, TLC27L1BI
TEST
CONDITIONS
PARAMETER
TA†
MIN
VDD = 5 V
TYP MAX
25°C
TLC27L1I
VIO
Input offset voltage
TLC27L1AI
VO = 1.4 V,
VIC = 0 V,
RS = 50 Ω,,
RL = 1 MΩ
TLC27L1BI
1.1
Full range
VDD = 10 V
TYP MAX
10
1.1
13
25°C
0.9
Full range
0.24
Full range
0.9
2
0.26
3.5
αVIO
0.1
60
0.1
60
Input offset current (see Note 4)
VO = VDD /2,
VIC = VDD /2
25°C
IIO
85°C
24
1000
26
1000
0.6
60
0.7
60
Input bias current (see Note 4)
VO = VDD /2,
VIC = VDD /2
25°C
IIB
85°C
200
2000
220
2000
VOH
VOL
AVD
CMRR
25°C
−0.2
to
4
Full range
−0.2
to
3.5
Common-mode input
voltage range (see Note 5)
High-level output voltage
Low-level output voltage
Large-signal differential
voltage amplification
Common-mode rejection ratio
VID = 100 mV,
RL= 1 MΩ
VID = − 100 mV,
IOL = 0
RL= 1 MΩ
See Note 6
VIC = VICRmin
µV/°C
1
−0.3
to
4.2
−0.2
to
9
−0.3
to
9.2
−0.2
to
8.5
25°C
3
4.1
8
8.9
−40°C
3
4.1
7.8
8.9
85°C
3
4.2
7.8
8.9
V
25°C
0
50
0
50
−40°C
0
50
0
50
85°C
0
50
0
50
25°C
50
520
50
870
−40°C
50
900
50
1550
85°C
50
330
50
585
25°C
65
94
65
97
−40°C
60
95
60
97
85°C
60
95
60
98
25°C
70
97
70
97
−40°C
60
97
60
97
85°C
60
98
60
98
dB
VI(SEL) = VDD
25°C
65
VO = VDD /2,
VIC = VDD /2,
No load
25°C
10
17
14
23
−40°C
16
27
25
43
85°C
17
13
10
† Full range is − 40 to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
18
Supply current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
V/mV
Input current (BIAS SELECT)
IDD
pA
V
VDD = 5 V to 10 V,
VO = 1.4 V
II(SEL)
pA
V
Supply-voltage rejection ratio
(∆VDD /∆VIO)
kSVR
mV
2
Average temperature coefficient
of input offset voltage
VICR
1.1
5
7
3.5
25°C to
85°C
10
13
5
7
25°C
UNIT
MIN
dB
95
nA
µA
5
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
electrical characteristics at specified free-air temperature (unless otherwise noted)
TLC27L1M
PARAMETER
VIO
Input offset voltage
TEST
CONDITIONS
VO = 1.4 V,
VIC = 0 V,
RS = 50 Ω,
RL = 1 MΩ
αVIO
Average temperature coefficient
of input offset voltage
IIO
Input offset current (see Note 4)
VO = VDD /2,
VIC = VDD /2
IIB
Input bias current (see Note 4)
VO = VDD /2,
VIC = VDD /2
TA†
25°C
VOL
AVD
CMRR
High-level output voltage
Low-level output voltage
Large-signal differential
voltage amplification
Common-mode rejection ratio
VID = − 100 mV,
IOL = 0
RL= 1 MΩ,
MΩ
See Note 6
VIC = VICRmin
10
1.1
10
12
12
1.4
25°C
0.1
60
0.1
60
pA
125°C
1.4
15
1.8
15
nA
25°C
0.6
60
0.7
60
pA
125°C
9
35
10
35
nA
0
to
4
µV/°C
1.4
−0.3
to
4.2
0
to
9
0
to
3.5
−0.3
to
9.2
V
0
to
8.5
V
25°C
3.2
4.1
8
8.9
−55°C
3
4.1
7.8
8.8
125°C
3
4.2
7.8
9
V
25°C
0
50
0
50
−55°C
0
50
0
50
125°C
0
50
0
50
25°C
50
520
50
870
−55°C
25
1000
25
1775
125°C
25
200
25
380
25°C
65
94
65
97
−55°C
60
95
60
97
125°C
60
85
60
91
25°C
70
97
70
97
−55°C
60
97
60
97
125°C
60
98
60
98
dB
VDD = 5 V to 10 V,
VO = 1.4 V
Input current (BIAS SELECT)
VI(SEL) = VDD
25°C
65
VO = VDD /2,
VIC = VDD /2,
No load
25°C
10
17
14
23
−55°C
17
30
28
48
125°C
7
12
9
† Full range is − 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
15
II(SEL)
IDD
6
Supply current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
V/mV
Supply-voltage rejection ratio
(∆VDD /∆VIO)
kSVR
UNIT
25°C to
125°C
Full range
VOH
VDD = 10 V
TYP MAX
MIN
mV
Common-mode input
voltage range (see Note 5)
VID = 100 mV,
RL= 1 MΩ
1.1
Full range
25°C
VICR
VDD = 5 V
MIN
TYP MAX
dB
95
nA
µA
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27L1C,
TLC27L1AC,
TLC27L1BC
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 33
VI(PP) = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 34
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
B1
φm
Unity-gain bandwidth
Phase margin
VI = 10 mV,
See Figure 35
VI = 10 mV,
CL = 20 pF,
RS = 20 Ω,
CL = 20 pF,
See Figure 33
CL = 20 pF,
f = B1,
See Figure 35
TYP
25°C
0.03
0°C
0.04
70°C
0.03
25°C
0.03
0°C
0.03
70°C
0.02
25°C
68
25°C
5
0°C
6
70°C
4.5
25°C
85
0°C
100
70°C
65
25°C
34°
0°C
36°
70°C
30°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
kHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27L1C,
TLC27L1AC,
TLC27L1BC
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
M ,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
VI(PP) = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 34
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
VI = 10 mV,
See Figure 35
CL = 20 pF,
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
B1
φm
Unity-gain bandwidth
Phase margin
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
25°C
0.05
0°C
0.05
70°C
0.04
25°C
0.04
0°C
0.05
70°C
0.04
25°C
68
25°C
1
0°C
1.3
70°C
0.9
25°C
110
0°C
125
70°C
90
25°C
38°
0°C
40°
70°C
34°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
kHz
7
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27L1I,
TLC27L1AI,
TLC27L1BI
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 33
VI(PP) = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 34
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
B1
φm
Unity-gain bandwidth
Phase margin
VI = 10 mV,
See Figure 35
VI = 10 mV,
CL = 20 pF,
RS = 20 Ω,
CL = 20 pF,
See Figure 33
CL = 20 pF,
f = B1,
See Figure 35
TYP
25°C
0.03
−40°C
0.04
85°C
0.03
25°C
0.03
−40°C
0.04
85°C
0.02
25°C
68
25°C
5
−40°C
7
85°C
4
25°C
85
−40°C
130
85°C
55
25°C
34°
−40°C
38°
85°C
28°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27L1C,
TLC27L1AC,
TLC27L1BC
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
M ,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
VI(PP) = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 34
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
VI = 10 mV,
See Figure 35
CL = 20 pF,
B1
φm
8
Unity-gain bandwidth
Phase margin
VI = 10 mV,l
CL = 20 pF,
POST OFFICE BOX 655303
f = B1,
See Figure 35
• DALLAS, TEXAS 75265
TYP
25°C
0.05
−40°C
0.06
85°C
0.03
25°C
0.04
−40°C
0.05
85°C
0.03
25°C
68
25°C
1
−40°C
1.4
85°C
0.8
25°C
110
−40°C
155
85°C
80
25°C
38°
−40°C
42°
85°C
32°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Slew rate at unity gain
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 33
VI(PP) = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 34
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
VI = 10 mV,
See Figure 35
CL = 20 pF,
B1
φm
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
TA
TLC27L1M
MIN
TYP
25°C
0.03
−55°C
0.04
125°C
0.02
25°C
0.03
−55°C
0.04
125°C
0.02
25°C
68
25°C
5
−55°C
8
125°C
3
25°C
85
−55°C
140
125°C
45
25°C
34°
−55°C
39°
125°C
25°
MAX
UNIT
V/ s
V/µs
nV/√Hz
kHz
kHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
VI(PP) = 1 V
SR
Slew rate at unity gain
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 33
VI(PP) = 5.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 34
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
VI = 10 mV,
See Figure 35
CL = 20 pF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
POST OFFICE BOX 655303
f = B1,
See Figure 35
• DALLAS, TEXAS 75265
TA
TLC27L1M
MIN
TYP
25°C
0.05
−55°C
0.06
125°C
0.03
25°C
0.04
−55°C
0.06
125°C
0.03
25°C
68
25°C
1
−55°C
1.5
125°C
0.7
25°C
110
−55°C
165
125°C
70
25°C
38°
−55°C
43°
125°C
29°
MAX
UNIT
V/ s
V/µs
nV/√Hz
kHz
kHz
9
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
10
VIO
αVIO
Input offset voltage
Distribution
1, 2
Temperature coefficient
Distribution
3, 4
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
vs Free-air temperature
5, 6
7
8
VOL
Low-level output voltage
vs Common-mode input voltage
vs Differential input voltage
vs Free-air temperature
vs Low-level output current
9, 10
11
12
13, 14
AVD
Large-signal differential voltage amplification
vs Supply voltage
vs Free-air temperature
vs Frequency
15
16
27, 28
IIB
IIO
Input bias current
vs Free-air temperature
17
Input offset current
vs Free-air temperature
17
VI
Maximum input voltage
vs Supply voltage
18
IDD
Supply current
vs Supply voltage
vs Free-air temperature
19
20
SR
Slew rate
vs Supply voltage
vs Free-air temperature
21
22
Bias-select current
vs Supply voltage
23
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
24
B1
Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
25
26
φm
Phase margin
vs Supply voltage
vs Free-air temperature
vs Capacitive load
29
30
31
Vn
Equivalent input noise voltage
vs Frequency
32
Phase shift
vs Frequency
27, 28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
Percentage of Units − %
60
ÏÏÏÏÏÏÏÏÏÏÏÏ
70
905 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA = 25°C
P Package
50
40
30
20
50
40
30
20
10
10
0
905 Amplifiers Tested From 6 Wafer Lots
VDD = 10 V
TA = 25°C
P Package
60
Percentage of Units − %
70
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
−5
−4
−3 −2 −1 0
1
2
3
VIO − Input Offset Voltage − mV
4
0
5
−5
−4
−3 −2 −1 0
1
2
3
VIO − Input Offset Voltage − mV
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
70
70
356 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 19.2 µV/°C
(1) 12.1 µV/°C
60
Percentage of Units − %
Percentage of Units − %
50
5
Figure 2
Figure 1
60
4
40
30
20
10
50
40
ÏÏÏÏÏÏ
356 Amplifiers Tested From 8 Wafer Lots
VDD = 10 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 18.7 µV/°C
(1) 11.6 µV/°C
30
20
10
0
−10 −8
−6
−4
−2
0
2
4
6
8
10
αVIO − Temperature Coefficient − µV/°C
0
2
4
6
8
−10 −8 −6 −4 −2 0
αVIO − Temperature Coefficient − µV/°C
Figure 3
10
Figure 4
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
16
ÁÁ
ÁÁ
ÁÁ
VID = 100 mV
TA = 25°C
4
VOH High-Level Output Voltage − V
VOH−
VOH High-Level Output Voltage − V
VOH−
5
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏÏ
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
2
ÁÁ
ÁÁ
ÁÁ
1
0
0
−2
−4
−6
−8
IOH − High-Level Output Current − mA
VID = 100 mV
TA = 25°C
14
VDD = 16 V
12
10
8
VDD = 10 V
6
4
2
0
0
−10
−5 −10 −15 −20 −25 −30 −35
IOH − High-Level Output Current − mA
Figure 6
Figure 5
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
−1.6
VID = 100 mV
RL = 1 MΩ
TA = 25°C
14
V
VOH−
OH High-Level Output Voltage − V
V
VOH−
OH High-Level Output Voltage − V
16
12
10
8
6
ÁÁÁ
ÁÁÁ
ÁÁÁ
4
2
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
ÁÁ
ÁÁ
ÁÁ
IOH = − 5 mA
VID = 100 mV
−1.7
VDD = 5 V
−1.8
−1.9
−2
VDD = 10 V
−2.1
−2.2
−2.3
−2.4
−75
−50
Figure 7
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 8
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
12
−40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
500
ÁÁ
ÁÁ
VDD = 5 V
IOL = 5 mA
TA = 25°C
650
VOL
VOL − Low-Level Output Voltage − mV
VOL
VOL − Low-Level Output Voltage − mV
700
600
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
550
VID = − 100 mV
500
450
450
400
VID = − 100 mV
VID = − 1 V
350
VID = − 2.5 V
ÁÁÁ
ÁÁÁ
400
VID = − 1 V
350
300
250
300
0
VDD = 10 V
IOL = 5 mA
TA = 25°C
1
2
3
VIC − Common-Mode Input Voltage − V
4
0
1
3
5
7
9
2
4
6
8
VIC − Common-Mode Input Voltage − V
Figure 10
Figure 9
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
900
IOL = 5 mA
VIC = VID/2
TA = 25°C
700
VOL
VOL − Low-Level Output Voltage − mV
VOL
VOL − Low-Level Output Voltage − mV
800
ÁÁ
ÁÁ
10
600
ÏÏÏÏ
ÏÏÏÏ
500
VDD = 5 V
400
300
ÁÁ
ÁÁ
ÁÁ
VDD = 10 V
200
100
0
0
−1
−2
−3
−4 −5
−6
−7
−8
−9 −10
800
IOL = 5 mA
VID = − 1 V
VIC = 0.5 V
700
ÏÏÏÏ
ÏÏÏÏ
VDD = 5 V
600
500
ÏÏÏÏ
ÏÏÏÏ
400
VDD = 10 V
300
200
100
0
−75
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
VID − Differential Input Voltage − V
Figure 12
Figure 11
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
1
VOL
VOL − Low-Level Output Voltage − V
0.9
0.8
VOL
VOL − Low-Level Output Voltage − V
VID = − 1 V
VIC = 0.5 V
TA = 25°C
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
ÁÁ
ÁÁ
2.5
0.2
0.1
0
0
1
2
3
4
5
6
7
VDD = 16 V
2
VDD = 10 V
1.5
ÁÁ
ÁÁ
ÁÁ
0.3
VID = − 1 V
VIC = 0.5 V
TA = 25°C
1
0.5
0
0
8
5
10
15
20
25
IOL − Low-Level Output Current − mA
IOL − Low-Level Output Current − mA
Figure 13
Figure 14
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
2000
2000
AVD
AVD− Large-Signal Differential
Voltage Amplification − V/mV
TA = − 55°C
1600
1400
TA = 0°C
1200
70°C
800
85°C
600
400
125°C
200
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
1600
1400
ÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
25°C
1000
14
RL = 1 MΩ
1800
− 40°C
AVD
AVD− Large-Signal Differential
Voltage Amplification − V/mV
RL = 1 MΩ
1800
Á
Á
Á
ÁÁ
ÁÁ
ÁÁ
16
VDD = 10 V
1200
1000
800
600
VDD = 5 V
400
200
0
−75
−50
Figure 15
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 16
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
14
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
FREE-AIR TEMPERATURE
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
16
VDD = 10 V
VIC = 5 V
See Note A
1000
ÏÏÏÏ
ÏÏÏÏ
TA = 25°C
ÏÏ
V I max − Maximum Input Voltage − V
IIB and I IO − Input Bias and Input Offsert
Currents − pA
10000
MAXIMUM INPUT VOLTAGE
vs
SUPPLY VOLTAGE
IIB
100
ÏÏ
ÏÏ
IIO
10
1
14
12
10
8
6
4
2
0
0.1
25
35
45
55
65
75
85
0
95 105 115 125
2
TA − Free-Air Temperature − °C
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
4
6
8
10
Figure 17
16
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
30
45
TA = − 55°C
VO = VDD/2
No Load
40
VO = VDD/2
No Load
25
ÏÏÏÏ
35
−40°C
30
25
0°C
ÏÏÏ
20
25°C
15
70°C
10
125°C
5
mA
A
IIDD
DD − Supply Current − µ
mA
A
IIDD
DD − Supply Current − µ
14
Figure 18
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
12
VDD − Supply Voltage − V
ÁÁ
ÁÁ
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
20
VDD = 10 V
15
10
VDD = 5 V
5
0
−75
−50
Figure 19
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 20
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
SLEW RATE
vs
SUPPLY VOLTAGE
0.07
0.07
AV = 1
VI(PP) = 1 V
RL = 1 MΩ
CL = 20 pF
TA= 25°C
See Figure 33
0.05
0.04
0.03
0.02
0.01
0.05
VDD = 10 V
VI(PP) = 1 V
0.04
0.03
VDD = 5 V
VI(PP) = 1 V
0.02
VDD = 5 V
VI(PP) = 2.5 V
0.01
0.00
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
0.00
−75
16
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 21
Bias-Select Current − nA
120
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
135
ÏÏÏÏÏ
ÏÏÏÏÏ
TA = 25°C
VI(SEL) = VDD
105
90
75
60
45
30
15
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
10
Á
9
8
7
6
5
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
TA = 125°C
TA = 25°C
TA = −55°C
VDD = 10 V
VDD = 5 V
4
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
3
RL = 1 MΩ
See Figure 33
2
1
0
0.1
1
10
f − Frequency − kHz
Figure 24
Figure 23
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
125
Figure 22
BIAS-SELECT CURRENT
vs
SUPPLY VOLTAGE
150
RL = 1 MΩ
CL = 20 pF
AV = 1
See Figure 33
VDD = 10 V
VI(PP) = 5.5 V
0.06
SR − Slew Rate − V/sµ s
0.06
SR − Slew Rate − V/sµ s
SLEW RATE
vs
FREE-AIR TEMPERATURE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
140
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 35
130
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 35
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
130
B1
B1 − Unity-Gain Bandwidth − kHz
B1
B1 − Unity-Gain Bandwidth − kHz
150
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
110
90
70
50
120
110
100
90
80
70
60
30
−75
50
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
0
125
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
Figure 26
Figure 25
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
VDD = 5 V
RL = 1 MΩ
TA = 25°C
ÁÁ
ÁÁ
105
0°
ÏÏÏ
104
30°
AVD
103
60°
ÏÏÏÏÏ
ÏÏÏÏÏ
102
90°
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
106
Phase Shift
101
1
0.1
1
10
100
1k
10 k
f − Frequency − Hz
120°
150°
100 k
180°
1M
Figure 27
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
VDD = 10 V
RL = 1 MΩ
TA = 25°C
ÁÁ
ÁÁ
105
0°
ÏÏÏÏ
104
30°
AVD
103
60°
ÏÏÏÏÏ
ÏÏÏÏÏ
102
90°
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
106
Phase Shift
101
1
0.1
1
10
120°
150°
100
1k
10 k
f − Frequency − Hz
100 k
180°
1M
Figure 28
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
42°
40°
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 35
Á
Á
36°
38°
φm
m − Phase Margin
φm
m − Phase Margin
40°
VDD = 5 mV
VI = 10 mV
CL = 20 pF
See Figure 35
38°
36°
34°
32°
30°
ÁÁ
ÁÁ
34°
28°
26°
24°
32°
22°
30°
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
20°
−75
−50
Figure 29
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 30
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS†
37°
VDD = 5 mV
VI = 10 mV
TA = 25°C
See Figure 35
φm
m − Phase Margin
35°
33°
ÁÁ
ÁÁ
ÁÁ
ÁÁ
31°
ÁÁ
ÁÁ
29°
27°
25°
0
10
20
30 40 50 60 70 80
CL − Capacitive Load − pF
90 100
VN
nV/ Hz
V n − Equivalent Input Noise Voltage − nV/Hz
PHASE MARGIN
vs
CAPACITIVE LOAD
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÏÏÏÏÏ
ÁÁÁÁÁ
ÏÏÏÏÏ
200
VDD = 5 V
RS = 20Ω
TA = 25°C
See Figure 34
175
150
125
100
75
50
25
0
10
100
f − Frequency − Hz
1
Figure 31
1000
Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC27L1 is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.
VDD
VDD +
−
−
VO
VO
CL
RL
VI
+
+
VI
CL
RL
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 33. Unity-Gain Amplifier
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits (continued)
2 kΩ
2 kΩ
VDD
20 Ω
VDD +
−
−
1/2 VDD
VO
VO
+
+
20 Ω
20 Ω
20 Ω
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 34. Noise-Test Circuit
10 kΩ
10 kΩ
VDD
−
VI
VDD +
100 Ω
−
100 Ω
VI
VO
VO
+
1/2 VDD
+
CL
CL
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 35. Gain-of-100 Inverting Amplifier
input bias current
Due to the high input impedance of the TLC27L1 operational amplifiers, attempts to measure the input bias
current can result in erroneous readings. The bias current at normal room ambient temperature is typically less
than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 36). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias-current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
20
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PARAMETER MEASUREMENT INFORMATION
8
5
V = VIC
1
4
Figure 36. Isolation Metal Around Device Inputs (JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise is necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. When conditions other than these are
to be used, please refer to the Typical Characteristics section of this data sheet.
input offset-voltage temperature coefficient
Erroneous readings often result from attempts to measure the temperature coefficient of input offset voltage.
This parameter is actually a calculation using input offset-voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset-voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the amplifier slew rate limits the output voltage swing, is often
specified two ways: full-linear response and full-peak response. The full-linear response is generally measured
by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until
the maximum frequency is found above which the output contains significant distortion. The full-peak response
is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output
swing cannot be maintained.
Since there is no industry-wide accepted value for significant distortion, the full-peak response is specified in
this data sheet and is measured using the circuit in Figure 33. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 37). A square wave allows a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
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21
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
full-power response (continued)
(a) f = 100 Hz
(b) BOM > f > 100 Hz
(c) f = BOM
(d) f > BOM
Figure 37. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices, and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
single-supply operation
VDD
R4
R1
VI
R2
−
VO
+
While the TLC27L1 performs well using dual
power supplies (also called balanced or split
supplies), the design is optimized for
single-supply operation. This includes an input
common-mode voltage range that encompasses
ground as well as an output voltage range that
pulls down to ground. The supply voltage range
extends down to 3 V (C-suffix types), thus allowing
operation with supply levels commonly available
for TTL and HCMOS; however, for maximum
dynamic range, 16-V single-supply operation is
recommended.
Vref
V
R3
C
0.01 µF
ref
V
O
+V
R3
DD R1 ) R3
+ (V
ref
* V ) R4 ) V
I R2
ref
Figure 38. Inverting Amplifier With Voltage
Reference
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference
level (see Figure 38). The low-input bias-current consumption of the TLC27L1 permits the use of very large
resistive values to implement the voltage divider, thus minimizing power consumption.
The TLC27L1 works well in conjunction with digital logic; however, when powering both linear devices and digital
logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device
supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.
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APPLICATION INFORMATION
single-supply operation (continued)
−
OUT
Logic
Logic
Power
Supply
Logic
+
(a) COMMON SUPPLY RAILS
−
Logic
+
OUT
Logic
Power
Supply
Logic
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common Versus Separate Supply Rails
input offset voltage nulling
The TLC27L1 offers external input-offset null control. Nulling of the input-offset voltage may be achieved by
adjusting a 25-kΩ potentiometer connected between the offset null terminals with the wiper connected as shown
in Figure 40. Total nulling may not be possible.
IN −
VDD
IN +
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
OUT
N2
+
N1
IN −
25 kΩ
IN +
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
OUT
N2
+
25 kΩ
N1
GND
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 40. Input Offset-Voltage Null Circuit
input characteristics
The TLC27L1 is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD − 1 V at TA = 25°C and at VDD − 1.5 V at all other temperatures.
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SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
input characteristics (continued)
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L1 very good input
offset-voltage drift characteristics relative to conventional metal-gate processes. Offset-voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The
offset-voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias-current requirements, the TLC27L1 is
well suited for low-level signal processing; however, leakage currents on printed circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance. It is good practice
to include guard rings around inputs (similar to those of Figure 36 in the Parameter Measurement Information
section). These guards should be driven from a low-impedance source at the same voltage level as the
common-mode input (see Figure 41).
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low-input bias-current requirements of the TLC27L1 results in a very-low noise current,
which is insignificant in most applications. This feature makes the devices especially favorable over bipolar
devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise
currents.
+
(a) NONINVERTING AMPLIFIER
VO
+
VO
(b) INVERTING AMPLIFIER
Figure 41. Guard-Ring Schemes
24
POST OFFICE BOX 655303
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
• DALLAS, TEXAS 75265
VI
+
−
VI
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
VI
−
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
(c) UNITY-GAIN AMPLIFIER
VO
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
feedback
Operational amplifier circuits almost always
employ feedback, and since feedback is the first
prerequisite for oscillation, a little caution is
appropriate. Most oscillation problems result from
driving capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 42). The value of this
capacitor is optimized empirically.
−
VO
+
electrostatic discharge protection
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Figure 42. Compensation for Input Capacitance
The TLC27L1 incorporates an internal ESD protection circuit that prevents functional failures at voltages up to
2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling
these devices as exposure to ESD may result in the degradation of the device parametric performance. The
protection circuit also causes the input bias currents to be temperature dependent and have the characteristics
of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L1 inputs
and output were designed to withstand − 100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails
as close to the device as possible.
The current path established when latch-up occurs is usually between the positive supply rail and ground and
can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the
supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and
the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance
of latch-up occurring increases with increasing temperature and supply voltages.
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SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
output characteristics
(a) CL = 20 pF, RL = NO LOAD
2.5 V
+
All operating characteristics of the TLC27L1 were
measured using a 20-pF load. The devices drive
higher capacitive loads; however, as output load
capacitance increases, the resulting response
pole occurs at lower frequencies, thereby causing
ringing, peaking, or even oscillation (see Figure
44). In many cases, adding some compensation
in the form of a series resistor in the feedback loop
alleviates the problem.
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
The output stage of the TLC27L1 is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this high
current capability can cause device damage
under certain conditions. Output current capability
increases with supply voltage (see Figure 43).
VI
VO
CL
TA = 25°C
f = 1 kHz
VI(PP) = 1 V
− 2.5 V
Figure 43. Test Circuit for Output
Characteristics
(b) CL = 260 pF, RL = NO LOAD
(c) CL = 310 pF, RL = NO LOAD
Figure 44. Effect of Capacitive Loads in Low-Bias Mode
Although the TLC27L1 possesses excellent high-level output voltage and current capability, methods are
available for boosting this capability, if needed. The simplest method involves the use of a pullup resistor (RP)
connected from the output to the positive supply rail (see Figure 45). There are two disadvantages to the use
of this circuit. First, the NMOS pulldown transistor, N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between
approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low
values of RP, a voltage offset from 0 V at the output occurs. Secondly, pullup resistor RP acts as a drain load
to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the
output current.
26
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SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VDD
−
VI
RP
IP
VO
+
IF
V –V
DD O
R +
P
I )I )I
F
L
P
IP = Pullup current required
by the operational amplifier
(typically 500 mA)
R2
IL
R1
RL
Figure 45. Resistive Pullup to Increase VOH
10 kΩ
10 kΩ
10 kΩ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5V
−
VI
TLC27L1
0.016 µF
0.016 µF
10 kΩ
+
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5V
−
10 kΩ
TLC27L1
+
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5V
−
TLC27L1
Low Pass
+
High Pass
5 kΩ
Band Pass
R = 5 kΩ(3/d-1)
(see Note A)
NOTE A: d = damping factor, I/O
Figure 46. State-Variable Filter
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27
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
VO (see Note A)
9V
C = 0.1 µF
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
9V
10 kΩ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
9V
100 kΩ
−
TLC27L1
R2
+
10 kΩ
VO (see Note B)
TLC27L1
+
R1, 100 kΩ
F
O
R3, 47 kΩ
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 47. Single-Supply Function Generator
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
+
VI
TLC27L1
VI
−
VDD
S1
C
A
Select
AV
S1
10
S2
100
S2
C
A
90 kΩ
X1
TLC4066
1
B
1
X2
2
9 kΩ
Analog
Switch
2
B
1 kΩ
NOTE A: VDD = 5 V to 12 V
Figure 48. Amplifier With Digital-Gain Selection
28
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+
ƪ ƫ
R1
1
4C(R2) R3
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5V
+
500 kΩ
TLC27L1
VO1
−
5V
500 kΩ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+
VO2
TLC27L1
−
0.1 µF
500 kΩ
500 kΩ
Figure 49. Multivibrator
10 kΩ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VDD
20 kΩ
VI
+
VO
TLC27L1
−
100 kΩ
NOTE A: VDD = 5 V to 16 V
Figure 50. Full-Wave Rectifier
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SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
APPLICATION INFORMATION
10 kΩ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VDD
100 kΩ
Set
+
100 kΩ
Reset
TLC27L1
−
33 Ω
NOTE A: VDD = 5 V to 16 V
Figure 51. Set/Reset Flip-Flop
0.016 µF
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5V
10 kΩ
10 kΩ
+
Vi
0.016 µF
TLC27L1
−
NOTE A: Normalized to FC = 1 kHz and RL = 10 kΩ
Figure 52. Two-Pole Low-Pass Butterworth Filter
30
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VO
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°−ā 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / B10/94
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Four center pins are connected to die mount pad.
Falls within JEDEC MS-012
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31
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC27L1ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC27L1AC
Samples
TLC27L1AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L1AI
Samples
TLC27L1BCD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
27L1BC
Samples
TLC27L1CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
27L1C
Samples
TLC27L1CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
27L1C
Samples
TLC27L1CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC27L1CP
Samples
TLC27L1ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L1I
Samples
TLC27L1IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L1I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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