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TLC555
SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
TLC555 LinCMOS™ Timer
1 Features
•
1
•
•
•
•
•
•
•
•
•
Very low power consumption:
– 1-mW typical at VDD = 5 V
Capable of operation in astable mode
CMOS output capable of swinging rail to rail
High output current capability
– Sink: 100-mA typical
– Source: 10-mA typical
Output fully compatible with CMOS, TTL, and
MOS
Low supply current reduces spikes during output
transitions
Single-supply operation from 2 V to 15 V
Functionally interchangeable with the NE555; has
same pinout
ESD protection exceeds 2000 V per MIL-STD883C, method 3015.2
Available in Q-temp automotive
– High-reliability automotive applications
– Configuration control and print support
– Qualification to automotive standards
2 Applications
•
•
•
•
•
•
•
Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator
Like the NE555, the TLC555 has a trigger level equal
to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of
the supply voltage. These levels can be altered by
use of the control voltage terminal (CONT). When the
trigger input (TRIG) falls below the trigger level, the
flip-flop is set and the output goes high. If TRIG is
above the trigger level and the threshold input
(THRES) is above the threshold level, the flip-flop is
reset and the output is low. The reset input (RESET)
can override all other inputs and can be used to
initiate a new timing cycle. If RESET is low, the flipflop is reset and the output is low. Whenever the
output is low, a low-impedance path is provided
between the discharge terminal (DISCH) and GND.
All unused inputs must be tied to an appropriate logic
level to prevent false triggering.
Device Information(1)
PART NUMBER
TLC555C
TLC555I
TLC555M
TLC555Q
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.38 mm
SOP (8)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.38 mm
LCCC (20)
8.89 mm × 8.89 mm
CDIP (8)
9.60 mm × 6.67 mm
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
CONT
5
RESET
4
VDD
8
3 Description
The TLC555 is a monolithic timing circuit fabricated
using the TI LinCMOS™ process. The timer is fully
compatible with CMOS, TTL, and MOS logic and
operates at frequencies up to 2 MHz. Because of its
high input impedance, this device supports smaller
timing capacitors than those supported by the NE555
or LM555. As a result, more accurate time delays and
oscillations are possible. Power consumption is low
across the full range of power-supply voltage.
PACKAGE
R
THRES
R1
6
3
R
OUT
1
S
R
TRIG
2
R
7
DISCH
1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC555
SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics: VDD = 2 V for TLC555C,
VDD = 3 V for TLC555I ............................................... 7
Electrical Characteristics: VDD = 5 V......................... 8
Electrical Characteristics: VDD = 15 V....................... 9
Operating Characteristics........................................ 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision H (August 2016) to Revision I
Page
•
Added MIN value for input voltage in Absolute Maximum Ratings ........................................................................................ 6
•
Added discharge pin in Absolute Maximum Ratings .............................................................................................................. 6
•
Changed MIN supply voltage based on part number in Recommended Operating Conditions............................................. 6
•
Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for
TLC555I .................................................................................................................................................................................. 7
•
Added trigger, threshold capacitance TYP value in Electrical Characteristics: VDD = 5 V ..................................................... 8
•
Changed VOH test condition current to –1 mA in Electrical Characteristics: VDD = 5 V.......................................................... 8
•
Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 5 V .................................................... 9
•
Added trigger, threshold capacitance TYP value in Electrical Characteristics: VDD = 15 V ................................................... 9
•
Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 15 V ................................................ 10
•
Added Operating Characteristics to the Specifications section............................................................................................ 11
•
Added Supply Current vs Supply Voltage chart to the Typical Characteristics section ....................................................... 12
•
Added Control Impedance vs Temperature chart to the Typical Characteristics section .................................................... 12
•
Added Output Low Resistance vs Temperature chart to the Typical Characteristics section.............................................. 12
•
Added Output High Resistance vs Temperature chart to the Typical Characteristics section............................................. 12
•
Added Propagation Delay vs Control Voltage chart, VDD = 2 V to the Typical Characteristics section ............................... 12
•
Added Propagation Delay vs Control Voltage chart, VDD = 5 V to the Typical Characteristics section ............................... 12
•
Changed trigger high hold time to 1 µs in the Monostable Operation section ..................................................................... 15
•
Changed minimum monostable pulse width to 1 µs in the Monostable Operation section.................................................. 15
•
Changed Output Pulse Duration vs Capacitance chart scale down to 0.001 ms in the Monostable Operation section...... 15
•
Added more astable frequency formulas to the Astable Operation section ......................................................................... 17
•
Changed scale on Free-Running Frequency vs Timing Capacitance chart up to 2 MHz in the Astable Operation section 18
•
Added CONT pin table note to the Function Table in the Device Functional Modes section .............................................. 19
•
Changed the application curve chart in the Pulse-Width Modulation section ...................................................................... 22
•
Changed the application curve charts in the Pulse-Position Modulation section ................................................................. 23
•
Added clamping diodes to Sequential Timer Circuit in the Sequential Timer section.......................................................... 24
2
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SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
Revision History (continued)
•
Added Designing for Improved ESD Performance section to the Application Information section ...................................... 25
Changes from Revision G (November 2008) to Revision H
Page
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 6
•
Deleted Dissipation Ratings table .......................................................................................................................................... 6
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5 Pin Configuration and Functions
D, P, PS, and JG Packages
8-Pin SOIC, PDIP, SOP, CDIP
Top View
1
8
VDD
TRIG
2
7
DISCH
OUT
3
6
THRES
RESET
4
5
CONT
GND
Pin Functions: D, P, PS, and JG Packages
PIN
I/O
DESCRIPTION
NAME
SOIC, PDIP,
SOP, CDIP
CONT
5
I
Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.
DISCH
7
O
Open collector output to discharge timing capacitor.
GND
1
—
Ground.
NC
—
—
No internal connection.
OUT
3
O
High current timer output signal.
RESET
4
I
Active low reset input forces output and discharge low.
THRES
6
I
End of timing input. THRES > CONT sets output low and discharge low.
TRIG
2
I
Start of timing input. TRIG < 1/2 CONT sets output high and discharge open.
VDD
8
—
4
Power-supply voltage.
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SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
PW Package
14-Pin TSSOP
Top View
OUT
5
THRES
10
NC
6
9
NC
RESET
7
8
CONT
19 NC
NC
4
18
NC
TRIG
5
17
DISCH
NC
6
16
NC
OUT
7
15
THRES
NC
8
14
NC
13
NC
NC
11
NC
4
1
NC
20 VDD
DISCH
11
12
12
3
NC
TRIG
CONT
NC
NC
13
GND
2
2
NC
9
VDD
10
14
NC
1
RESET
GND
3
FK Package
20-Pin LCCC
Top View
Pin Functions: PW and FK
PIN
NAME
I/O
DESCRIPTION
TSSOP
LCCC
CONT
8
12
I
Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.
DISCH
12
17
O
Open-collector output to discharge timing capacitor.
GND
1
2
—
Ground.
2, 4, 6,
9, 11, 13
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
—
No internal connection.
NC
OUT
5
7
O
High current timer output signal.
RESET
7
10
I
Active low reset input forces output and discharge low.
THRES
10
15
I
End of timing input. THRES > CONT sets output low and discharge low.
TRIG
3
5
I
Start of timing input. TRIG < 1/2 CONT sets output high and discharge open.
VDD
14
20
—
Power-supply voltage.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)Continuous total power dissipation and lead temperature
parameters from Absolute Maximum Ratings
Voltage
Current
MIN
MAX
Supply, VDD (2)
–0.3
18
Input, any input
–0.3
VDD
Discharge
–0.3
18
Sink, discharge or output
150
Source, output, IO
15
Operating, TA
Temperature
Case, for 60 seconds
C-suffix
0
I-suffix
–40
85
Q-suffix
–40
125
M-suffix
–55
125
FK package
–65
150
–65
150
Storage, Tstg
(1)
(2)
UNIT
V
mA
70
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network GND.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD
Operating free-air
temperature, TA
MIN
MAX
TLC555C
2
15
TLC555I
3
15
TLC555M
5
15
TLC555Q
5
15
TLC555C
0
70
TLC555I
–40
85
TLC555M
–55
125
TLC555Q
–40
125
UNIT
V
°C
6.3 Thermal Information
TLC555
THERMAL METRIC
(1)
D
(SOIC)
FK
(LCCC)
JG
(CDIP)
P
(PDIP)
PS
(SOP)
PW
(TSSOP)
UNIT
8 PINS
20 PINS
8 PINS
8 PINS
8 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
113
n/a
120
58
120
135
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58
37
81
48
72
61
°C/W
RθJB
Junction-to-board thermal resistance
55
36
110
35
69
77
°C/W
ψJT
Junction-to-top characterization
parameter
11
n/a
45
26
32
12
°C/W
ψJB
Junction-to-board characterization
parameter
54
n/a
103
35
68
77
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
4.3
31
n/a
n/a
n/a
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
TLC555C
25°C
VIT
Threshold voltage
Full range
25°C
IIT
Threshold current
Max
Trigger voltage
Full range
25°C
II(TRIG)
Trigger current
Max
Reset voltage
Full range
Control voltage (open-circuit) as a
Max
percentage of supply voltage
IOL = 1 mA, 25°C
Discharge switch on-stage
voltage
IOL = 1 mA, Full range
25°C
Discharge switch off-stage
current
Max
IOH = –300 µA, 25°C
VOH
High-level output voltage
IOH = –300 µA,
Full range
IOL = 1 mA, 25°C
VOL
Low-level output voltage
IOL = 1 mA, Full range
25°C
IDD
Supply current (2)
Full range
CPD
(1)
(2)
(3)
(4)
Power dissipation
capacitance (3) (4)
25°C
MAX
1.33
1.65
TLC555I
1.6
2.4
TLC555C
0.85
1.75
TLC555I
1.5
UNIT
V
2.5
TLC555C
10
TLC555I
10
TLC555C
75
pA
150
TLC555C
0.4
0.67
0.95
TLC555I
0.71
1
1.29
TLC555C
0.3
TLC555I
0.61
V
1.05
1.39
TLC555C
10
TLC555I
10
TLC555C
75
TLC555I
25°C
VI(RESET)
TYP
TLC555I
25°C
VI(TRIG)
MIN
0.95
pA
150
TLC555C
0.4
1.1
1.5
TLC555I
0.4
1.1
1.5
TLC555C
0.3
TLC555I
0.3
V
2
1.8
TLC555C
66.7%
TLC555I
66.7%
TLC555C
0.03
TLC555I
0.03
TLC555C
0.2
0.2
V
0.25
TLC555I
0.375
TLC555C
0.1
TLC555I
0.1
TLC555C
0.5
TLC555I
120
TLC555C
1.5
1.9
TLC555I
2.5
2.85
TLC555C
1.5
TLC555I
2.5
TLC555C
0.07
TLC555I
0.07
TLC555C
nA
V
0.3
0.3
V
0.35
TLC555I
0.4
TLC555C
250
TLC555I
250
TLC555C
400
TLC555I
µA
500
TLC555C
80
TLC555I
90
pF
Full range is 0°C to 70°C the for TLC555C, and –40°C to 85°C for the TLC555I. For conditions shown as Max, use the appropriate
value specified in the Recommended Operating Conditions table.
These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
CPD is used to determine the dynamic power consumption.
PD = VDD2 fo (CPD + CL) where fo = output frequency, CL = output load capacitance, VDD = supply voltage
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6.5 Electrical Characteristics: VDD = 5 V
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
VIT
MIN
TYP
MAX
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
2.8
3.3
3.8
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
2.7
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
Threshold voltage
IIT
Threshold current
Max
V
II(TRIG)
TLC555C
75
TLC555I
150
25°C
1.36
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
1.26
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
TLC555I
150
Trigger current
Max
CI
VI(RESET)
Reset voltage
II(RESET)
Discharge switch off-stage
current
VOH
VOL
(1)
8
High-level output voltage
Low-level output voltage
V
5000
25°C
2.1
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
0.4
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
0.3
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
1.1
1.5
10
TLC555C
75
TLC555I
150
5000
66.7%
IOL = 10 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
0.14
IOL = 10 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
pA
0.5
V
0.6
0.1
TLC555C
0.5
TLC555I
120
TLC555M, TLC555Q
120
IOH = –1 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
4.1
IOH = –1 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
4.1
IOL = 8 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 8 mA,
Full range
pF
V
TLC555C, TLC555I,
TLC555M, TLC555Q
Max
pA
1.8
TLC555M, TLC555Q
Control voltage (open circuit) as a
Max
percentage of supply voltage
1.96
2.06
TLC555C, TLC555I,
TLC555M, TLC555Q
Max
Discharge switch on-stage
voltage
1.66
TLC555M, TLC555Q
Reset current
pA
5000
TLC555C, TLC555I,
TLC555M, TLC555Q
Trigger voltage
Trigger, threshold capacitance
(each pin)
3.9
10
TLC555M, TLC555Q
VI(TRIG)
UNIT
nA
4.8
V
0.21
0.4
TLC555C
0.5
TLC555I
0.5
TLC555M, TLC555Q
0.6
V
Full range is 0°C to 70°C the for TLC555C, –40°C to 85°C for the TLC555I, –40°C to 125°C for the TLC555Q, and –55°C to 125°C for
the TLC555M. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.
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Electrical Characteristics: VDD = 5 V (continued)
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
IOL = 5 mA, 25°C
MIN
TLC555C, TLC555I,
TLC555M, TLC555Q
TYP
MAX
0.13
0.3
TLC555C
IOL = 5 mA,
Full range
VOL
0.4
TLC555I
0.4
TLC555M, TLC555Q
Low-level output voltage
IOL = 3.2 mA, 25°C
IOL = 3.2 mA,
Full range
0.45
TLC555C, TLC555I,
TLC555M, TLC555Q
0.08
TLC555C
0.35
TLC555I
0.35
IDD
Supply current
Full range
Power dissipation
capacitance (3) (4)
CPD
(2)
(3)
(4)
0.4
TLC555C, TLC555I,
TLC555M, TLC555Q
(2)
170
350
TLC555C
500
TLC555I
600
TLC555M, TLC555Q
700
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
V
0.3
TLC555M, TLC555Q
25°C
UNIT
115
µA
pF
These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
CPD is used to determine the dynamic power consumption.
PD = VDD2 fo (CPD + CL) where fo = output frequency, CL = output load capacitance, VDD = supply voltage
6.6 Electrical Characteristics: VDD = 15 V
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
VIT
MIN
TYP
MAX
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
9.45
10
10.55
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
9.35
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
Threshold voltage
IIT
Threshold current
Max
V
TLC555C
75
TLC555I
150
II(TRIG)
25°C
4.65
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
4.55
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
Trigger current
Max
Trigger, threshold capacitance
(each pin)
CI
VI(RESET)
II(RESET)
V
10
TLC555C
75
TLC555I
150
5000
25°C
1.8
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
0.4
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
0.3
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
Reset current
1.1
pA
pF
1.5
V
1.8
10
TLC555C
75
TLC555I
150
TLC555M, TLC555Q
5.35
5.45
TLC555C, TLC555I,
TLC555M, TLC555Q
Max
(1)
5
TLC555M, TLC555Q
Reset voltage
pA
5000
TLC555C, TLC555I,
TLC555M, TLC555Q
Trigger voltage
10.65
10
TLC555M, TLC555Q
VI(TRIG)
UNIT
pA
5000
Full range is 0°C to 70°C for TLC555C, –40°C to 85°C for TLC555I, –40°C to 125°C for the TLC555Q, and –55°C to 125°C for
TLC555M. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.
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Electrical Characteristics: VDD = 15 V (continued)
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
Control voltage (open circuit) as a
Max
percentage of supply voltage
Discharge switch on-stage
voltage
Discharge switch off-stage
current
VOH
High-level output voltage
IOL = 100 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
0.77
IOL = 100 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
Max
0.5
TLC555I
120
TLC555M, TLC555Q
120
12.5
IOH = –10 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
12.5
IOH = –5 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
13.5
IOH = –5 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
13.5
IOH = –1 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
14.2
IOH = –1 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
14.2
IOL = 100 mA, 25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 10 mA, 25°C
14.6
V
14.9
1.28
IDD
Supply current (2)
Full range
3.6
TLC555I
3.7
TLC555M, TLC555Q
3.8
0.63
CPD
(2)
(3)
(4)
10
25°C
1
TLC555C
1.3
TLC555I
1.4
TLC555M, TLC555Q
1.5
TLC555C, TLC555I,
TLC555M, TLC555Q
0.12
TLC555C, TLC555I,
TLC555M, TLC555Q
0.3
0.4
0.45
360
600
TLC555C
800
TLC555I
900
TLC555C, TLC555I,
TLC555M, TLC555Q
V
0.4
TLC555I
TLC555M, TLC555Q
Power dissipation
capacitance (3) (4)
3.2
TLC555C
TLC555M, TLC555Q
25°C
nA
14.2
TLC555C
IOL = 10 mA,
Full range
1.7
0.1
TLC555C
TLC555C, TLC555I,
TLC555M, TLC555Q
UNIT
V
IOH = –10 mA, 25°C
IOL = 50 mA,
Full range
MAX
1.8
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 50 mA, 25°C
Low-level output voltage
TYP
66.7%
IOL = 100 mA,
Full range
VOL
MIN
TLC555C, TLC555I,
TLC555M, TLC555Q
µA
1000
140
pF
These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
CPD is used to determine the dynamic power consumption.
PD = VDD2 fo (CPD + CL) where fo = output frequency, CL = output load capacitance, VDD = supply voltage
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6.7 Operating Characteristics
VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TYP
MAX
VDD = 5 V to 15 V, CT = 0.1 μF
RA = RB = 1 kΩ to 100 kΩ (2)
1%
3%
Supply voltage sensitivity of timing interval
VDD = 5 V to 15 V, CT = 0.1 μF
RA = RB = 1 kΩ to 100 kΩ (2)
0.1
0.5
%/V
tr
Output pulse rise time
RL = 10 MΩ, CL = 10 pF
20
75
ns
tf
Output pulse fall time
RL = 10 MΩ, CL = 10 pF
15
60
fmax
Maximum frequency in a-stable mode
RA = 470 Ω, CT = 200 pF RB = 200 Ω
Initial error of timing interval
(1)
(2)
TEST CONDITIONS
(1)
MIN
(2)
1.2
2.1
UNIT
ns
MHz
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
RA, RB, and CT are as defined in Figure 12.
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600
100
70
VDD = 2 V, IO = 1 mA
Propagation Delay Times (ns)
Discharge Switch On-State Resistance (W)
6.8 Typical Characteristics
40
VDD = 5 V, IO = 10 mA
20
10
7
VDD = 15 V, IO = 100 mA
4
2
IO(on) ³ 1 mA
CL » 0
TA = 25°C
500
400
300
tPHL
200
100
tPLH
1
(1)
0
-75
-50
-25
0
25
50
75
100
0
125
4
2
6
8
10
12
14
16
18
20
Supply Voltage (V)
Temperature (°C)
Figure 1. Discharge Switch On-State Resistance vs
Free-Air Temperature
(1) The effects of the load resistance on these values must be
taken into account separately.
Figure 2. Propagation Delay Times to Discharge Output
From Trigger and Threshold Shorted Together
vs Supply Voltage
90
300
-55qC
-40qC
0qC
25qC
70qC
85qC
125qC
200
VDD
VDD
VDD
VDD
80
70
Impedance (k:)
Supply Current (PA)
250
150
100
60
50
40
50
30
0
0
2
4
6
8
10
Supply Voltage (V)
12
14
20
-75
16
-25
0
25
50
Temperature (qC)
75
100
125
D002
Figure 4. Control Impedance vs Temperature
90
450
70
= 2V, I O = 1mA
= 3V, I O = 1mA
= 5V, I O = 10mA
= 15V, I O = 100mA
VDD
VDD
VDD
VDD
400
Output Resistance (:)
VDD
VDD
VDD
VDD
80
Output Resistance (:)
-50
D001
Figure 3. Supply Current vs Supply Voltage
60
50
40
30
20
350
= 2V, I O = 300PA
= 3V, I O = 300PA
= 5V, I O = 1mA
= 15V, I O = 10mA
300
250
200
150
100
10
0
-75
-50
-25
0
25
50
Temperature (qC)
75
100
125
50
-75
D003
Figure 5. Output Low Resistance vs Temperature
12
= 2V
= 3V
= 5V
= 15V
-50
-25
0
25
50
Temperature (qC)
75
100
125
D004
Figure 6. Output High Resistance vs Temperature
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Typical Characteristics (continued)
100
TPLH VDD = 2V
TPHL VDD = 2V
50
30
20
Propogation Delay (Ps)
Propogation Delay (Ps)
100
10
5
3
2
1
0.5
0.3
0.2
0.1
0.4
0.6
0.8
1.0
1.2
1.4
Control Voltage (V)
1.6
1.8
2.0
TPLH VDD = 5V
TPHL VDD = 5V
50
30
20
10
5
3
2
1
0.5
0.3
0.2
0.1
0.5
1.0
D007
Figure 7. Propagation Delay vs Control Voltage
VDD = 2 V
1.5
2.0
2.5
3.0
3.5
Control Voltage (V)
4.0
4.5
5.0
D009
Figure 8. Propagation Delay vs Control Voltage
VDD = 5 V
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7 Detailed Description
7.1 Overview
The TLC555 is a precision timing device used for general-purpose timing applications up to 2.1 MHz. All inputs
are level sensitive not edge triggered inputs.
7.2 Functional Block Diagram
CONT
5
RESET
4
VDD
8
R
THRES
R1
6
3
R
OUT
1
S
R
TRIG
2
R
7
DISCH
1
GND
Pin numbers are for all packages except the PW and FK package. RESET can override TRIG, which can override
THRES (when CONT pin is 2/3 VDD).
The resistance of “R" resistors vary with VDD and temperature. The resistors match each other very well across VDD
and temperature for a temperature stable control voltage ratio.
7.3 Feature Description
7.3.1 Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the internal latch; the output goes high, and
discharge pin (DISCH) becomes open drain. Capacitor C then is charged through RA until the voltage across the
capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the
output of the threshold comparator resets the internal latch, the output goes low, the discharge pin goes low
which quickly discharges capacitor C.
14
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Feature Description (continued)
V DD
(5 V to 15 V)
5
8
CONT
V DD
RA
4
7
6
2
Input
RESET
DISCH
OUT
3
Output
THRES
TRIG
GND
C
1
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 1 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 1 µs, which limits the minimum monostable pulse width
to 1 µs. The output pulse duration is approximately tw = 1.1 × RAC. Figure 11 is a plot of the time constant for
various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply
voltage, VDD. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is
constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
capacitor C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low
as long as the reset pulse is low. To prevent false triggering, when RESET is not used it must be connected to
VDD.
10000
5000
1k:
10k:
100k:
1M:
10M:
2000
1000
500
Input Voltage
Time (ms)
Voltage − 2 V/div
200
100
50
20
10
5
2
1
0.5
0.2
0.1
0.05
Output Voltage
0.02
0.01
0.005
0.002
0.001
0.01
Capacitor Voltage
Time − 0.1 ms/div
RA = 9.1 kΩ
CL = 0.01 µF
0.1 0.2 0.5 1 2 3 5 710 20
Capacitance (nF)
50 100
1000
D006
Figure 11. Output Pulse Duration vs Capacitance
See Figure 9
Figure 10. Typical Monostable Waveforms
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Feature Description (continued)
7.3.2 Astable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to
the threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through
RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and
RB.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈ 0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the monostable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
VDD
(5 V t o 15 V)
RA
RB
PF
Open
(see Note A) 5
CONT
4
RESET
7
DISCH
6
2
8
VDD
OUT
3
Output
t
H
THRES
TRIG
C
Voltage − 1 V/div
0.01
Output Voltage
tL
GND
1
Decoupling CONT voltage to ground with a capacitor can improve
operation. This should be evaluated for individual applications.
Figure 12. Circuit for Astable Operation
Capacitor Voltage
RA = 5 kΩ
See Figure 12
Time − 0.5 ms/div
RB = 3 kΩ
C = 0.15 µF
Figure 13. Typical Astable Waveforms
Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and
low-level duration tL for frequencies below 100 kHz can be calculated as follows:
tH = 0.693 (R A + RB )C
(1)
tL = 0.693 (RB )C
(2)
Other useful relationships are shown below:
16
period = tH + tL = 0.693 (R A + 2RB )C
(3)
1.44
frequency »
(R A +2RB )C
(4)
tL
RB
Output driver duty cycle =
=
tH + tL R A + 2RB
(5)
tH
RB
Output waveform duty cycle =
= 1tH + tL
R A + 2RB
(6)
t
RB
Low-to-high ratio = L =
tH R A + RB
(7)
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Feature Description (continued)
The formulas (1-7) do not account for any propagation delay times from the TRIG and THRES inputs to DISCH
output. These delay times add directly to the period and overcharge the capacitor which creates differences
between calculated and actual values that increase with frequency. In addition, the internal on-state resistance
ron during discharge adds to RB to provide another source of timing error in the calculation when RB is very low.
The equations below provide better agreement with measured values. The formulas Equation 8 represent the
actual low and high times when used at higher frequencies because propagation delay and discharge on
resistance is added to the formulas. Because the formulas are complex, a calculation tool, TLC555 Design
Calculator can be used to calculate the component values.
é
æ
öù
-tPLH
t c(H) = CT (R A + RB ) In ê3 - exp ç
÷ ú + tPHL
è CT (RB + ron ) ø ûú
ëê
é
æ
öù
-tPHL
t c(L) = CT (RB + ron ) In ê3 - exp ç
÷ ú + tPLH
êë
è CT (R A + RB ) ø úû
tc(H)
(8)
tc(L)
VDD
tPHL
2/3 VDD
1/3 VDD
GND
tPLH
Figure 14. Trigger and Threshold Voltage Waveform
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Feature Description (continued)
2000
1k:
10k:
100k:
1M:
10M:
1000
500
200
100
Frequency (kHz)
50
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1 0.2 0.5 1
2 3 5 710 20 50 100
Capacitance (nF)
1000
10000
D012
Figure 15. Free-Running Frequency vs Timing Capacitance
Resistance = RA + 2 × RB
7.3.3 Frequency Divider
Voltage − 2 V/div
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 16 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during
the timing cycle.
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
VCC = 5 V
See Figure 9
RA = 1250 Ω
C = 0.02 µF
Figure 16. Divide-by-Three Circuit Waveforms
18
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7.4 Device Functional Modes
Table 1 shows the device truth table.
Table 1. Function Table
RESET
VOLTAGE (1)
TRIGGER VOLTAGE (1)
THRESHOLD
VOLTAGE (1)
OUTPUT
DISCHARGE SWITCH
MAX
MAX
>MAX
>MAX
>MAX
>MAX
[maximum normal input high time].
20
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Typical Applications (continued)
Voltage − 2 V/div
8.2.1.3 Application Curve
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
VDD = 5 V
See Figure 18
RA = 1 kΩ
C = 0.1 µF
Figure 19. Timing Waveforms for Missing-Pulse Detector
8.2.2 Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 20 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 21 shows the resulting duty cycle versus control voltage transfer function. Attempting to
run under 10% duty cycle could result in inconsistent output pulses. Attempting to run close to 100% duty cycle
will result in frequency division by 2, then 3, then 4.
VDD (5 V to 15 V)
4
RESET
Clock
Input
2
RA
8
VDD
OUT
TRIG
3
Output
7
DISCH
Modulation
Input
(see Note A)
5
CONT
THRES
6
GND
1
A.
C
The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of
modulation source voltage and impedance on the bias of the timer.
Figure 20. Circuit for Pulse-Width Modulation
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Typical Applications (continued)
8.2.2.1 Design Requirements
The clock input must have VOL and VOH levels that are less than and greater than 1/3 VDD, respectively. Clock
input VOL time must be less than minimum output high time, therefore a high (positive) duty cycle clock is
recommended. Minimum recommended modulation voltage is 1 V. Lower CONT voltage can greatly increase
threshold comparator’s propagation delay and storage time. The application must be tolerant of a nonlinear
transfer function; the relationship between modulation input and pulse width is not linear because the capacitor
charge is RC based with an negative exponential curve.
8.2.2.2 Detailed Design Procedure
Choose RA and C so that RA × C is same or less than clock input period. Figure 21 shows the non linear
relationship between control voltage and output duty cycle. Duty cycle is function of control voltage and clock
period relative to RC time constant.
8.2.2.3 Application Curve
100
Clock period = 1 RC
Clock period = 2.5 RC
Output Duty Cycle (%)
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
Control Voltage (V)
3.5
4.0
4.5
D015
Figure 21. Pulse-Width-Modulation vs Control Voltage
Clock Duty Cycle 98%, VDD = 5 V
8.2.3 Pulse-Position Modulation
As shown in Figure 22, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and thereby the time delay of a free-running oscillator. Figure 23 and Figure 24
shows the output frequency and duty cycle versus control voltage.
22
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Typical Applications (continued)
VDD (5 V to 15 V)
4
RESET
2
RA
8
VDD
OUT
3
Output
TRIG
7
DISCH
Modulation
Input 5
(see Note A)
CONT
RB
6
THRES
GND
C
A.
The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of
modulation source voltage and impedance on the bias of the timer.
RA = 3 kΩ
RB = 309 kΩ
C = 1 nF
Figure 22. Circuit for Pulse-Position Modulation
8.2.3.1 Design Requirements
Both DC- and AC-coupled modulation input changes the upper and lower voltage thresholds for the timing
capacitor. Both frequency and duty cycle vary with the modulation voltage. Control voltage below 1 V could result
in output glitches instead of a steady output pulse stream
8.2.3.2 Detailed Design Procedure
The nominal output frequency and duty cycle for control voltage set to 2/3 of VDD can be determined using
formulas in Astable Operation section.
8.2.3.3 Application Curves
4
100
80
Output Duty Cycle (%)
Output Frequency (kHz)
3.5
3
2.5
2
1.5
60
40
20
1
0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Control Voltage (V)
4.0
4.5
5.0
0
0.5
D013
Figure 23. Pulse-Position-Modulation Frequency
vs Control Voltage, VDD = 5 V
1.0
1.5
2.0
2.5
3.0
3.5
Control Voltage (V)
4.0
4.5
5.0
D014
Figure 24. Pulse-Position-Modulation Duty Cycle
vs Control Voltage, VDD = 5 V
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Typical Applications (continued)
8.2.4 Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 25
shows a sequencer circuit with possible applications in many systems, and Figure 26 shows the output
waveforms.
VDD
4
RESET
33 k:
2
1N4148
VDD
3
OUT
TRIG
S
DISCH
5
0.01
PF
CONT
33 k:
RA
8
2
0.001 PF
7
1
6
0.01
PF
CA
CA = 10 PF
RA = 100 k:
TRIG
RB
8
VDD
3
OUT
DISCH 7
5
THRES
GND
4
RESET
CONT
THRES
GND
1
CB
Out pu t A
33 k:
1N4148
2
0.001 PF
4
RESET
8
VDD
3
OUT
TRIG
DISCH
5
6
CONT
0.01
PF
Out pu t B
CB = 4.7 PF
RB = 100 k:
THRES
GND
1
RC
7
6
CC
CC = 14.7 PF
RC = 100 k:
Out pu t C
NOTE: S closes momentarily at t = 0.
Figure 25. Sequential Timer Circuit
8.2.4.1 Design Requirements
The sequential timer application chains together multiple monostable timers. The joining components are the
33-kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next
monostable. A diode is needed to prevent over voltage on the trigger input when on the previous output's low to
high edge.
8.2.4.2 Detailed Design Procedure
The timing resistors and capacitors can be chosen using this formula: tw = 1.1 × R × C.
24
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Typical Applications (continued)
8.2.4.3 Application Curve
twA
Output A
twA = 1.1 RACA
Voltage − 5 V/div
twB
Output B
twB = 1.1 RBCB
Output C
twC
twC = 1.1 RCCC
t=0
t − Time − 1 s/div
See Figure 25
Figure 26. Sequential Timer Waveforms
8.2.5 Designing for Improved ESD Performance
The TLC555 internal HBM and CDM protection allows for safe assembly in ESD controlled environments. In
applications that may expose pins of the TLC555 to ESD, additional protection is highly recommended. The test
board schematic below has bypass capacitors, current-limiting resistors, and voltage clamping TVS diodes to
provide additional protection for commonly exposed pins [Reset, Trig, and Output] against ESD.
C5
R1
100k
TP1
50V
1000pF
D1
BAT54WSTR
R2
Reset
C9
2.20k
C1
50V
1000pF
D2
BAT54WSTR
R3
10.0k
50V
1000pF
D6
BAT54WSTR
U1
3
VDD
R5
10.0k
TLC555CP
R6
100k
C4
50V
0.1uF
C3
50V
1000pF
1
TRIG
10.0
D7
BAT54WSTR
TP3
Output
C10
50V
1000pF
C8
100V
0.01uF
50V
D4
1000pF
BAT54WSTR
TP2
Trig
10.0
5
THRES
C7
R4
RESET
DISCH
C6
50V
1000pF
R9
J1
R7
10.0k
Vcc
D5
BAT54WSTR
R8
10.0k
J2
C11
50V
10uF
C12
50V
0.1uF
D3
SMBJ15A-13-F
GND
Figure 27. ESD Test Schematic
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Product Folder Links: TLC555
25
TLC555
SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
www.ti.com
Typical Applications (continued)
The table below gives the ESD protection levels recorded for different supply voltages and external components
populated. Using only passive components to protect the TLC555 with a single 15-V supply is not recommended
because the higher voltage allows for an unacceptable amount of current to flow through the device.
Table 2. ESD test result table
Supply Voltage
(1)
Just passive components populated. D1..D7 not populated (1)
All components populated
5V
8 kV
12 kV
15 V
Not recommended
12 kV
(1)
Sample results. Results may vary with populated components, board layout, and samples used.
9 Power Supply Recommendations
The TLC555 requires a voltage supply greater than or equal to 2 V, 3 V, or 5 V based the coldest ambient
temperature supported and a supply voltage less than or equal to 15 V. Adequate power supply bypassing is
necessary to protect associated circuitry and provide stable output pulses. Minimum recommended is 0.1-μF
ceramic in parallel with 1-μF electrolytic. Place the bypass capacitors as close as possible to the TLC555 and
minimize the trace length.
26
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Product Folder Links: TLC555
TLC555
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SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
10 Layout
10.1 Layout Guidelines
Standard PCB rules apply to routing the TLC555. The 0.1-μF ceramic capacitor in parallel with a 1-μF electrolytic
capacitor must be as close as possible to the TLC555. The capacitor used for the time delay must also be placed
as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity
and signal integrity.
Figure 28 is the basic layout for various applications.
• C1—based on time delay calculations
• C2—0.01-μF bypass capacitor for control voltage pin
• C3—0.1-μF bypass ceramic capacitor
• C4—1-μF electrolytic bypass capacitor
• R1—based on time-delay calculations
10.2 Layout Example
C4
C3
GND
VDD
OUT
TLC555
R1
TRIG
DISCH
THRES
C1
RESET
CONT
C2
Figure 28. Layout Example
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Product Folder Links: TLC555
27
TLC555
SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
www.ti.com
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
LinCMOS, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Copyright © 1983–2019, Texas Instruments Incorporated
Product Folder Links: TLC555
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
(1)
TLC555CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL555C
TLC555CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL555C
TLC555CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL555C
TLC555CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL555C
TLC555CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC555CP
TLC555CPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC555CP
TLC555CPS
ACTIVE
SO
PS
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P555
TLC555CPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P555
TLC555CPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P555
TLC555CPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P555
TLC555CPWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P555
TLC555ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL555I
TLC555IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL555I
TLC555IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL555I
TLC555IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL555I
TLC555IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC555IP
TLC555IPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC555IP
TLC555QDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL555Q
TLC555QDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
The marketing status values are defined as follows:
Addendum-Page 1
TL555Q
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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