TLC5905PAP

TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 D D D D D D D D Drive Capability and Output Counts: – 80 mA (Current Sink) × 16 Bits – 120 mA (Current Sink) × 8 Bits Constant Current Output Range: – 5 mA to 80 mA/10 mA to 120 mA (Selectable by MODE Terminal) (Current Value Setting for All Output Terminals Using External Resistor and Internal Brightness Control Register) Constant Current Accuracy ± 4% (Maximum Error Between Bits) Voltage Applied to Constant Current Output Terminals: – Minimum 0.4 V (Output Current 5 mA to 40 mA) – Minimum 0.7 V (Output Current 40 mA to 80 mA) 256 Gray Scale Display: – Pulse Width Control 256 Steps Brightness Adjustment: – Output Current Adjustment for 32 Steps (Adjustment for Brightness Deviation Between LED Modules) – 8 Steps Brightness Control by 8 Times Speed Gray Scale Control Clock (Brightness Adjustment for Panel) Error Output Signal Check: – Check Error Output Signal Line Such as Protection Circuit When Operating Data Output Timing Selectable: – Select Data Output Timing for Shift Register Relative to Clock D D D D D D D D D D D D OVM (Output Voltage Monitor): – Monitor Voltage on Constant Current Output Terminals (Detect LED Disconnection and Short Circuit) WDT (Watchdog Timer): – Turn Output Off When Scan Signal Stopped TSD (Thermal Shut Down): – Turn Output Off When Junction Temperature Exceeds Limit Data Input: – Clock Synchronized 1 Bit Serial Input (Shmitt-Triggered Input) Data Output: – Clock Synchronized 1 Bit Serial Output (3-State Output) Input Signal Level: – CMOS Level Power Supply Voltage . . . 4.5 V to 5.5 V Maximum Output Voltage . . . 17 V Data Transfer Rate . . . 15 MHz (Max Gray Scale Clock Frequency . . . 8 MHz (Max) Operating Free-Air Temperature Range –20°C to 85°C 64-Pin HTQFP Package (PD = 4.9 W, TA = 25°C) description The TLC5905 is a constant current driver that incorporates shift register, data latch, constant current circuitry with a current value adjustable and 256 gray scale display that uses pulse width control. The output current can be selected as maximum 80 mA with 16 bits or 120 mA with 8 bit. The current value of the constant current output is set by one external resistor. After this device is mounted on a printed-circuit board (PCB), the brightness deviation between LED modules (ICs) can be adjusted using an external data input, and the brightness control for the panel can be accomplished by the brightness adjustment circuitry. Also, the device incorporates the output voltage monitor (OVM) used for LED open detection (LOD) by monitoring constant current output. Moreover, the device incorporates watchdog timer (WDT) circuitry, which turns constant current output off when the scan signal stops during dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns constant current output off when the junction temperature exceeds the limit. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 pin assignments NC OUT3 GNDLED OUT2 OUT1 GNDLED OUT0 NC NC BCENA GNDLOG MODE VCCLOG TSENA NC SIN PAP PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC OUT4 GNDLED OUT5 OUT6 GNDLED NC OUT7 OUT8 NC GNDLED OUT9 OUT10 GNDLED OUT11 NC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 NC OUT12 GNDLED OUT13 OUT14 GNDLED OUT15 NC IREF VCCLED WDCAP GNDANA NC VCCANA MCENA SOUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST2 SOMODE GSCLK BLANK RSEL1 RSEL0 SCLK XENABLE XOE WDTRG XLATCH XDOWN1 XDOWN2 TEST1 BOUT GSOUT TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 functional block diagram Shift Register and Data Latch OVM Shift Register Data Latch MCENA BCENA RSEL0 SOUT RSEL1 SIN XENABLE SCLK Controller SCLK Brightness Control Shift Register Data Latch SOMODE Gray Scale Control Shift Register Data Latch XOE XLATCH MODE GSCLK BLANK 8 bits Gray Scale Counter DELEY GSOUT DELEY BOUT 16 x 8 bits Comparator TSENA XDOWN1 TSD WDTRG WDCAP IREF XDOWN2 WDT Current Reference Circuit 16 bits Constant Current Driver OUT0 16 bits OVM Comp LATCH OUT15 NOTE: All the input terminals are with Schmitt-triggered inverter except IREF and WDCAP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 functional block diagram for shift register and data latch MCENA OVM Data Latch (1 x 8 bit) OVM Shift Register (8 x 1 bit) SIN BCENA Brightness Control Data Latch (1 x 8 bit) Gray Scale Control Data Latch (16 x 8 bit) SCLK Constant Current Driver Control Gray Scale Clock Counter Brightness Control Shift Register (8 x 1 bit) XLATCH XENABLE 16 bit OVM Comparator XDOWN1, 2 Output Driver 16 x 8 bit Data Comparator SCLK Controller Gray Scale Control Shift Register (128 x 1 bit / 64 x 1 bit) (see Note) MODE 1 bit S/R t u RSEL 0–1 SOMODE SOUT XOE NOTE: Enclosed in ( ) is dependent on MODE pin selection. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 equivalent input and output schematic diagrams Input VCCLOG INPUT GNDLOG SOUT, GSOUT, BOUT VCCLOG OUTPUT GNDLOG XDOWN1, XDOWN2 XDOWN1, XDOWN2 GNDLOG OUTn OUTn GNDLED POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 Terminal Functions ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME I/O DESCRIPTION BCENA 55 I Brightness control enable. When BCENA is low, the brightness control latch is set to the default value. The output current value in this status is 100% of the value set by an external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to brightness control latch is enabled. BLANK 45 I Blank(Light off). When BLANK is high, all the output of the constant current driver is turned off. The constant current output is turned on (LED on) when synchronized to the falling edge of GCLK after next rising edge of GCLK when BLANK goes from high to low. BOUT 34 O Blank signal delay. BOUT is an output with the addition of delay time to BLANK. GSCLK 46 I Clock input for gray scale. The gray scale display is accomplished by lighting the LED on until the number of GSCLK counted is equal to data latched. GNDANA 28 GNDLED 3,6,11,14, 19,22,59,62 GNDLOG 54 GSOUT 33 O Clock delay for gray scale. GSOUT is an output with the addition of delay time to GSCLK. IREF 25 I/O Constant current value setting. LED current is set to the desired value by connecting an external resistor between IREF and GND. The 37 times current is compared to current across the external resistor sink on the output terminal. MCENA 31 I OVM enable. When MCENA is low, the OVM latch is set to the default value. The comparison voltage in this status is 0.3 V. When MCENA is high, writing to OVM latch is enabled. MODE 53 I 8/16 bits select. When MODE is high, the 16 bits output is selected. When MODE is low, the 8 bits output is selected. NC OUT0 – OUT15 Analog ground (internally connected to GNDLOG and GNDLED) LED driver ground (internally connected to GNDANA and GNDLOG) Logic ground (internally connected to GNDANA and GNDLED) 1,7,10,16,17,24, 29,50,56,57,64 58,60,61,63, 2,4,5,8,9,12,13 15,18,20,21,23 No internal connection O Constant current output RSEL0 RSEL1 43 44 I Shift register data latch switching. When RSEL1 is low and RESL0 is low, gray scale data shift register latch is selected. When RSEL1 is low and RESL0 is high, the brightness control register latch is selected. When RSEL1 is high and RSEL0 is low, the OVM register latch is selected. When RSEL1 is high and RSEL0 high, no register latch is selected. SCLK 42 I Clock input for data transfer. The input data is from SIN. All data on the shift register selected by RSEL0 and RSEL1, and output data at SOUT are sifted by 1 bit synchronizing to SCLK. The data except the SOUT is synchronized to the rising edge. The edge for data from SOUT is determined by the level of SOMODE. SIN 49 I Input for 1 bit serial data. These terminals are inputs for shift register for gray scale data, brightness control and OVM. The register selected is determined by RSEL0, 1. SOMODE 47 I Timing select for data output. When SOMODE is low, SOUT is changed by synchronizing to the rising edge of SCLK. When SOMODE is high, SOUT is changed by synchronizing to the falling edge of SCLK. SOUT 32 O Output for 1 bit serial data with 3–state. These terminals are outputs for shift register for gray scale data, brightness control and OVM. The register selected is determined by RSEL0, 1. TEST1 TEST2 35 48 I TEST. Factory test terminal. TEST1 and TEST2 should be connected to GND for normal operation. THERMAL PAD TSENA 6 NO. package bottom 51 Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. I TSD (thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 Terminal Functions (Continued) ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME NO. I/O DESCRIPTION VCCANA VCCLOG 30 Analog power supply voltage 52 Logic power supply voltage VCCLED 26 LED driver power supply voltage WDCAP 27 I WDT (watchdog timer) detection time adjustment. WDT detection time is adjusted by connecting a capacitor between WDCAP and GND. When WDCAP is directly connected to GND, the WDT function is disabled. In this case, WDTRG should be tied to a high or low level. WDTRG 39 I WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan signal can be monitored by turning the constant current output off and protecting the LED from damage by burning when the scan signal is stopped during constant period designed. XDOWN1 37 O Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current output is shut down by the WDT or TSD function. XDOWN2 36 O OVM comparator output. XDOWN2 is configured as open collector. It monitors terminal voltage when constant current output is turned on. XDOWN2 goes low when this voltage is lower than the level selected by the OVM latch. When BLANK is set high, the previous level is held. XENABLE 41 I SCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the rising edge of SCLK after XENABLE goes low. During XENABLE high, no data is transferred. XLATCH 38 I Latch. When XLATCH is high, data on shift register goes through latch. When XLATCH is low, data is latched. Accordingly, if data on shift register is changed during XLATCH high, this new value is latched (level latch). XOE 40 I Data output enable. When XOE is low, the SOUT terminal is drived. When XOE is high, the SOUT terminal goes to high-impedance state. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Logic supply voltage, VCC(LOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage for constant current circuit, VCC(LED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Analog supply voltage, VCC(ANA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output current (DC), IOL(C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 mA Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC(LOG) + 0.3 V Output voltage range, V(SOUT), V(BOUT) and V(GSOUT) . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC(LOG) + 0.3 V Output voltage range, V(OUTn) and V(XDOWNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 W Power dissipation rating at (or above) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39.4 mW/°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GNDLOG terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ dc characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Logic supply voltage, VCC(LOG) 4.5 5 5.5 V Supply voltage for constant current circuit, VCC(LED) 4.5 5 5.5 V Analog power supply, VCC(ANA) 4.5 5 5.5 V – 0.3 0 0.3 V – 0.3 0 0.3 V 17 V VCC(LOG) 0.2 VCC(LOG) V Voltage between VCC, V(DIFF1) Voltage between GND, V(DIFF2) Voltage applied to constant current output, V(OUTn) V(DIFF1) = VCC(LOG) – VCC(ANA) VCC(LOG) – VCC(LED), VCC(ANA) – VCC(LED) V(DIFF2) = GNDLOG – GND(ANA) GND(LOG) – GND(LED), GND(ANA) – GND(LED) OUT0 to OUT15 off High-level input voltage, VIH 0.8 VCC(LOG) Low-level input voltage, VIL High-level output current, IOH Low level output current Low-level current, IOL Constant output current, IOL(C) GNDLOG VCC(LOG) = 4.5V, SOUT, BOUT, GSOUT VCC(LOG) = 4.5V, SOUT, BOUT, GSOUT – 1.0 1.0 VCC(LOG) = 4.5V, XDOWN1, XDOWN2 OUT0 to OUT15 Operating free–air temperature range, TA V mA 5 mA 5 80 mA – 20 85 °C ac characteristics, VCC(LOG) = VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = – 20 to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS SCLK clock frequency, frequency f(SCLK) MIN At cascade operation (SOMODE = L) 10 20 Frequency division ratio 1/1 20 Frequency division ratio 1/1 40 No GSOUT operation (see Note 2) 20 WDTRG clock frequency, f(WDT) 40 XLATCH pulse duration (high), tw(h) 50 Rise/fall time, tr/tf Setup time, tsu Hold time, th 10 BLANK – GSCLK 20 XENABLE – SCLK 15 XLATCH – SCLK 15 XLATCH – GSCLK 10 RSEL – SCLK 10 RSEL – XLATCH 20 SIN – SCLK 10 XENABLE – SCLK 20 XLATCH – SCLK 30 RSEL – SCLK 20 RSEL – XLATCH 20 NOTE 2: When GSCLK is operated with >8 MHz, GSOUT operation can not be assured. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MHz MHz ns ns 100 SIN – SCLK MHz ns 8 WDTRG pulse duration (high or low level), tw(h)/tw(l) UNIT ns 8 No GSOUT operation (see Note 2) GSCLK pulse duration (high or low level), level) tw(h) (h)/tw(l) (l) MAX 15 SCLK pulse duration (high or low level), tw(h)/tw(l) GSCLK clock frequency, frequency f(GSCLK) TYP At single operation ns ns ns TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 electrical characteristics, MIN/MAX:VCC(LOG)= VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = –20 to 85°C TYP: VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, TA = 25°C (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS MIN TYP MAX VCC(LOG) –0.5 UNIT VOH High-level output voltage IOH = –1 mA, SOUT, GSOUT, BOUT VOL Low level output voltage Low-level IOL = 1 mA, SOUT, GSOUT, BOUT IOL = 5 mA, XDOWN1, XDOWN2 0.5 II Input current ±1 µA I(LOG) Supply y current ((logic) g ) VI = VCC(LOG) or GND(LOG) Input signal is static, TSENA = H, WDCAP = OPEN 1 mA mA 0.5 Data transfer, SCLK = 15 MHz, GSCLK = 8 MHz I(ANA) I(LED) Supply current (analog) Supply current (constant current driver) V 18 30 LED turnon, R(IREF) = 590 Ω LED turnoff, R(IREF) = 590 Ω 3 5 3 5 LED turnoff, R(IREF) = 1180 Ω 15 20 LED turnoff, R(IREF) =590 Ω VO = 1 V, R(IREF) = 1180 Ω All output bits turn on 30 40 25 35 50 70 VO = 1 V, R(IREF) = 590 Ω All output bits turn on V mA mA IO(LC1) Constant output current VO = 1 V, V(IREF) = 1.24 V, R(IREF) = 1180 Ω 35 40 45 mA IO(LC2) Constant output current VO = 1, V(IREF) = 1.24V, R(IREF) = 590 Ω 70 80 90 mA IO(LK) ( ) Constant output leakage current 0.1 µA XDOWN1,2 (V(XDOWNn) = 15 V) 1 µA SOUT (VOUTn = VCC(LOG) or GND) 1 µA OUT0 to OUT15 (V(OUTn) = 15 V) ∆IO(LC) Constant output current error between bits VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, VO = 1V, R(IREF) = 590 Ω, All output bits turnon ±1% ±4% I∆O(LC1) Changes in constant output current depend on supply voltage VO = 1 V, R(IREF) = 1180 Ω, V(IREF) = 1.24 V, 1 bit output turnon ±1% ±4% %/V I∆O(LC2) Changes in constant output current depend on output voltage VO= 1 V to 3 V, R(IREF) = 1180 Ω, V(IREF) = 1.24 V, 1 bit output turnon ±1% ±2% %/V T(tsd) T(wdt) TSD detection temperature Junction temperature 150 160 170 °C WDT detection temperature No external capacitor 5 10 15 ms V(IREF) Voltage reference BCENA = L, R(IREF) = 590 Ω POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.24 V 9 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 switching characteristics, CL = 15pF, MIN/MAX: VCC(LOG)= VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = –20 to 85°C TYP: VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, TA = 25°C (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER tr TEST CONDITIONS Rise time MIN 12 30 GSOUT, BOUT 13 30 GSOUT, BOUT OUTn (see Figure 1) Propagation delay time 35 60 350 500 20 40 70 350 500 GSCLK – GSOUT 20 40 70 SCLK – SOUT 15 30 50 XOE↓ – SOUT (see Note 3) 10 20 35 XOE↑ – SOUT (see Note 3) 10 15 25 GSCLK – XDOWN2 10 20 25 BLANK↑ – OUT0 NOTE 3: Until SOUT will be turned on (drive) or turned off (Hi–Z). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns 200 GSCLK↓ – OUT0 td 8 10 OUTn+1 – OUTn BLANK – BOUT UNIT 250 SOUT Fall time MAX SOUT OUTn (see Figure 1) tf TYP 5000 ns TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC 51 Ω VCC IREF OUTn GND 590 Ω 15 pF Figure 1. Rise Time and Fall Time Test Circuit for OUTn VIH or VOH 100% VIH 90% 50% 10% VIL tr VIL or VOL 0% tf td 100% VIH 50% 100% VIH or VOH 50% 0% VIL tw(h) 0% VIL or VOL tw(l) Figure 2. Timing Requirements POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION constant current output selection by user (80 mA x16 bits or 120 mA x 8 bits) When the MODE terminal is set to high, output is selected as 80 mA x 16 bits. When the MODE terminal is set to low, output is selected as 120 mA x 8 bits. By this setting, the shift register latch for gray scale data is changed to the configuration corresponding to the bit selected. Note that two constant output terminals should be tied to LED such as OUT0-to-OUT1 and OUT2-to-OUT3 because they operate in pairs when the 8-bit output mode is selected. Also, in this case, the current value on constant current output is the same as in 16-bit output mode. Therefore, when output current of 120 mA is desired, the resister connected to the IREF terminal should be set to the same value as the output current of 60 mA. ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Table 1. Operation Mode Selection MODE OUTPUT H 80 mA × 16 bits L 120 mA × 8 bits On the constant current output terminals (OUT0–15), approximately 37 times the current that flows through external resistor, RIREF (connected between IREF and GND), can flow. The external resistor value is calculated using the following equation. R(IREF) (Ω) ≅ 37 × 1.24 (V) / IOL(C)(A) where BCENA is low. Note that more current flows if IREF is connected directly to GND. constant output current operation The constant current output turns on (sink constant current), if all the gray scale data latched into the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 8-bit gray scale counter. Then, output counted corresponding to the gray scale data is turned off (stop to sink constant current). If the shift register for gray scale is updated during XLATCH high, data on the gray scale data latch is also updated affecting the number of the gray scale of constant current output. Accordingly, during on-state of constant current output, XLATCH should be kept at a low level and the gray scale data latch should be held. If there are constant current output terminals unconnected (includes LED disconnection), the LED should be turned on after writing zero to the gray scale data latch corresponding to the output unconnected. Unless this action is taken, supply current on the constant current driver will increase resulting in influencing the current value for the constant current output when turned on. shift register latch The device provides three kinds of shift register latchs including the gray scale data, brightness control, and OVM. To write data into the shift register, SCLK and SIN are utilized. The selection of the shift register will be done by RSEL0 and RSEL1 as shown in Table 2. Note that RSEL0 and RSEL1 should be changed when both SCLK and XLATCH are low. ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Table 2. Shift Register Latch Selection 12 RSEL0 RSEL1 L L Shift register latch for gray scale data SHIFT REGISTER LATCH SELECTED L H Shift register latch for brightness control H L Shift register latch for OVM H H N/A (SOUT is tied to low level) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION shift register latch for gray scale data The shift register latch for gray scale data is set as a 64 x 1 bit configuration in the 8-bit mode, and as a 128 x 1 bit configuration in the 16-bit mode. The gray scale data, configured as 8 bits, represents the time when constant current output is being turned on, and the data range is 0 to 255 (00h to FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). On the other hand, when the gray scale data is 255, the time is longest, and it turns on during time of 255 clocks from GSCLK. The configuration of shift register and latch for gray scale data is shown in Figure 3. Latch for Gray Scale Data XLATCH OUT15 Data OUT14 Data (8 bits) (8 bits) .......... OUT1 Data OUT0 Data (8 bits) (8 bits) Shift Register for Gray Scale Data SOUT MSB 128 121 120 113 .......... 16 9 LSB 0 8 SCLK SIN 16 Bit Mode (MODE=H, RSEL0 and RSEL1=L) Latch for Gray Scale Data XLATCH OUT15,14 Data OUT13,12 Data (8 bits) (8 bits) .......... OUT3,2 Data OUT1,0 Data (8 bits) (8 bits) Shift Register for Gray Scale Data SOUT MSB 64 57 56 49 .......... 16 9 8 LSB 0 SCLK SIN 8 Bit Mode (MODE=L, RSEL0 and RSEL1=L) Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION shift register latch for brightness control and OVM The shift register latch for both the brightness control and OVM (output voltage monitor) is configured with a 1 x 1 byte. In the shift register latch for brightness control, the division ratio of GSCLK can be set and the output current value on constant current output can be adjusted. In the shift register latch for OVM, the comparison voltage at the OVM comparator on constant current output terminals (OUT0 to OUT15) can be set and the output signal for both XDOWN1 and XDOWN2 can be forced to a low level. When powered up, the latch data is indeterminate and shift register is not initialized. When these functions are used, data should be written to the shift register latch prior to turning the constant current output on (BLANK=L). Also, it is inhibited from rewriting the latch value for brightness control when the constant current output is turned on. When these functions are not used, latch value can be set to the default value setting of BCENA or MCENA or to low level (tied to GND). The configuration of the shift register and latch for brightness control and monitor control is shown in Figure 4. Latch for Brightness Control GSCLK Division Ratio Data Set XLATCH 0 0 MSB Current Data Adjusted On Constant Current Output 0 1 LSB MSB 1 1 1 1 (see Note) LSB Shift Register for Brightness Control SCLK SOUT 8th bit 7th bit 6th bit 5th bit 4th bit 3rd bit 2nd bit 1st bit SIN Latch for OVM Monitor Control Data N/A XLATCH 0 0 0 MSB 1 (see Note) LSB Shift Register for OVM SCLK SOUT 8th bit 7th bit 6th bit 5th bit 4th bit 3rd bit 2nd bit 1st bit SIN NOTE: Indicates default value at BCENA low if brightness control latch, at MCENA low if OVM latch. Figure 4. Relationship Between Shift Register and Latch for Brightness Control and OVM write data to shift register latch The shift register latch written is selected using the RSEL0 and RSEL1 terminal. The data is applied to the SIN data input terminal and clocked into the shift register synchronizing to the rising edge of SCLK after XENABLE is pulled low. The shift register for gray scale data is 64 bit length in the 8 bit mode resulting in 64 times of SCLK, and 128 bit length in the16 bit mode resulting in 128 times of SCLK. Brigtness control and monitor control results in eight times the SCLK input. At number of SCLK input for each case, data can be written into the shift register. In this condition, when XLATCH is pulled high, data in the shift register is clocked into latch (data through), and when XLATCH is pulled low, data is held (latch). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION brightness control function By writing data into the brightness control latch, current on all constant current outputs can be adjusted to control the variation of brightness between ICs and the division ratio for the gray scale clock can be set to control the variation of brightness for the total panel system. output current adjustment on all constant current outputs – brightness adjustment between ICs By using the lower 5 bits of the brightness control latch, output current can be adjusted to 32 steps as 1 step of 1.6% current ratio between 100% and 51.6% when the output current is set to 100% of an external resistor. By using this function, the brightness control between modules (ICs) can be adjusted, sending the desired data externally even if ICs are mounted on a print-circuit board. When BCENA is pulled low, the output current is set to 100%. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Table 3. Relative Current Ratio For Total Constant Current Output CODE CURRENT RATIO% 20 (mA) 80 (mA) MSB 00000 LSB 51.6 10.3 41.3 VIREF (TYP) 0.63 . . . . . . . . . . . . . . . . . . . . 11110 11111† 98.4 19.3 78.7 1.22 100 20.0 80.0 1.24 † BCENA is low. frequency division ratio setting for gray scale clock – panel brightness adjustment By using the upper 3 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/8. If the gray scale clock is set to 8 times the speed (256 × 8 = 2048) of frequency during horizontal scanning time, the brightness can be adjusted to 8 steps by selecting the frequency division ratio. Therefore, the total panel brightness can be adjusted at once, and applied to the brightness of day or night. When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted as shown in Table 4. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Table 4. Relative Brightness Ratio For Total Constant Current Output CODE FREQUENCY DIVISION RATIO RELATIVE BRIGHTNESS RATIO (%) MSB 000 LSB† 1/1 12.5 . . . . . . . . . . . . 110 1/7 87.5 111 1/8 100 † BCENA is low. OVM (output voltage monitor) function By writing data into the OVM latch, the comparison voltage for voltage comparator of OUT0 to OUT15 can be set and the output signal for XDOWN1 and XDOWN2 can be checked. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION OVM (output voltage monitor) function (continued) OVM comparator The OVM comparator compares the voltage on the constant current output terminal during turnon with comparison voltage set by the OVM latch. When the voltage on the constant current output terminal is lower, XDOWN2 goes low. As shown in Figure 5, the comparator is provided in every output portion, and the comparison result corresponding to the output to be turned on appears in the XDOWN2 terminal. Since the XDOWN2 terminal is an open-collector output, outputs of multiple ICs are brought together. The output terminal for comparison result is XDOWN2 only. The voltage on all the constant current output can be checked to monitor XDOWN2, turning output on in turn. The voltage on the constant current output, when turned on, can also be measured, resulting in a change to the comparison voltage set by the OVM latch. Using this function, the sensing (LOD function) LED disconnection (output voltage is below 0.3 V) and short circuit (output voltage is extremely high) can be detected and specifies which LED has encountered this failure. Also, by monitoring the output voltage and controlling the voltage across anode of the LED to minimize the voltage on the constant current output (approximately 0.7 V at IO = 80 mA), the rising temperature of the chip can be minimized. Furthermore, by setting BLANK to low during LED on, the previous comparison result can be held. Thus, synchronizing timing to check XDOWN2 from the system to the LED lighting timing is not required. Note that the gray scale data being turned on should be a minimum of 5 µs since the XDOWN2 output is required approximately 5 µs after the constant current output is turned on. The comparison result is also required approximately 5 µs after latch data is changed. OUT0 – + Internal OUT0 Turn ON Signal OUT1 – + XDOWN2 Internal OUT1 Turn ON Signal D Q OUT14 LATCH – + Internal OUT014 Turn ON Signal OUT15 Internal OUT015 Turn ON Signal – + BLANK Comparison Voltage When BLANK is high, hold the data When BLANK is low, data is out. Figure 5. OVM Functional Diagram 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION OVM (output voltage monitor) function (continued) output signal check for XDOWN1, XDOWN2 XDOWN1 or XDOWN2 can be forced to a low level by setting the appropriate latch value for OVM. This allows investigation of the correct connection of XDOWN1 or XDOWN2 to the external system. Since both XDOWN1 and XDOWN2 terminal are open-collector outputs, outputs of multiple ICs are brought together. OVM comparator setting Setting the OVM latch is shown in Table 5. Note that the comparison voltage is set to the default value of 0.3 V when MCENA tied to a low level. ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Table 5. OVM Setting COMPARISON VOLTAGE XDOWN1 XDOWN2 0000 0001† NO COMPARISON DEPEND ON TSD/WDT HI–Z 0.3 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0010 0.4 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR MONITOR CONTROL DATA MSB LSB 0011 0.5 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0100 0.6 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0101 0.7 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0110 0.8 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0111 0.9 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1000 1.0 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1001 1.1 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1010 1.2 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1011 1/3 × VCC(ANA) DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1100 1/2 × VCC(ANA) DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1101 2/3 × VCC(ANA) DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1110 0.3 V L DEPEND ON OVM COMPARATOR 1111 † MCENA is low. 0.3 V DEPEND ON TSD/WDT L SOUT output timing selection The timing for the SOUT output can be switched by selecting the SOMODE level. When SOMODE is low, SOUT is clocked out synchronizing to the rising edge of SCLK. When SOMODE is high, SOUT is clocked out synchronizing to the falling edge of SCLK. When the shift operation with SOMODE high, data can be protected from shift error even if the SCLK signal is buffered in serial externally. In this case, when ICs are connected in cascade, the maximum data transfer speed will be slower than the case of SOMODE low. protection This device incorporates WDT and TSD functions. If the WDT or TSD is turned on, then the constant current output is stopped and XDOWN1 goes low. Therefore, by monitoring XDOWN1 terminal, these failures can be detected immediately. Since the XDOWN1 output is configured as an open collector, outputs of multiple ICs are brought together. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION protection (continued) WDT (watchdog timer) The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the signal applied to WDTRG has not been changed. Therefore, by a connecting scan signal (signal to control line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned off preventing the LED from burning and damage by continuous LED turnon at the dynamic scanning operation. The detection time can be set using an external capacitor, Cext. The typical value is approximately 10 ms without a capacitor, 160 ms with a1000 pF capacitor and 1500 ms with a 0.01 µF capacitor. During static operation, the WDT function is disabled connecting WDCAP to GND (high or low level should be applied to WDTRG). Note that normal operation will be resumed changing the WDTRG level when WDT functions. WDT operational time T (ms) ≅ 10 + 0.15 x Cext (pF) TLC5905 1500 Scan Signal WDTRG WDCAP Cext 160 10 0 0.001 0.01 Cext – External Capacitor – µF Figure 6. WDT Operational Time and Usage Example TSD (thermal shutdown) When the junction temperature exceeds the limit, TSD functions and turns the constant current output off, and XDOWN1 goes low. When TSD is used, TSENA is pulled high. When TSD is not used, TSENA is pulled low. To recover from constant current output off-state to normal operation, the power supply should be turned off or TSENA should be pulled low once. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION noise reduction concurrent switching noise reduction The concurrent switching noise has potential to occur when multiple outputs turn on or off at the same time. To prevent this noise, the device has delay output terminals such as XGSOUT and BOUT for GSCLK (gray scale clock) and BLANK (blanking signal) respectively. By connecting these outputs to GSCLK and BLANK terminals of next stage IC, it allows differences in the switching time between ICs to be made. When GSCLK is output to GSOUT through the device, duty will be changed between input and output, and the number of stages to be connected will be limited depending on frequency. output slope When output current is 80 mA, the time to change constant current output to turnon and turnoff is approximately 150 ns and 250 ns respectively. It is effective in reducing concurrent switching noise that occurrs when multiple outputs turn or off at the same time. delay between constant current output The constant current output has a delay time of approximately 30 ns between outputs. It means approximately 450 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for reduction of concurrent switching noise as well as the output slope. This delay time has the same value in 8 bits or 16 bits operation mode. power supply The followings should be taken into consideration. D D VCC(LOG), VCC(ANA) and VCC(LED) should be supplied by a single power supply to minimize voltage differences between these terminals. The bypass capacitor should be located between power the supply and GND to eliminate the variation of power supply voltage. GND Although GNDLOG, GNDANA and GNDLED are internally tied together, these terminals should be externally connected to reduce noise influence. thermal pad The thermal pad should be connected to GND to eliminate the noise influence since it is connected to the bottom side of IC chip. Also, desired thermal effect will be obtained by connecting this pad to the PCB pattern with better thermal conductivity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION noise reduction (continued) 4.9 3.2 2.5 1.48 0 0 –20 0 25 85 TA – Free–Air Temperature – °C NOTES: A. This is based on simulation. When a TI recommended PCB is used, derate linearly at the rate of 39.4 mW/°C for operation above 25°C free-air temperature. VCC(LOG)=VCC(ANA)=VCC(LED)= 5 V, IO(LC) = 80 mA, IC(C) is typical value. B. The thermal impedance will be varied depending on mounting conditions. Since PAP package established low thermal impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal impedance. C. The material for PCB should be selected considering the thermal characteristics since the temperature will rise around the thermal pad. Figure 7. Power Rating – Free-Air Temperature 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 PRINCIPLES OF OPERATION noise reduction (continued) 90 80 70 60 50 40 30 20 10 0 0.1 1.0 10.0 RIREF – kΩ Conditions : VO = 1 V, V(IREF) = 1.24 V I OLC (mA) W ^ V (V) (IREF) R (k ) (IREF) W 37 ^I 47 (mA) O(LC) NOTE: The output current is in 16 bit mode. When in 8 bit mode (MODE=L), the output current is the sum of both outputs. This sum current should be set from 10 mA to 120 mA. The resistor, R(IREF), should be located as close to the IREF terminal as possible to avoid the noise influence. R (IREF) (k ) Figure 8. Current on Constant Current Output vs External Resistor POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 RSEL1 XOE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 XENABLE tsu(XENABLE–SCLK) 1/f(DCLK) th(XENABLE–SCLK) SCLK tsu(SIN–SCLK) SD00_A SIN SD01_A tw(l)(SCLK) SD02_A th(SIN–SCLK) SD7E_A tw(h)(SCLK) SD7F_A SD00_B th(XLATCH–SCLK) SD7D_B SD7E_B SD7F_B SD00_C SD01_C tsu(XLATCH–SCLK) XLATCH tw(h)(XLATCH) SOUT HI–Z SD00_A td(XOE↓–SOUT) SD01_A SD7E_A SD7F_A td(SCLK–SOUT) NOTE : MODE = H Figure 9. Timing Diagram (Shift Register for Gray Scale Data) SD00_B td(XOE↑–SOUT) TLC5905 LED DRIVER SLLS401 – november 1999 22 RSEL0 MCENA RSEL0 RSEL1 tsu(RSEL–XLATCH) th(RSEL–XLATCH) XOE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 XENABLE tsu(RSEL–SCLK) th(RSEL–SCLK) SCLK SD00_A SIN SD01_A SD07_A SD00_B SD01_B SD07_B SD00_C SD01_C SD02_C SD03_C SD04_C th(XLATCH–SCLK) XLATCH tw(h)(XLATCH) MCL_0 Default Value 1 Default Value 1 (Monitor Control Latch–Internal Signal) MCL_1–3 Default Value 0 Default Value 0 HI–Z SD00_A td(XOE↑–SOUT) SD01_A SD06_A SD07_A SD00_B Figure 10. Timing Diagram (Shift Register for Monitor Control) SD01_B SD03_B 23 TLC5905 LED DRIVER SOUT td(SCLK–SOUT) SLLS401 – november 1999 td(XOE↓–SOUT) RSEL0 tsu(RSEL–XLATCH) th(RSEL–XLATCH) RSEL1 XOE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 XENABLE tsu(RSEL–SCLK) th(RSEL–SCLK) SCLK SD00_A SIN SD01_A SD07_A SD00_B SD01_B SD07_B SD00_C SD01_C SD02_C SD03_C th(XLATCH–SCLK) XLATCH tw(h)(XLATCH) BCL_0–4 Default Value 1 Default Value 1 (Monitor Control Latch–Internal Signal) BCL_5–7 Default Value 0 Default Value 0 td(XOE↓–SOUT) SOUT HI–Z td(SCLK–SOUT) SD00_A td(XOE↑–SOUT) SD01_A SD06_A SD07_A SD00_B Figure 11. Timing Diagram (Shift Register for Brightness Control) SD01_B SD03_B SD04_C TLC5905 LED DRIVER SLLS401 – november 1999 24 BCENA XLATCH tsu(XLATCH–GSCLK) BLANK tsu(BLANK–GSCLK) 1/f(GSCLK) td(BLANK–OUT0) GSCLK tw(l)(GSCLK) tw(h)(GSCLK) 1/f(WDT) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 WDTRG tw(l)(WDTRG) tw(h)(WDTRG) td(BLANK–OUT0) td(GSCLK–OUT0) ON (see Note A) OFF OUT0 td(OUTn+1–OUTn) ON (see Note A) OFF ...... ON (see Note A) OFF OFF (see Note A) OFF ...... OFF (see Note A) (see Note A) OFF ...... OFF (see Note A) (see Note A) HI–Z XDOWN1 XDOWN2 (see Note A) OFF tw(dt) td(OUTn+1–OUTn) OUT1 ...... OUT15 td(GSCLK–OUT0) td(GSCLK–XDOWN2) (see NoteB) (see NoteB) td(BLANK–BOUT) GSOUT NOTES: A. ON or OFF, or ON time is varied dpend on the gray scale data and BLANK. B. LED disconnection 25 Figure 12. Timing Diagram (Constant Current Output) TLC5905 LED DRIVER td(GSCLK–GSOUT) SLLS401 – november 1999 BOUT TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 MECHANICAL DATA PAP (S-PQFP-G64) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 Thermal Pad (See Note D) 64 17 0,13 NOM 1 16 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Gage Plane 0,25 0,15 0,05 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4147702/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026 PowerPAD is a trademark of Texas Instruments Incorporated. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLC5905PAP ACTIVE HTQFP PAP 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -20 to 85 TLC5905 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of