TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
16-Channel, 16-Bit, PWM LED Driver with
6-Bit Global Brightness Control
Check for Samples: TLC59482
FEATURES
APPLICATIONS
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
•
16 Constant-Current Sink Output Channels
Sink Current Capability with Max BC Data:
– 1 mA to 35 mA (VCC ≤ 3.6 V)
– 1 mA to 45 mA (VCC > 3.6 V)
Global Brightness Control (BC):
– 6-Bit (64 Steps) with 0% to 100% Range
(default is 50%)
LED Power-Supply Voltage: Up to 10 V
VCC: 3.0 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel: ±1% (typ), ±2.5% (max)
– Device-to-Device: ±2% (typ), ±4% (max)
Data Transfer Rate: 30 MHz
Grayscale Control Clock: 33 MHz
Auto Display Repeat
Auto Data Refresh
Display Timing Reset
Four-Channel Grouped Delay Switching to
Prevent Inrush Current
Operating Temperature: –40°C to +85°C
LED Video Displays
LED Signboards
DESCRIPTION
The TLC59482 is a 16-channel, constant-current sink
driver. Each channel has an individually-adjustable,
pulse width modulation (PWM) grayscale (GS)
brightness control with 65,536 steps. All channels
have a 64-step global brightness control (BC). BC
adjusts brightness deviation with other LED drivers.
GS and BC data are accessible via a serial interface
port.
VLED
OUT0
DATA
¼
¼
¼
¼
¼
¼
¼
SCLK
SOUT
LAT
GSCLK
Device 1
OUT15
SOUT
VCC
SCLK
LAT
VCC
Device n
VCC
GSCLK
GSCLK
IREF
Controller
¼
SIN
VCC
SCLK
LAT
OUT0
OUT15
SIN
IREF
GND
RIREF
GND
RIREF
3
Data Read
Typical Application Circuit (Multiple Daisy-Chained TLC59482s)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE
DESIGNATOR
PRODUCT
DBQ
TLC59482
RGE (2)
(1)
(2)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TLC59482DBQR
Tape and Reel, 2500
TLC59482DBQ
Tube, 50
TLC59482RGER
Tape and Reel, 3000
TLC59482RGET
Tape and Reel, 250
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Product preview device.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
Voltage (2)
Current
(2)
–0.3
+6
V
SIN, SCLK, LAT, GSCLK, IREF
–0.3
VCC + 0.3
V
SOUT
–0.3
VCC + 0.3
V
OUT0 to OUT15
–0.3
+11
V
+55
mA
+150
°C
Operating junction, TJ (max)
Storage, Tstg
Electrostatic discharge (ESD)
ratings
UNIT
VCC
IOUT (dc), OUT0 to OUT15
Temperature
(1)
MAX
+150
°C
Human body model (HBM)
–55
3000
V
Charged device model (CDM)
2000
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to device ground terminal.
THERMAL INFORMATION
TLC59482
THERMAL METRIC (1)
DBQ
(SSOP, QSOP)
RGE
(QFN)
24 PINS
24 PINS
θJA
Junction-to-ambient thermal resistance
86.7
35.5
θJCtop
Junction-to-case (top) thermal resistance
50.4
44
θJB
Junction-to-board thermal resistance
10.0
14.7
ψJT
Junction-to-top characterization parameter
13.0
0.4
ψJB
Junction-to-board characterization parameter
39.7
14.8
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
2.9
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC
Supply voltage
VO
Voltage applied to output
OUT0 to OUT15
VIH
High-level input voltage
SIN, SCLK, LAT, GSCLK
VIL
Low-level input voltage
SIN, SCLK, LAT, GSCLK
IOH
High-level output current
SOUT
–2
mA
IOL
Low-level output current
SOUT
2
mA
OUT0 to OUT15,
3 V ≤ VCC ≤ 3.6 V
35
mA
OUT0 to OUT15,
3.6 V < VCC ≤ 5.5 V
45
mA
IOLC
Constant output sink current
3.0
5.5
V
10
V
0.7 × VCC
VCC
V
GND
0.3 × VCC
V
TA
Operating free-air temperature range
–40
+85
°C
TJ
Operating junction temperature range
–40
+125
°C
3.0
AC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC
Supply voltage
fCLK
(SCLK)
Data shift clock frequency
fCLK
(GSCLK)
Grayscale control clock frequency
5.5
V
SCLK, 3.0 V ≤ VCC ≤ 3.6 V
25
MHz
SCLK, 3.6 V < VCC ≤ 5.5 V
30
MHz
33
MHz
GSCLK
tWH0
SCLK
10
ns
tWL0
SCLK
10
ns
GSCLK
10
ns
tWL1
GSCLK
10
ns
tWH2
LAT
10
ns
tSU0
SIN to SCLK↑
4
ns
tWH1
tSU1
Pulse duration
LAT↑ to SCLK↑
2
ns
tSU2
LAT↓ to SCLK↑ (1)
5
ns
tH0
SCLK↑ to SIN
4
ns
SCLK↑ to LAT↑
7
ns
SCLK↑ to LAT↓
14
ns
LAT↓ to GSCLK↑
30
ns
tH1
tH2
Setup time
Hold time
tH3
(1)
Refer to the tD1 parameter in the Switching Characteristics table for the FC data read time.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
3
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage (SOUT)
IOH = –2 mA
VOL
Low-level output voltage (SOUT)
IOL = 2 mA
VIREF
Reference voltage output
RIREF = 1.5 kΩ
IIN
Input current
(SIN, SCLK, GSCLK)
VIN = VCC or GND
MIN
TYP
MAX
UNIT
VCC
V
0.4
V
1.225
V
1
μA
VCC – 0.4
1.175
1.200
–1
ICC0
SIN, SCLK, LAT, GSCLK = GND, GSn = 0000h,
BC = 3Fh, VOUTn = 0.8 V, RIREF = open
1.5
3
mA
ICC1
SIN, SCLK, LAT, GSCLK = GND, GSn = 0000h,
BC = 3Fh, VOUTn = 0.8 V, RIREF = 3 kΩ
(IOUTn = 15.9-mA target)
3
5
mA
ICC2
SIN, SCLK, LAT = GND, GSCLK = 33 MHz,
GSn = FFFFh, BC = 3Fh, VOUTn = 0.8 V, RIREF = 3 kΩ
(IOUT = 15.9-mA target)
8
10
mA
ICC3
SIN, SCLK, LAT = GND, GSCLK = 33 MHz,
GSn = FFFFh, BC = 3Fh, VOUTn = 0.8 V, RIREF = 1.5 kΩ
(IOUT = 31.8-mA target)
9
13.5
mA
31.8
33.8
mA
0.1
μA
Supply current (VCC)
IOLC
Constant output sink current
(OUT0 to OUT15)
All OUTn = on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.5 kΩ, TA = +25°C (IOLCn = 31.8-mA target)
Output leakage current
(OUT0 to OUT15)
All OUTn = off, GSn = 0000h,
VOUTn = VOUTfix = 10 V,
RIREF = 1.5 kΩ
(IOLCn = 31.8-mA target)
IOLKG0
IOLKG1
IOLKG2
29.8
TJ = +25°C
TJ = +85°C
(1)
TJ = +125°C (1)
0.2
μA
0.3
0.8
μA
ΔIOLC0
Constant-current error,
channel-to-channel
(OUT0 to OUT15) (2)
All OUTn = on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.5 kΩ, TA = +25°C
(IOUTn = 31.8-mA target)
±1%
±2.5%
ΔIOLC1
Constant-current error,
device-to-device
(OUT0 to OUT15) (3)
All OUTn = on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.5 kΩ, TA = +25°C
(IOUTn = 31.8-mA target)
±2%
±4%
ΔIOLC2
Line regulation
(OUT0 to OUT15) (4)
VCC = 3.0 V to 5.5 V, all OUTn = on, BC = 3Fh,
VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ
(IOUTn = 31.8-mA target)
±1
±3
%/V
ΔIOLC3
Load regulation
(OUT0 to OUT15) (5)
All OUTn = on, BC = 3Fh, VOUTn = 0.8 V to 3.0 V,
VOUTfix = 0.8 V, RIREF = 1.5 kΩ
(IOUTn = 31.8-mA target)
±1
±3
%/V
RPDWN
Pull-down resistor
LAT
500
750
kΩ
(1)
(2)
250
Not tested; specified by design.
The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
IOLCn
D (%) =
-1
IOLC0 + IOLC1 + ... + IOLC14 + IOLC15
´ 100
16
(3)
where n = 0 to 15.
The deviation of the OUTn output current value from the ideal constant-current value. Deviation is calculated by the formula:
(IOLC0 + IOLC1 + ... IOLC14 + IOLC15)
D (%) =
16
- Ideal Output Current
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
IOLCn(IDEAL) (mA) = 39.8 ´
(4)
where n = 0 to 15.
Line regulation is calculated by the formula:
D (%/V) =
(5)
1.20
RIREF (W)
(IOLCn at VCC = 5.5 V) - (IOLCn at VCC = 3.0 V)
IOLCn at VCC = 3.0 V
´
100
5.5 V - 3 V
where n = 0 to 15.
Load regulation is calculated by the equation:
D (%/V) =
(IOLCn at VOUTn = 3 V) - (IOLCn at VOUTn = 0.8 V)
IOLCn at VOUTn = 0.8 V
´
100
3 V - 0.8 V
where n = 0 to 15.
4
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
SWITCHING CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 110 Ω, RIREF = 1.5 kΩ, and VLED = 5.0 V, unless otherwise
noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
tR0
Rise time
tR1
TEST CONDITIONS
MIN
SOUT
TYP
MAX
1.5
5
UNIT
ns
OUTn, BC = 7Fh, TA = +25°C
30
SOUT
1.5
OUTn, BC = 7Fh, TA = +25°C
30
tD0
SCLK↑ to SOUT↑↓
23
35
ns
tD1
LAT↓ to SOUT↑↓
27
42
ns
tD2
GSCLK↑ to OUT0, OUT7, OUT8, OUT15 on/off with
BC = 7Fh, TA = +25°C
50
ns
GSCLK↑ to OUT1, OUT6, OUT9, OUT14 on/off with
BC = 7Fh, TA = +25°C
55
ns
tD4
GSCLK↑ to OUT2, OUT5, OUT10, OUT13 on/off with
BC = 7Fh, TA = +25°C
60
ns
tD5
GSCLK↑ to OUT3, OUT4, OUT11, OUT12 on/off with
BC = 7Fh, TA = +25°C
65
ns
tF0
Fall time
tF1
Propagation delay
tD3
tON_ERR
(1)
Output on-time error (1)
tOUTON – tGSCLK, GSn = 0001h, GSCLK = 20 MHz,
BC = 3Fh, VCC = 3.3 V, TA = +25°C
–35
ns
5
ns
ns
10
ns
Output on-time error (tON_ERR) is calculated by the formula: tON_ERR = tOUT_ON – tGSCLK. tOUT_ON is the actual on-time of the constantcurrent driver. tGSCLK is the GSCLK period.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
5
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
LAT
GND
GND
Figure 1. SIN, SCLK, and GSCLK
Figure 2. LAT
VCC
SOUT
GND
Figure 3. SOUT
OUTn
(1)
GND
(1) n = 0 to 15.
Figure 4. OUT0 Through OUT15
6
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
TEST CIRCUITS
RL
VCC
VCC
OUTn
IREF
RIREF
(1)
VLED
(2)
CL
GND
(1) n = 0 to 15.
(2) CL includes measurement probe and jig capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for OUTn
VCC
SOUT
VCC
CL
GND
(1)
(1) CL includes measurement probe and jig capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
¼
VCC
IREF
(1)
¼
RIREF
OUTn
GND OUT15
VOUTfix
VOUTn
(1) n = 0 to 15.
Figure 7. Constant-Current Test Circuit for OUTn
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
7
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
TIMING DIAGRAMS
tWH0, tWH1, tWH2, tWL0, tWL1:
VCC
Input
(1)
50%
GND
tWH
tWL
tSU0, tSU1, tSU2, tH0, tH1, tH2, tH3:
VCC
Clock Input
(1)
50%
GND
tSU
tH
VCC
Data and Control
Clock
(1)
50%
GND
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5:
VCC
Input
(1)
50%
GND
tD
VOH or VOUTnH
90%
Output
50%
10%
VOL or VOUTnL
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Output Timing
8
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
SIN
GS1
8A
GS1
7A
GS1
6A
GS1
3A
GS1
4A
GS1
5A
GS1
1A
GS1
2A
GS1
0A
GS0
15A
GS0
14A
1
2
GS0
13A
GS0
0A
GS0
1A
tH0
tSU0
tWH0
SCLK
9
8
10
11
12
13
14
tWL0
15
tH1
16
tWH2
---
tSU2
14
15
16
tH2
tSU1
LAT
tH3
tWH1
GSCLK
tD1
GS Second Data
Latch (Internal)
tWL1
New Data (GS15-15A to GS0-0A)
Old Data
GS data are updated at the same time as the second
GS data when auto data refresh is disabled (XFRESH = 1).
GS Third Data
Latch (Internal)
Old Data
FC data are loaded into the common shift register
when the READFC command is input.
tD0
SOUT
GS2
7A
GS2
6A
New Data (GS15-15A to GS0-0A)
GS2
5A
GS2
4A
GS2
3A
GS2
2A
GS2
1A
GS2
0A
GS1
15A
GS1
14A
GS1
13A
GS1
1A
GS1
0A
GS0
15A
tR0, tF0
GS data are one case.
tF1
OUT0, OUT7,
OUT8, OUT15
OUT1, OUT6,
OUT9, OUT14
OUT2, OUT5,
OUT10, OUT13
OUT3, OUT4,
OUT11, OUT12
tR1
OFF
ON
tD2
tOUTON
OFF
ON
tD3
tOUTON
OFF
ON
tD4
tOUTON
OFF
ON
tD5
tOUTON
tON_ERR = tOUTON - tGSCLK
(1) NV = Not valid; these data are not used for any function.
Figure 10. Timing Diagram
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
9
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
PIN CONFIGURATIONS
DBQ PACKAGE
SSOP-24, QSOP-24
(Top View)
GND
1
24
VCC
SIN
2
23
IREF
SCLK
3
22
SOUT
LAT
4
21
GSCLK
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
SCLK
SIN
GND
VCC
IREF
SOUT
24
23
22
21
20
19
RGE PACKAGE
QFN-24
(Top View)
LAT
1
18
GSCLK
OUT0
2
17
OUT15
OUT1
3
16
OUT14
OUT2
4
15
OUT13
OUT3
5
14
OUT12
OUT4
6
13
OUT11
7
8
9
10
11
12
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
Thermal Pad
(Bottom Side)
NOTE: The thermal pad is not internally connected to GND. The thermal pad must be connected to GND via the printed board circuit (PCB)
pattern.
10
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
PIN DESCRIPTIONS
PIN
NO.
NAME
DBQ
RGE
I/O
GND
1
22
—
DESCRIPTION
Power ground
GSCLK
21
18
I
Grayscale (GS) pulse width modulation (PWM) reference clock control for OUTn.
Each GSCLK rising edge increments the GS counter for PWM control.
When the TMGRST command is input with the TMRSTEN bit (equal to '1') in the function
control data latch, all constant-current outputs (OUT0 to OUT15) are forced off and the GS
counter is reset to '0'. Furthermore, all constant-current outputs are forced off and the GS
counter is reset to '0' when the LATGS command is input with the XRFRESH bit (equal to '1')
in the function control data latch.
IREF
23
20
I/O
Reference current terminal.
A resistor connected between IREF to GND sets the maximum current for all constant-current
outputs.
The LAT falling edge latches the data from the 16-bit common shift register into the first GS
data latch for the OUTn that are selected by either the GS data address down counter, global
brightness control (BC) data latch, or function control (FC) data latch. The data latch is
selected by the number of input SCLK rising edges while LAT is high. This pin is internally
pulled down to GND with a 500-kΩ (typ) resistor.
LAT
4
1
I
OUT0
5
2
O
OUT1
6
3
O
OUT2
7
4
O
OUT3
8
5
O
OUT4
9
6
O
OUT5
10
7
O
OUT6
11
8
O
OUT7
12
9
O
OUT8
13
10
O
OUT9
14
11
O
OUT10
15
12
O
OUT11
16
13
O
OUT12
17
14
O
OUT13
18
15
O
OUT14
19
16
O
OUT15
20
17
O
Constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
SCLK
3
24
I
Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit common shift register with the SCLK
rising edge. Data in the shift register are shifted towards the MSB at each SCLK rising edge.
The MSB of the common shift register appears on SOUT.
SIN
2
23
I
Serial data input for the 16-bit common shift register
SOUT
22
19
O
Serial data output of the 16-bit common shift register.
SOUT is connected to the 16-bit common shift register MSB. Data are clocked out at the
SCLK rising edge. Data in the function data latch can be read from SOUT during the READFC
command.
VCC
24
21
—
Power-supply voltage
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
11
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VCC
LSB
MSB
16-Bit
Common
Shift Register
SIN
SCLKB
SCLK
0
SOUT
15
16
16
ADR[15:0]
1
LSB
Grayscale (GS)
XRST
Data Latch
Address Counter
LAT16B
1
16
GS First
Data Latch
for OUT0
GS First
Data Latch
for OUT1
31 32
15 16
16
16
0
LOAD
LAT256B
16
1
16
MSB
GS First
GS First
Data Latch
Data Latch
for OUT15
for OU14
239 240
223 224
255
16
16
LSB
LAT3RD
LAT
Command
Decoder
1
16
MSB
GS Second
Data Latch
for OUT0
LATFC
0
GS Second
Data Latch
for OUT1
31 32
15 16
16
XRST
SCLK
16
MSB
LSB
GS Third
Data Latch
for OUT0
SCLKB
GS Third
Data Latch
for OUT1
31 32
15 16
0
GS Second
GS Second
Data Latch
Data Latch
for OUT15
for OUT14
223 224
239 240
255
16
16
GS Third
GS Third
Data Latch
Data Latch
for OUT14
for OUT15
223 224
239 240
255
LAT
16
16
MSB
LSB
XRST
Power-On
Reset
XRFRESH
2 LATMODE
Function Control (FC) Data Latch
0
15
16
256
1
PRIODEND
GSCLK
XTMGRST
16-Bit
GS Counter
16-Bit PWM Timing Control
16
6
4-Grouped Switching Delay
BC
16
IREF
Reference
Current
Control
Constant Sink Current Driver with 6-Bit BC
GND
OUT0
12
OUT1
Submit Documentation Feedback
OUT14
OUT15
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
100
60
Output Current (mA)
Reference Resistor (kΩ)
VCC = 5 V, BC = 3Fh, TA = +25°C
10
50
IOLCMax = 45 mA
40
IOLCMax = 35 mA
30
IOLCMax = 20 mA
20
IOLCMax = 10 mA
10
IOLCMax = 1 mA
1
0
10
20
30
Output Current (mA)
40
0
50
0
0.5
Figure 11. REFERENCE RESISTOR
vs OUTPUT CURRENT
3
G001
VCC = 5 V, BC = 3Fh, VOUTn = 0.8 V, TA = +25°C
Constant−Current Error (%)
38
Output Current (mA)
2.5
3
VCC = 5 V, BC = 3Fh, IOLCMax = 35 mA
37
36
35
34
33
TA = −40°C
TA = +25°C
TA = +85°C
32
0
0.5
1
1.5
2
Output Voltage (V)
2.5
2
1
0
−1
−2
−3
3
0
10
20
30
Output Current (mA)
G002
Figure 13. OUTPUT CURRENT
vs OUTPUT VOLTAGE
40
50
G003
Figure 14. CONSTANT-CURRENT ERROR vs
OUTPUT CURRENT SET BY EXTERNAL RESISTOR
3
50
VCC = 5 V, BC = 3Fh, VOUTn = 0.8 V, IOLCMax = 35 mA
VCC = 5 V, VOUTn = 0.8 V, TA = +25°C
IOLCMax = 45 mA
2
40
Output Current (mA)
Constant−Current Error (%)
1.5
2
Output Voltage (V)
Figure 12. OUTPUT CURRENT
vs OUTPUT VOLTAGE
39
31
1
G000
1
0
−1
IOLCMax = 35 mA
30
IOLCMax = 20 mA
20
IOLCMax = 10 mA
10
−2
IOLCMax = 1 mA
−3
−40
−20
0
20
40
60
Ambient Temperature (°C)
80
100
0
0
G004
Figure 15. CONSTANT-CURRENT ERROR
vs AMBIENT TEMPERATURE
8
16
24
32
40
BC Data (Decimal)
48
56
Product Folder Links: TLC59482
G005
Figure 16. GLOBAL BRIGHTNESS
CONTROL LINEARITY
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
63
13
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
20
VCC = 5.0 V
VCC = 3.3 V
18
16
ICC (mA)
14
12
10
8
6
TA = +25°C, SIN = 17.5 MHz, SCLK = 25 MHz,
GSCLK = 33 MHz, All GS data = FFFFh,
BC = 3Fh, VOUTn = 0.8 V
4
2
0
0
10
20
30
Output Current (mA)
40
50
G006
Figure 17. SUPPLY CURRENT
vs OUTPUT CURRENT
14
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
DETAILED DESCRIPTION
MAXIMUM CONSTANT SINK CURRENT VALUE
The maximum output current value of each channel (IOLCMax) is programmed by a single resistor (RIREF) that is
placed between the IREF and GND pins. The current value can be calculated by Equation 1:
RIREF (kW) =
VIREF (V)
IOLCMax (mA)
´ 39.8
Where:
VIREF = the internal reference voltage on IREF (typically 1.20 V when the global BC data are at maximum)
IOLCMax = 1 mA to 35 mA (3 V ≤ VCC ≤ 3.6 V) or 1 mA to 45 mA (3.6 V < VCC ≤ 5.5 V) at OUTn and BC =
63
(1)
IOLCMax is the highest current for each output. Each output sinks IOLCMax current when it is turned on and the
global brightness control (BC) data are set to the maximum value of 3Fh (64). Each output sink current can be
reduced by lowering the BC value.
RIREF must be between 1.06 kΩ and 47.8 kΩ in order to hold IOLCMax between 45 mA (typ) and 1 mA (typ).
Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved by setting IOLCMax to
1 mA or higher and then using global BC to lower the output current.
Table 1 shows the characteristics of the constant-current sink versus the external resistor, RIREF.
Table 1. Maximum Constant-Current Output versus External Resistor Value
IOLCMax (mA)
IOLC FOLLOWING POWER-UP (mA, BC =
32)
RIREF (kΩ, typ)
45 (VCC > 3.6 V only)
22.5
1.06
40 (VCC > 3.6 V only)
20
1.19
35
17.5
1.37
30
15
1.59
25
12.5
1.91
20
10
2.39
15
7.5
3.18
10
5
4.78
5
2.5
9.55
1
0.5
47.8
GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION
The TLC59482 can simultaneously adjust the output current of all constant-current outputs. This function is
called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) is programmed with a 6-bit
word. The global BC adjusts all output currents in 64 steps from 0% to 100%, where 100% corresponds to the
maximum output current set by RIREF. Equation 2 calculates the actual output current as a function of RIREF and
global BC value. BC data can be set via the serial interface. When the device is powered on, the BC data in the
function control (FC) data latch is set to 32 as the initial value.
The output current value controlled by BC can be calculated by Equation 2.
IOUTn (mA) = IOLCMax (mA) ´ BCn
63
Where:
IOLCMax = the maximum constant-current value for each output determined by RIREF
BC = the global brightness control value in the brightness control data latch (0 to 63)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
(2)
15
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
Table 2 summarizes the BC data versus the set current value.
Table 2. BC Data versus Constant-Current Ratio and Set Current Value
BC DATA
BINARY
DECIMAL
HEX
RATIO OF OUTPUT
CURRENT TO
IOLCMax(%)
IOUT (mA)
(IOLCMax= 45 mA,
typ)
IOUT (mA)
(IOLCMax= 1 mA, typ)
00 0000
0
00
0
0
0
00 0001
1
01
1.6
0.71
0.02
00 0010
2
02
3.2
1.43
0.03
—
—
—
—
—
—
01 1111
31
1F
49.2
22.14
0.49
10 0000 (default)
32 (default)
20 (default)
50.8
22.86
0.51
10 0001
33
21
52.4
23.57
0.52
—
—
—
—
—
—
11 1101
61
3D
96.8
43.57
0.97
11 1110
62
3E
98.4
44.29
0.98
11 1111
63
3F
100.0
45.00
1.00
GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC59482 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The architecture of 16 bits per channel results in 65,536 brightness steps, from 0% up to 100%
brightness.
The PWM operation is controlled by the grayscale (GS) counter based on the GS data in the third GS data latch.
The GS counter increments on each rising edge of the grayscale reference clock (GSCLK). When the TMGRST
command is input with the TMRSTEN bit (equal to '1') of the function control data latch, or when the LATGS
command is input with the XRFRESH bit (equal to '1') of the function control data latch, all constant-current
outputs (OUT0 to OUT15) are forced off, the GS counter is reset to ‘0’, and the GS PWM timing controller is
initialized.
The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 3.
tOUT_ON (ns) = tGSCLK × GSn
where:
tGSCLK is on GS clock period
GSn is the programmed GS value for OUTn (0 to 65535)
16
Submit Documentation Feedback
(3)
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
Table 3 summarizes the GS data values versus the output on-time duty cycle in a 16-bit length PWM. When the
device powers up, all outputs are forced off and do not turn on until the 256-bit GS data are written to the third
data latch even if GSCLK is input.
Table 3. Output Duty Cycle and On-Time versus GS Data (16-Bit PWM Bit Length)
GS DATA
GS DATA
ON-TIME RATE vs
MAX GS (%)
DECIMAL
HEX
ON-TIME RATE vs
MAX GS (%)
0
0
32768
8000
50.001
1
0.002
32769
8001
50.002
2
0.003
32770
8002
50.004
50.005
DECIMAL
HEX
0
1
2
3
3
0.005
32771
8003
—
—
—
—
—
—
8191
1FFF
12.499
40959
9FFF
62.499
8192
2000
12.500
40960
A000
62.501
8193
2001
12.502
40961
A001
62.502
—
—
—
—
—
—
16383
3FFF
24.999
49151
BFFF
75.000
16384
4000
25.000
49152
C000
75.001
16385
4001
25.002
49153
C001
75.003
—
—
—
—
—
—
24575
5FFF
37.499
57343
DFFF
87.500
24576
6000
37.501
57344
E000
87.501
24577
6001
37.502
57345
E001
87.503
—
—
—
—
—
—
32765
7FFD
49.996
65533
FFFD
99.997
32766
7FFE
49.998
65534
FFFE
99.998
32767
7FFF
49.999
65535
FFFF
100.000
Enhanced Spectrum (ES) PWM Control
In this PWM control, the entire display period is divided into 128 display segments. The total display period is the
time from the first grayscale clock (GSCLK) to the 65,536th GS clock input for the 16-bit length PWM. Each
display segment has a maximum of 512 grayscale clocks (maximum). The OUTn on-time changes, depending on
the 16-bit grayscale data. Refer to Table 4 for the sequence of information and to Figure 18 for the timing
information.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
17
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
Table 4. ES PWM Drive Turn On-Time Length
GS DATA
18
DECIMAL
HEX
OUTn DRIVER OPERATION
0
0000h
Does not turn on
1
0001h
Turns on for one GSCLK period in the first display segment
2
0002h
Turns on for one GSCLK period in the first and 65th display segments
3
0003h
Turns on for one GSCLK period in the first, 65th, and 33th display segments
4
0004h
Turns on for one GSCLK period in the first, 65th, 33th, and 97th display segments
5
0005h
Turns on for one GSCLK period in the first, 65th, 33th, 97th, and 17th display segments
6
0006h
Turns on for one GSCLK period in the first, 65th, 33th, 97th, 17th, and 81th display segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
> 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
—
—
127
007Fh
Turns on for one GSCLK period in the first to 127th display segments, but does not turn on in the
128th display segment
128
0080h
Turns on for one GSCLK period in all display segments (first to 128th)
129
0081h
Turns on for two GSCLK periods in the first display period and for one GSCLK period in all other
display periods
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
> 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
—
—
255
00FFh
Turns on for two GSCLK periods in the first to 127th display segments and turns on one GSCLK
period in the 128th display segment
256
0100h
Turns on for two GSCLK periods in all display segments (first to 128th)
257
0101h
Turns on for three GSCLK periods in the first display segments and for two GSCLK periods in all
other display segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
> 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
—
—
65407
FF7Fh
Turns on for 511 GSCLK periods in the first to 127th display segments, but only turns on 510
GSCLK periods in the 128th display segment
65408
FF80h
Turns on for 511 GSCLK periods in all display segments (first to 128th)
65409
FF81h
Turns on for 512 GSCLK periods in the first display period and for 511 GSCLK periods in the
second to 128th display segments
—
—
65534
FFFEh
Turns on for 512 GSCLK periods in the first to 63th and 65th to 127th display segments; also turns
on 511 GSCLK periods in 64th and 128th display segments
65535
FFFFh
Turns on for 512 GSCLK periods in the first to 127th display segments but only turns on 511
GSCLK periods in the 128th display segment
—
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
16382
511
1
2
3
¼
513
¼
512
514
32766
16385
16383
16386 ¼
16384
16387
32769
49150
49153
32767
32770 ¼
32768
32771
49151
49154 ¼
49152
49155
65th
64th
Period Period
96th
Period
65023
65026
65536
65024
¼ 65534
65025
65535
GSCLK
(Voltage Level = High)
OUTn OFF
(GS Data = 0000h)
ON
1st Period
33rd
2nd ¼ 32nd
Period Period
Period
¼
¼
97th ¼ 127th
Period
Period
128th
Period
1st
Period
(Voltage Level = Low)
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 0001h)
ON
t = GSCLK
t = GSCLK
OUTn OFF
(GS Data = 0002h)
ON
t = GSCLK
t = GSCLK
t = GSCLK
OUTn OFF
(GS Data = 0003h)
ON
t = GSCLK
t = GSCLK
t = GSCLK
OUTn OFF
(GS Data = 0004h)
ON
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
OUTn OFF
(GS Data = 0041h)
ON
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
OUTn OFF
(GS Data = 0080h)
ON
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK ´ 2
t = GSCLK ´ 1
OUTn OFF
(GS Data = 0081h)
ON
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK ´ 2
t = GSCLK ´ 2
OUTn OFF
(GS Data = 0082h)
ON
t = GSCLK
t=
GSCLK ´ 511
t = GSCLK ´ 511 in 2nd to 128th Period
t = GSCLK ´ 512
t = GSCLK ´ 511 in 2nd to 128th Period
t = GSCLK
OUTn OFF
(GS Data = FF80h)
ON
OUTn OFF
(GS Data = FF81h)
ON
t = GSCLK ´ 512
t = GSCLK ´ 512 in 2nd to 63rd and 65th to 127th Periods,
t = GSCLK ´ 511 in 64th Period
t=
GSCLK ´ 511
t = GSCLK ´ 512
t = GSCLK ´ 512 in 2nd to 127th Period
t=
GSCLK ´ 511
OUTn OFF
(GS Data = FFFEh)
ON
OUTn OFF
(GS Data = FFFFh)
ON
Figure 18. ES PWM Operation
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
19
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 19. This
function is always enabled. OUTn turn on at the 513th GSCLK after the first LATGS command is input.
3V~5.5V
VCC
0V
SIN
SCLK
256 SCLK for 16-bit
* 16-word writing
2 SCLK for
“LATGS”
Command
LAT
16 LAT for
16 “WRTGS”
Command
GS Third Data
Latch (Internal)
First
“LATGS”
Command
Unknown
Written Data by 16 “WRTGS” Command
1
1
2
2
512
3
65534
1
65535
2
65536
3
65534
1
65535
2
65536
3
GSCLK
OUTn is turned on
th
at 513 GSCLK after first
“LATGS” command is input.
OFF
OUT
First Entire
Display Period
Second Entire
Display Period
Third Entire
Display Period
Display period is repeated
by auto display repeat
function.
OFF
OFF
ON
(GS Data = FFFFh)
Figure 19. Auto Display Repeat Function
Auto Data Refresh Function
This function allows users to input grayscale (GS) data at any time without synchronizing the input to the display
timing. When the LATGS command is input with the auto data refresh function enabled (XRFRESH bit = 0), the
256-bit data in the first GS data latch are copied only to the second GS data latch. The data in the second GS
data latch are copied to the third data latch when the 65,536th GSCLK occurs. The third latch data are used for
constant-current output (OUT0-OUT15) for the next display period.
When the LATGS command is input with the auto data refresh function disabled (XRFRESH bit = 1), the 256-bit
data in the first GS data latch are copied to the second and third GS data latches at the same time and the GS
data in the third data latch are used for OUT0-OUT15 on/off control from the next input GSCLK rising edge.
Furthermore, the GS counter is set to '0' and all constant-current outputs (OUTn) are forced off. Refer to
Figure 20 for a timing diagram of the auto data refresh function.
20
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SIN
SBVS218 – DECEMBER 2012
GS1
0B
GS0
15B
GS0
4B
GS0
3B
GS0
2B
GS0
1B
GS15 GS15 GS15 GS15 GS15 GS15
15C 14C 13C
12C 11C
10C
GS0
0B
Dotted line LAT
timing is accepted.
SCLK
13
14
12
Dotted line LAT timing
is accepted.
1
15
16
The LATGS command executes.
LAT
----
2 or 3 rising edge of SCLK is needed
to be input while LAT is high level.
65535
1
65534
65536
3
2
----
GSCLK
Shift Register
LSB Data
(Internal)
GS1
0B
GS0
15B
GS0
5B
GS0
4B
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS15 GS15 GS15 GS15 GS15 GS15
15C 14C 13C
12C 11C
10C
Shift Register
LSB+1 Data
(Internal)
GS1
1B
GS1
0B
GS0
6B
GS0
5B
GS0
4B
GS0
3B
GS0
2B
GS0
1B
GS0 GS15 GS15 GS15 GS15 GS15
0B
15C 14C
13C 12C
11C
Shift Register
MSB-1 Data
(Internal)
GS1
14B
GS1
13B
GS1
3B
GS1
2B
GS1
1B
GS1
0B
GS0
15B
GS0
14B
GS0
13B
GS0
12B
GS0
11B
GS0
10B
GS0
9B
GS0
8B
GS1
14B
GS1
4B
GS1
3B
GS1
2B
GS1
1B
GS1
0B
GS0
15B
GS0
14B
GS0
13B
GS0
12B
GS0
11B
GS0
10B
GS0
9B
GS1
15B
SOUT
OUT1
GS Data Latch
Address Counter
(Internal)
OUT0
OUT15
OUT0
OUT15 GS First
Data Latch
(Internal)
The all data in 16-bit common shift
register are copied to GS0 first data
latch at falling edge of LAT.
OUT0 GS First
Data Latch
(Internal)
Old 16-bit GS Data
New 16-bit GS Data
The all data in GS first data
latch are copied to GS
second data latch.
GS Second Data
Latch (Internal)
Old 256-bit GS Data
New 256-bit GS Data
When Auto data refresh mode is enabled,
the all data in GS second data latch are copied
to GS third data latch at 65536th GSCLK.
GS Third Data
Latch (Internal)
Old 256-bit GS Data
New 256-bit GS Data
OUT OFF
(GS data = FFFFh)
ON
Figure 20. Auto Data Refresh Function (XRFRESH = 0, LATMODE = 0)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
21
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
REGISTER AND DATA LATCH CONFIGURATION
The TLC59482 has one common shift register, one function control (FC) data latch, and a set of three data
latches: the first, second, and third grayscale (GS) data latches. The common shift register and FC data latch are
16 bits long and the GS data latches are 256 bits long. Figure 21 shows the common shift register and the data
latches configuration.
LSB
SCLK
MSB
16-bit
Common
Shift Register
LOAD
0
SIN
SOUT
15
16
OUT15 GS Data Latch (Internal)
OUT14 GS Data Latch (Internal)
OUT13~2 GS Data Latch (Internal)
OUT1 GS Data Latch (Internal)
OUT0 GS Data Latch (Internal)
12
16
16
16
GS
First Latch
for OUT0
0
Latch Signal for GS Second
Data Latch (Internal)
GS
First Latch
for OU14
GS
First Latch
for OUT1
31 32
15 16
16
16
16
16
LSB
223 224
MSB
GS
First Latch
for OUT15
239 240
16
LSB
MSB
GS
GS
Second Latch Second Latch
for OUT1
for OUT0
16
GS
GS
Second Latch Second Latch
for OUT15
for OUT14
239 240
223 224
255
16
16
31 32
15 16
0
Latch Signal for GS Third
Data Latch (Internal)
16
MSB
LSB
GS
Third Latch
for OUT0
0
Latch Signal for FC
Data Latch (Internal)
255
16
GS
Third Latch
for OUT1
GS
Third Latch
for OUT14
223 224
31 32
15 16
GS
Third Latch
for OUT15
239 240
255
16
LSB
MSB
LAT
DIN
16
Function Control (FC) Data Latch
0
15
256
16
To Constant Current Output/
PWM Timing Control/Data Latch
Control Circuit
To PWM Timing
Control Circuit
Figure 21. Shift Register and Data Latch Configuration
22
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
16-Bit Common Shift Register
The 16-bit common shift register is used to shift data from the SIN pin into the TLC59482. The data shifted into
the register are used for GS and FC data. The LSB of the common shift register is connected to SIN and the
MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all 16 bits
are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is powered up,
the data in the 16-bit common shift register are set to '0'.
First, Second, and Third Grayscale Data Latch
The first, second, and third grayscale (GS) data latches are each 256 bits long, and set the PWM timing for each
constant-current output. The on-time of all constant-current outputs is controlled by the data in the third GS data
latch. The 16-bit data are copied to the first GS data latch indicated by the GS data latch address counter when
the WRTGS command is input. The 256-bit GS data for OUTn in the first data latch are copied to the second GS
data latch when the LATGS command is input. The 256-bit data in the second data latch are copied to the third
GS data latch when the 65,536th GSCLK occurs with the XRFRESH bit in the FC data latch set to ‘0’. When the
XRFRESH bit is '1', the 256-bit data in the first data latch are copied to the second and third data latch at the
same time. When the device powers up, all constant-current outputs are forced off until GS data are written to
the third data latch. The GS data write sequence is shown in Figure 22 and Figure 23.
SIN
GS0
0A
GS15 GS15 GS15 GS15 GS15
15B 14B
13B
12B 11B
GS15 GS15 GS15 GS15 GS15 GS15
3B
1B
2B
6B
5B
4B
GS14 GS14 GS14
14B 13B
15B
GS15
0B
SCLK
1
2
3
4
5
10
11
12
13
14
15
16
1
Dashed LAT
timing is accepted.
2
3
LAT
0 or 1 SCLK rising edge must
be input while LAT is high.
Shift Register
LSB Data
(Internal)
GS0
0A
GS15 GS15 GS15 GS15
15B 14B
13B
12B
GS15 GS15 GS15 GS15 GS15 GS15
6B
4B
5B
3B
1B
2B
GS15
0B
GS14 GS14
15B 14B
Shift Register
LSB+1 Data
(Internal)
GS0
1A
GS0 GS15 GS15 GS15
0A
15B
14B
13B
GS15 GS15 GS15 GS15 GS15 GS15
6B
7B
5B
4B
3B
2B
GS15
1B
GS15 GS14
0B
15B
Shift Register
MSB-1 Data
(Internal)
GS0
14A
GS0
13A
GS0
12A
GS0
11A
GS0
10A
GS0
4A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
GS15
15B
GS15
14B
GS15 GS15
13B 12B
GS0
14A
GS0
13A
GS0
12A
GS0
11A
GS0
5A
GS0
4A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
SOUT
GS0
15A
GS Data Latch
Address Counter
(Internal)
OUT15
GS15
GS15 GS15
15B
14B 13B
The GS data latch address counter value is decreased by 1
for every WRTGS command input. When the counter value is
‘0’, if the command is input, then the value becomes ‘15’.
OUT14
The data in the 16-bit common shift register are
copied to the first data latch of OUTn shown
by the GS data latch address counter.
OUT15 GS First
Data Latch
(Internal)
Old 16-bit GS Data
New 16-bit GS Data
OUT0 GS First
Data Latch
(Internal)
GS Second Data
Latch (Internal)
GS Third Data
Latch (Internal)
Figure 22. 16-Bit GS Data Write (WRTGS) Command
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
23
TLC59482
SBVS218 – DECEMBER 2012
SIN
GS1
0B
www.ti.com
GS0
15B
GS0
14B
GS0
13B
GS0
12B
GS0
11B
GS0
6B
GS0
5B
GS0
4B
GS0
3B
GS0
1B
GS0
2B
GS0
0B
GS15 GS15 GS15
15C 14C 13C
Dotted line LAT
timing is accepted.
SCLK
1
2
3
4
5
10
11
12
Dashed LAT timing
is accepted.
13
14
15
1
16
2
3
LAT
2 or 3 SCLK rising edges must
be input while LAT is high.
Shift Register
LSB Data
(Internal)
GS1
0B
GS0
15B
GS0
14B
GS0
13B
GS0
12B
GS0
6B
GS0
5B
GS0
4B
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS15 GS15
15C 14C
Shift Register
LSB+1 Data
(Internal)
GS1
1B
GS1
0A
GS0
15B
GS0
14B
GS0
13B
GS0
7B
GS0
6B
GS0
5B
GS0
4B
GS0
3B
GS0
2B
GS0
1B
GS0 GS15
0B
15C
Shift Register
MSB-1 Data
(Internal)
GS1
14B
GS1
13A
GS1
12A
GS1
11A
GS1
10A
GS1
4A
GS1
3A
GS1
2A
GS1
1A
GS1
0A
GS0
15B
GS0
14B
GS0
13B
GS0
12B
GS1
14A
GS1
13A
GS1
12A
GS1
11A
GS1
5A
GS1
4A
GS1
3A
GS1
2A
GS1
1A
GS1
0A
GS0
14B
GS0
13B
SOUT
GS1
15B
GS0
15B
OUT1
GS Data Latch
Address Counter
(Internal)
OUT0
OUT15
OUT0
OUT15 GS First
Data Latch
(Internal)
All data in the 16-bit common shift
register are copied to the first GS0 data latch.
OUT0 GS First
Data Latch
(Internal)
Old 16-Bit GS Data
New 16-Bit GS Data
All data in the first GS data latch are copied
to the second GS data latch.
GS Second Data
Latch ( Internal)
Old 256-Bit GS Data
New 256-Bit GS Data
When the auto data refresh mode is disabled,
all data in the first GS data latch are copied
to both the second and third GS data latches.
GS Third Data
Latch (Internal)
Old 256-Bit GS Data
New 256-Bit GS Data
Figure 23. 256-Bit GS Data Latch (LATGS) Command (LATMODE = 0)
24
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
Function Control (FC) Data Latch
The function control (FC) data latch is 16 bits long. This latch sets the brightness control (BC) data, auto data
refresh, enables or disables the display timing reset, and selects the data latch mode. When the device is
powered on, the data in the FC data latch are set to the default values, as shown in Table 5.
Table 5. Function Control Data Latch Bit Description
BIT
NUMBER
BIT
NAME
DEFAULT
VALUE
(Binary)
0 (LSB) to 3
N/A
0000
4-9
BC
DESCRIPTION
No applicable bit
100000
Global brightness (BC) control bit (000000-111111).
This 6-bit data controls all output current with 64 steps between 0% and 100%
of the maximum current determined by a external resistor. When all bits are ‘0’,
all outputs are off. When the device is powered on, all output current are set to
approximately 50%.
10
XRFRESH
0
Auto data refresh mode bit (0 = enabled, 1 = disabled).
If the LATGS command is input while this bit is '1', all data in the first grayscale
(GS) data latch are copied to both the second and third GS data latches. All
OUTn are forced off and the GS counter is also reset to '0'.
If the LATGS command is input while this bit is '0', all data in the first GS data
latch are only copied to the second GS data latch. All data in the second GS
data latch are copied to the third GS data latch when the GS counter reaches
the maximum count value of 65,535. No OUTn are forced off and the GS
counter continues counting.
11
TMRSTEN
0
Display timing reset enable bit (0 = disabled, 1 = enabled).
If the TMGRST command is input while this bit is '1', the GS counter is reset to
'0'. When this occurs, all OUTn are forced off. When this bit is '0', even if the
TMGRST command is input, the GS counter is not reset to '0'.
12-14
N/A
000
15 (MSB)
LATMODE
0
No applicable bit
Latch mode select bit (0 = 15 WRTGS + 1 LATGS mode, 1 = 16 WRTGS + 1
LATGS mode).
When this bit is '1', The commands for all GS data writes are (16 × WRTGS + 1
LATGS). The 16th WRTGS command is required to latch the last GS input 16bit data to the first GS data latch.
When this bit is '0', the commands for all GS data writes are (15 × WRTGS + 1
LATGS). The 16th WRTGS command is not required to latch the last GS input
16-bit data to the first GS data latch.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
25
TLC59482
SBVS218 – DECEMBER 2012
www.ti.com
Display Timing Reset Function
This function allows users to reset the GS counter using the TMGRST command described in Table 6. This
function is enabled when the TMRSTEN bit in the FC control data latch is ‘1’. The grayscale counter is reset to '0'
when the TMGRST command is input. All OUTn are forced off. Refer to Figure 26 for a display timing reset
functional timing diagram
Table 6. Function Commands Description
SCLK RISING
EDGES
WHILE LAT IS HIGH
COMMAND NAME
DESCRIPTION
0 or 1
The 16-bit data in the 16-bit common shift register are copied to the 16-bit GS latch in the
first latch selected by the GS data latch address counter. Refer to Figure 22 for a timing
diagram of this command operation.
LATGS
(256-bit GS data
latch)
2 or 3
All data in the first GS data latch are only copied to the second GS data latch when the
XRFRESH bit in the FC data latch is ‘0’, All data in the first GS data latch are copied to both
the second and third GS data latches when the XRFRESH bit in the FC data latch is '1'. The
GS data latch address counter is initialized to OUT15 at the same timing. Refer to Figure 23
for a timing diagram of this command operation.
READFC
(FC data read)
4 or 5
The 16-bit data in the FC data latch are copied to the 16-bit shift register. The loaded data
can be read from SOUT synchronized with the SCLK rising edge. Refer to Figure 24 for a
timing diagram of this command operation.
WRTFC
(FC data write)
10 or 11
The 16-bit data in the 16-bit common shift register are copied to the FC data latch. Refer to
Figure 25 for a timing diagram of this command operation.
TMGRST
(display timing reset)
12 or 13
The GS counter is reset to '0' and all constant-current outputs (OUTn) are forced off when
the TMRSTEN bit in the FC data latch is ‘1’. However, the GS data in the third data latch
are not updated. Refer to Figure 26 for a timing diagram of this command operation.
FCWRTEN
(FC write enable)
14 or 15
FC writes are enabled by this command. This command must always be input before the
FC data write occurs. Refer to Figure 25 for a timing diagram of this command operation.
WRTGS
(16-bit GS data write)
Function Commands
The TLC59482 has six commands that can be input with SCLK and LAT signals: WRTGS. LATGS, READFC,
WRTFC, TMGRST, and FCWRTEN. Refer to Figure 21 to Figure 26 for detailed command input timing diagrams
for each command. Each command function is described in Table 6.
SIN
1
(1)
*1
1
1
1
1
1
1
1
1
1
1
Dashed LAT
timing is accepted.
SCLK
1
2
3
4
5
10
11
12
13
14
15
1
16
2
3
4
LAT
Dashed LAT timing
is also accepted.
4 or 5 SCLK rising edges must
be input while LAT is high.
16-bit FC data are loaded to the 16-bit
common shift register at the LAT signal falling edge.
FC
15
SOUT
FC
14
FC
13
FC
12
Figure 24. FC Data Read (READFC) Command Timing Diagram
26
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SBVS218 – DECEMBER 2012
*1
SIN
*1
*1
*1
*1
FC
15
*1: Don’t Care
FC
13
FC
14
FC
11
FC
12
FC
10
FC
9
FC
1
FC
0
Dotted line LAT
timing is accepted.
Dotted line LAT
timing is accepted.
SCLK
1
2
3
15
16
1
2
3
4
5
6
7
15
16
LAT
14 or 15 rising edge of SCLK is needed
to be input while LAT is high level for
FC write enable.
Dotted line LAT timing
is accepted too.
16-bit FC
Data Latch
(Internal)
10 or 11 rising edge of SCLK is needed
to be input while LAT is high level for
FC write enable.
Old 16-bit FC Data
New 16-bit FC Data
The data in 16-bit common shift register are loaded to
FC data latch at LAT signal falling edge.
FC
15
SOUT
Figure 25. FC Data Write Enable (FCWRTEN) and FC Data Write (WRTFC) Command Timing Diagram
SIN
1
(1)
1
1
1
1
1
1
1
1
1
1
1
Dashed LAT
timing is accepted.
SCLK
1
2
3
4
5
10
11
12
13
14
15
1
16
2
3
Dashed LAT timing
is also accepted.
LAT
12 or 13 SCLK rising edges are required
to be input while LAT is high.
RSTENA in
FC Data Latch
(Internal)
1
GS counter is reset at the LAT
signal falling edge.
GS Counter
(Internal)
0
1
2
GSCLK
All OUTn are forced off at
the LAT signal falling edge.
OUT
OFF
OFF
ON
Figure 26. Display Timing Reset (TMGRST) Command Timing Diagram
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
27
TLC59482
SBVS218 – DECEMBER 2012
GS0 GS15 GS15
15A
14A
SIN 0
www.ti.com
GS15
1A
GS15
0A
GS14 GS14
15A 14A
GS14
1A
GS14
0A
GS13 GS1
15A 15A
GS1
14A
GS1
0A
GS1
1A
GS0
15A
GS0
3A
GS0
1A
GS0
2A
GS0
0A
SCLK
1
2
15
16
Dashed LAT timing is also accepted.
17
18
31
32
225
226
239
241
240
253
254
255
256
LAT
1st WRTGS
Command
2nd WRTGS
Command
15th WRTGS
Command
LATGS
Command
16-Bit Common
Shift Register
(Internal)
SOUT
GS0
15
LATMODE Bit
in FC Data Latch
(Internal)
GS0
14
GS0
1
GS0
0
GS15
15A
GS15 GS15
1A
0A
GS14
15A
GS2
14A
GS2
1A
GS1
15A
GS2
0A
GS1
2A
GS1
1A
GS1
0A
GS0
15A
0
The counter is decreased when
“WRTGS” command is input.
The counter is set to OUT15 when
“LATGS” command is input.
GS Data Latch
Address Counter OUT15
OUT15
(Internal)
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 1’st “WRTGS” command
OUT15 GS First
Data Latch
Old 16-bit GS data
(Internal)
OUT14 GS First
Data Latch
(Internal)
GS15
14A
OUT14
OUT14
OUT13
OUT1
OUT0
OUT1
OUT15
OUT0
New 16bit GS data
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 2’nd “WRTGS” command.
Old 16-bit GS data
New 16-bit GS data
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 15’th “WRTGS” command
OUT1 GS First
Data Latch
(Internal)
New 16-bit
GS data
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 16’th “LATGS” command.
Old 16-bit
GS data
Old 16-bit GS data
OUT0 GS First
Data Latch
(Internal)
The all data in GS first data latch
are copied to GS second data latch.
GS Second
Data Latch
(Internal)
Old 256-bit
GS data
The all data in GS first data latch are copied
to both GS second and third data latch
when Auto data refresh mode is disabled.
GS Third
Data Latch
(Internal)
New 16-bit
GS Data
New 256-bit
GS Data
Figure 27. 256-Bit GS Data Write Sequence Timing Diagram
(15 × WRTGS + 1 LATGS, LATMODE = 0)
28
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
TLC59482
www.ti.com
SIN
SBVS218 – DECEMBER 2012
GS0 GS15
0
15A
GS15
1A
GS15
0A
GS14
15A
GS14
1A
GS14
0A
GS13 GS0
3A
15A
GS0
2A
GS0
0A
GS0
1A
1
(1)
1
1
1
1
SCLK
1
15
16
17
Dotted line LAT timing is also accepted.
31
32
253
254
255
256
257
269
270
271
272
LAT
1st WRTGS
Command
2nd WRTGS
Command
16th WRTGS
Command
LATGS
Command
16-Bit Common
Shift Register
(Internal)
SOUT
GS0
15
GS0
14
GS0
1
GS0
0
GS15
15A
GS15 GS15 GS15
14A
1A
0A
GS14
15A
LATMODE Bit
in FC Data Latch 1
(Internal)
The counter is decreased when
The counter is set to OUT15 when
the WRTGS command is input.
the LATGS command is input.
GS Data Latch
Address Counter OUT15
OUT14
OUT15
OUT14
(Internal)
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 1’st “WRTGS” command
OUT15 GS First
Data Latch
New 16-Bit GS Data
Old 16-bit GS Data
(Internal)
GS1
14A
GS1
1A
GS1
0A
GS0
15A
GS1
14A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
OUT13
OUT0
OUT15
OUT15
All data in the 16-bit common shift
register are copied to the first GS1 data
latch at the 2nd WRTGS command.
OUT15 GS First
Data Latch
(Internal)
Old 16-Bit GS Data
New 16-Bit GS Data
All data in the16-bit common shift
register are copied to the first GS0 data
latch at the 16th WRTGS command.
OUT0 GS First
Data Latch
(Internal)
Old 16-Bit GS Data
New 16-Bit GS Data
The all data in GS first data latch
are copied to GS second data latch.
GS Second
Data Latch
(Internal)
Old 256-bitGS Data
All data in the first GS data latch are copied to both the second and
third GS data latches when the auto data refresh mode is disabled.
GS Third
Data Latch
(Internal)
New 256-Bit
GS Data
.
Old 256-Bit GS Data
Figure 28. 256-Bit GS Data Write Sequence Timing Diagram
(16 × WRTGS + 1 LATGS, LATMODE = 1)
NOISE REDUCTION
Large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs
turn on or off simultaneously. These large current surges can introduce detrimental noise and electromagnetic
interference (EMI) into other circuits.
The TLC59482 turns the outputs on with a series delay for each group independently to provide a soft-start
feature. The output current sinks are grouped into four groups. The first output group that is turned on/off are
OUT0, OUT7, OUT8, and OUT15; the second output group is OUT1, OUT6, OUT9, and OUT14; the third output
group is OUT2, OUT5, OUT10, and OUT13; and the fourth output group is OUT3, OUT4, OUT11, and OUT12.
Each output group is turned on and off sequentially with a 5-ns (typical) delay between the groups. However,
each output on/off is controlled by the GS clock.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC59482DBQ
ACTIVE
SSOP
DBQ
24
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC59482
TLC59482DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC59482
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
