TLK10031CTR

Order Now Product Folder Support & Community Tools & Software Technical Documents TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver 1 Device Overview 1.1 Features 1 • Single Channel Multi-Rate Transceiver • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet Standards • Supports all CPRI and OBSAI Data Rates up to 10 Gbps • Supports Multi-Rate SERDES Operation with up to 10.3125 Gbps Data Rate on the High Speed Side and up to 5 Gbps on the Low Speed Side • Differential CML I/Os on Both High Speed and Low Speed Sides • Interface to Backplanes, Passive and Active Copper Cables, or SFP+ Optical Modules • Selectable Reference Clock with Multiple Output Clock Options • Supports PRBS, CRPAT, CJPAT, High/Low/MixedFrequency Patterns, and KR Pseudo-Random Pattern Generation and Verification, Square-Wave Generation 1.2 • • Applications 10GBASE-KR Compliant Backplane Links 10 Gigabit Ethernet Switch, Router, and Network Interface Cards 1.3 • Supports Data Retime Operation • Two Power Supplies: 1 V (Core), and 1.5 or 1.8 V (I/O) • No Power Supply Sequencing Requirements • Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed and Low Speed Sides • Loss of Signal (LOS) Detection • Supports 10G-KR Link Training, Forward Error Correction, Auto-Negotiation • Jumbo Packet Support • JTAG; IEEE 1149.1 Test Interface • Industry Standard MDIO Control Interface • 65nm Advanced CMOS Technology • Industrial Ambient Operating Temperature (–40°C to 85°C) • Power Consumption: 800 mW (Nominal) • • Proprietary Cable/Backplane Links High-Speed Point-to-Point Transmission Systems Description The TLK10031 is a single-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode. Device Information (1) PART NUMBER TLK10031 (1) PACKAGE BODY SIZE (NOM) FCBGA (144) 13.00mm x 13.00mm For more information, see Section 12, Mechanical Packaging and Orderable Information. Simplified Schematic TLK10031 MAC XGXS 10GBASE-KR BACKPLANE XAUI MDC MDIO 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6 7 Parametric Measurement Information ............. 16 Detailed Description ................................... 18 1.1 Features .............................................. 1 1.2 Applications ........................................... 1 7.1 Overview 1.3 Description ............................................ 1 7.2 Functional Block Diagrams.......................... 18 2 3 4 Revision History ......................................... 2 Description ................................................ 3 Terminal Configuration and Functions .............. 4 5 Specifications 8 5.1 8 Pin Attributes ......................................... 4 4.1 ............................................ Absolute Maximum Ratings .......................... ESD Ratings .......................................... Recommended Operating Conditions ................ Thermal Information .................................. 5.2 5.3 5.4 5.5 Electrical Characteristics: High Speed Side Serial Transmitter ......................................... Electrical Characteristics: High Speed Side Serial Receiver ............................................. Electrical Characteristics: Low Speed Side Serial Transmitter .......................................... Electrical Characteristics: Low Speed Side Serial Receiver ............................................. 5.6 5.7 5.8 5.9 ...... Electrical Characteristics: Clocks ................... Timing Requirements ............................... Typical Characteristics .............................. Electrical Characteristics: LVCMOS (VDDO): 5.10 5.11 5.12 8 8 8 9 10 9 10 11 12 13 13 13 14 11 ............................................ 18 ................................. 20 ........................... 26 7.5 Register Maps ....................................... 55 Applications and Implementation ................. 134 8.1 Application Information ............................ 134 8.2 Typical Application ................................. 134 Power Supply Recommendations ................. 136 Layout ................................................... 137 10.1 Layout Guidelines .................................. 137 10.2 Layout Example .................................... 141 Device and Documentation Support .............. 142 11.1 Receiving Notification of Documentation Updates. 142 11.2 Community Resources............................. 142 11.3 Trademarks ........................................ 142 11.4 Electrostatic Discharge Caution ................... 142 11.5 Glossary............................................ 142 7.3 Feature Description 7.4 Device Functional Modes 12 Mechanical Packaging and Orderable Information ............................................. 142 12.1 Packaging Information ............................. 142 15 2 Revision History Changes from Revision B (August 2015) to Revision C • Changed the Description of bits 12, 8, and 1 in Table 7-13 ................................................................... 57 Changes from Revision A (August 2015) to Revision B • • 2 Page Changed the PD Nominal value From: 1.6 W To: 800 mW in the Recommended Operating Conditions table .......... 8 Changed the PD Worst case supply voltage value From: 2.3 W To 1.15 W in the Recommended Operating Conditions table ....................................................................................................................... 8 Changes from Original (July 2015) to Revision A • • • Page Page Changed the TLK10031 Pinout image to include the column numbers ....................................................... 4 Changed Pin B1 From: 1NINA To: INA1N; Changed Pin E1 From: INA1P To: INA3N in the TLK10031 Pinout image 4 Added Pin numbers: H3, L6, and M1 To Pin VSS in the Pin Description - Power Pins table .............................. 7 Revision History Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 3 Description While operating in the 10GBASE-KR mode, the TLK10031 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10031 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications. While operating in the General Purpose SERDES mode, the TLK10031 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10031 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates. The TLK10031 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported. The TLK10031 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of data. Each output port (either high speed or low speed) can be configured to output data coming from any of the device’s input ports. The switching can be initiated through either a hardware pin or through software control, and can be configured to occur either immediately or after the end of the current packet. This allows for switching between data sources without packet corruption. Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. The TLK10031 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes, allowing for asynchronous clocking. The TLK10031 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes. The TLK10031 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen. The TLK10031 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The low speed side of the TLK10031 is ideal for interfacing with an FPGA, ASIC, MAC, or network processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The device supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems. Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 3 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 4 Terminal Configuration and Functions A 13-mm x 13-mm, 144-pin PBGA package with a ball pitch of 1 mm is used. TLK10031 Pinout 2 1 A INA1P VSS B INIA1N INA2P 3 INA0N VSS C VSS INA2N D INA3P VDDA_LS VSS E INA3N VSS VSS VDDA_LS G VSS VDDA_LS H VSS VSS F VDDRA_LS 4 5 6 INA0P VSS OUTA0P OUTA0N 7 PDTRXA_N 8 RSV0 9 10 11 12 RSV1 VSS HSRXAN VSS OUTA1P OUTA1N VSS TMS PRBSEN LS_OK_IN_A VSS HSRXAP OUTA2P CLKOUTAP CLKOUTAN OUTA2N VSS VDDO0 TDI AMUX1 VSS TDO VPP TCK OUTA3N VSS TRST_N VDDD DVDD VDDD LOSA PRTAD0 VDDRA_HS HSTXAN OUTA3P VDDT_LS VSS VDDD DVDD VSS VDDT_HS VSS VDDA_HS VSS VSS VDDT_LS VSS DVDD VSS DVDD PRTAD1 VDDA_HS VSS RSV2 VSS VSS RESETN _ VDDD DVDD VDDD RSV3 MODE_SEL VSS RSV4 LS_OK_OUT_A VSS J VSS VDDA_LS VSS GPI1 VSS PRTAD3 MDIO MDC PRBS_PASS GPI0 K VSS VSS VDDRA_LS VSS VSS VSS VDDO1 RSV5 REFCLK1P REFCLK1N L VSS VSS VSS VSS VSS VSS VSS GPI2 PRTAD2 TESTEN M VSS VSS VSS VSS VSS VSS VSS PRTAD4 ST REFCLK0P 4.1 AMUX0 VSS VSS HSTXAP VDDRA_HS VSS VSS RSV6 VSS RSV7 REFCLK0N VSS Pin Attributes Table 4-1. Pin Description - Signal Pins PIN NO. I/O TYPE DESCRIPTION HSTXAP HSTXAN D12 E12 Output CML VDDA_HS High Speed Transmit Output. HSTXAP and HSTXAN comprise the high speed side transmit direction differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. HSRXAP HSRXAN B12 A12 Input CML VDDA_HS High Speed Receive Input. HSRXAP and HSRXAN comprise the high speed side receive direction differential serial input signal. These CML input signals must be AC coupled. INA[3:0]P/N D1/E1 B2/C2 A1/B1 A4/A3 Input CML VDDA_LS Low Speed Inputs. INAP and INAN comprise the low speed side transmit direction differential input signals. These signals must be AC coupled. OUTA[3:0]P/N F3/E3 C4/C5 B5/B6 A6/A7 Output CML VDDA_LS Low Speed Outputs. OUTAP and OUTAN comprise the low speed side receive direction differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. NAME LOSA E9 Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver Receive Loss Of Signal (LOS) Indicator. LOS = 0: Signal detected. LOS = 1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential input signal swing of ≤75 mVpp, LOSA is asserted (if enabled). If the input signal is greater than 150 mVpp, LOSA is deasserted. Outside of these ranges, the LOS indication is undefined. Other functions can be observed on LOSA real-time, configured via MDIO During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is floating. It is highly recommended that LOSA be brought to an easily accessible point on the application board (header) in the event that debug is required. LS_OK_IN_A LS_OK_OUT_A 4 B10 Input LVCMOS 1.5V/1.8V VDDO0 D9 Output LVCMOS 1.5V/1.8V VDDO 40Ω Driver Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_A = 0: Link partner receive lanes not aligned. LS_OK_IN_A = 1: Link partner receive lanes aligned Transmit Lane Alignment Status Indicator. Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_A = 0: Link partner transmit lanes not aligned. LS_OK_OUT_A = 1: Link partner transmit lanes aligned. Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Table 4-1. Pin Description - Signal Pins (continued) PIN NAME PDTRXA_N NO. A8 I/O TYPE DESCRIPTION Input LVCMOS 1.5V/1.8V VDDO0 Transceiver Power Down. When this pin is held low (asserted), the channel is placed in power down mode. When deasserted, the channel operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. RESERVED PINS RSV[7:0] L12, K12, K8, H12, H9, G12, A10, A9 Reserved. It should be left unconnected in the device application. REFERENCE CLOCKS, OUTPUT CLOCKS, AND CONTROL AND MONITORING SIGNALS REFCLK0P/N M10 M11 Input LVDS/ LVPECL DVDD Reference Clock Input Zero. This differential input is a clock signal used as a reference to channel A. The reference clock selection is done through MDIO. This input signal must be AC coupled. If unused, REFCLK0P/N should be pulled down to GND through a shared 100 Ω resistor. REFCLK1P/N K9 K10 Input LVDS/ LVPECL DVDD Reference Clock Input One. This differential input is a clock signal used as a reference to channel A. The reference clock selection is done through MDIO. This input signal must be AC coupled. If unused, REFCLK1P/N should be pulled down to GND through a shared 100 Ω resistor. CLKOUTAP/N C9 C10 Channel Output Clock. By default, this outputs is enabled, and outputs the high speed side recovered byte clock (high speed line rate divided by 16 or 20). Optionally, they can be configured to output the VCO clock divided by 2. (Note: for full rates, VCO/2 predivided clocks will be equivalent to the line rate divided by 8; for sub-rates, VCO/2 predivided clocks will be equivalent to the line rate divided by 4). Output CML DVDD These CML outputs must be AC coupled. During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N asserted low), or register-based power down, these pins are floating. PRBSEN PRBS_PASS B9 J9 Input LVCMOS 1.5V/1.8V VDDO0 Output LVCMOS 1.5V/1.8V VDDO1 40Ω Driver Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides. The PRBS 27-1 pattern is selected by default, and can be changed through MDIO. Receive PRBS Error Free (Pass) Indicator. When PRBS test is enabled (PRBSEN=1): PRBS_PASS = 1 indicates that PRBS pattern reception is error free. PRBS_PASS = 0 indicates that a PRBS error is detected. The high speed or low speed side, and lane (for low speed side) that this signal refers to is chosen through MDIO. During device reset (RESET_N asserted low) this pin is driven high. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is floating. It is highly recommended that PRBS_PASS be brought to easily accessible point on the application board (header), in the event that debug is required. ST MODE_SEL M9 Input LVCMOS 1.5V/1.8V VDDO[1:0] H10 Input LVCMOS 1.5V/1.8V VDDO[1:0] MDIO Select. Used to select Clause 22 (=1) or Clause 45 (=0) operation. Note that selecting clause 22 will impact mode availability. See MODE_SEL. A hard or soft reset must be applied after a change of state occurs on this input signal. Device Operating Mode Select. Used together with ST pin to select device operating mode. See Table 7-2 for details. MDIO Port Address. Used to select the MDIO port address. PRTAD[4:1] selects the MDIO port address. The TLK10031 has one MDIO port addresses. Selecting a unique PRTAD[4:1] per TLK10031 device allows 16 TLK10031 devices per MDIO bus. M8 J6 L9 G9 E10 Input LVCMOS 1.5V/1.8V VDDO[1:0] RESET_N H5 Input LVCMOS 1.5V/1.8V VDDO01 Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10 µs after device power stabilization. MDC J8 Input LVCMOS with Hysteresis 1.5V/1.8V VDDO1 MDIO Clock Input. Clock input for the MDIO interface. Note that an external pullup is generally not required on MDC except if driven by an opendrain/open-collector clock source. PRTAD[4:0] The TLK10031 responds if the 4 MSB’s of the port address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1], and PA[0] = 0. PRTAD0 is not needed for port addressing, but can be used as a general purpose input pin to control the switching function or the stopwatch latency measurement. If these functions are not needed, PRTAD0 should be grounded on the application board. Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 5 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Table 4-1. Pin Description - Signal Pins (continued) PIN NAME I/O TYPE NO. DESCRIPTION MDIO Data I/O. MDIO interface data input/output signal for the MDIO interface. This signal must be externally pulled up to VDDO using a 2-kΩ resistor. During device reset (RESET_N asserted low) this pin is floating. During software initiated power down the management interface remains active for control register writes and reads. Certain status bits will not be deterministic as their generating clock source may be disabled as a result of asserting either power down input signal. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is driven normally. J7 Input/ Output LVCMOS 1.5V/1.8V VDDO1 25Ω Driver C8 Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pullup) JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of the test port. In system applications where JTAG is not implemented, this input signal may be left floating. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. D6 Output LVCMOS 1.5V/1.8V VDDO0 50Ω Driver JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of the test port. When the JTAG port is not in use, TDO is in a high impedance state. During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. TMS B8 Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pullup) JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications where JTAG is not implemented, this input signal can be left unconnected. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. TCK D8 Input LVCMOS with Hysteresis 1.5V/1.8V VDDO0 JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan operation. In system applications where JTAG is not implemented, this input signal should be grounded. MDIO TDI TDO TRST_N E5 Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pulldown) JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal should be deasserted (high) during JTAG system testing, and otherwise asserted (low) during normal operation mode. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. TESTEN L10 Input LVCMOS 1.5V/1.8V VDDO1 Test Enable. This signal is used during the device manufacturing process. It should be grounded through a resistor in the device application board. The application board should allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO). L8, J4, J10 Input LVCMOS 1.5V/1.8V VDDO1 General Purpose Input. his signal is used during the device manufacturing process. It should be grounded through a resistor on the device application board. AMUX0 C11 Analog I/O SERDES Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. AMUX1 D4 Analog I/O SERDES Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. GPI0 6 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Table 4-2. Pin Description - Power Pins PIN NAME NO. I/O TYPE DESCRIPTION VDDA_LS/HS D2, F2, G2, J2, G10, F11 Input Power SERDES Analog Power. VDDA_LS and VDDA_HS provide supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board. VDDT_LS/HS F4, G4, F9 Input Power SERDES Analog Power. VDDT_LS and VDDT_HS provide termination and supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board. VDDD E6, F6, H6, E8, H8 Input Power SERDES Digital Power. VDDD provides supply voltage for the digital circuits internal to the SERDES. 1 V nominal. DVDD G6, E7, F7, H7, G8 Input Power Digital Core Power. DVDD provides supply voltage to the digital core. 1 V nominal. VDDRA_LS/HS C3, K3, J11 E11 Input Power SERDES Analog Regulator Power. VDDRA_LS and VDDRA_HS provide supply voltage for the internal PLL regulator for low speed and high speed sides respectively. 1.5 V or 1.8 V nominal. VDDO[1:0] K7 C7 Input Power LVCMOS I/O Power. VDDO0 and VDDO1 provide supply voltage for the LVCMOS inputs and outputs. 1.5 V or 1.8 V nominal. Can be tied together on the application board. VPP D7 Input Power Factory Program Voltage. Used during device manufacturing. The application must connect this power supply directly to DVDD. VSS A2, A5, A11, B3, B4, B7, B11, C1, C6, C12, D3, D5, D10, D11, E2, E4, F1, F5, F8, F10, F12, G1, G3, G5, G7, G11, H1, H2, H4, H3, H11, J1, J3, J5, J12, K1, K2, K4, K5, K6, K11, L1, L2, L3, L4, L5, L6, L7, L11, M1, M2, M3, M4, M5, M6, M7, M12 Ground Ground. Common analog and digital ground. Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 7 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE Supply voltage Input Voltage, VI UNIT MIN MAX DVDD, VDD_LS/HS, VDDT_LS/HS, VPP, VDDD –0.3 1.4 V VDDR_LS/HS, VDDO[1:0] –0.3 2.2 V LVCMOS, CML, Analog –0.3 Supply + 0.3 V 105 °C Operating Junction Temperature Characterized free-air operating temperature range –40 85 °C Storage temperature, Tstg -65 150 °C (1) (2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground (VSS). 5.2 ESD Ratings V(ESD) (1) (2) 5.3 Electrostatic discharge VALUE UNIT Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 (1) ±1000 V Charged Device Model (CDM), per JESD22-C101 (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions PARAMETER VDDD, VDD_LS/HS, DVDD, VDDT_LS/HS, VPP SERDES PLL regulator voltage VDDR_LS/HS LVCMOS I/O supply voltage VDDO[1:0] VDDD IDD TEST CONDITIONS Digital / analog supply voltages Supply current MIN NOM MAX UNIT 0.95 1.00 1.05 V 1.5V Nominal 1.425 1.5 1.575 1.8V Nominal 1.71 1.8 1.89 1.5V Nominal 1.425 1.5 1.575 1.8V Nominal 1.71 1.8 1.89 10.3 Gbps 650 DVDD + VPP 700 VDDT_LS/HS 600 VDDRA_LS 70 VDDRA_HS 70 VDDD Shutdown current VDDT PDTRXA_N Asserted 8 W 250 65 mA 7 VDDO REFCLK0P/N, REFCLK1P/N Random Jitter 1.15 85 VDDRA_HS/LS JR mW 300 VDDA ISD 800 Worst case supply voltage, temperature, and process. 10GBASE-KR, channel active, default swing and Clkout settings DVDD + VPP mA 10 Nominal Power dissipation V 650 VDDA_LS/HS VDDO[1:0] PD V 5 12kHz to 20MHz Specifications 1 ps Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 5.4 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Thermal Information NAME DESCRIPTION RθJA Junction-to-free air VALUE UNIT 25.5 °C/W ωJT Junction-to-package top 1.8 ωJB Junction-to-board 13.7 Custom Typical Application Board (1) RθJA Junction-to-free air 24.5 ωJT Junction-to-package top 0.9 ωJB Junction-to-board 11 (1) °C/W Custom Typical Application Board Characteristics: • 10x15 inches • 12 layer • 8 power/ground layers – 95% copper (1oz) • 4 signal layers – 20% copper (1oz) SPACER ΨJB = (TJ – TB)/(Total Device Power Dissipation) ΨJB = (TJ TJ = Device Junction Temperature ΨJB = (TJ TB = Temperature of PCB 1 mm from device edge. SPACER ΨJT = (TJ – TC)/(Total Device Power Dissipation) ΨJB = (TJ TJ = Device Junction Temperature ΨJB = (TJ TC = Hottest temperature on the case of the package. Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 9 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 5.5 www.ti.com Electrical Characteristics: High Speed Side Serial Transmitter PARAMETER TX Output differential peak-to-peak voltage swing, transmitter enabled VOD(p-p) MIN NOM MAX SWING = 0000 TEST CONDITIONS 50 130 220 SWING = 0001 110 220 320 SWING = 0010 180 300 430 SWING = 0011 250 390 540 SWING = 0100 320 480 650 SWING = 0101 390 570 770 SWING = 0110 460 660 880 SWING = 0111 530 750 1000 SWING = 1000 590 830 1100 SWING = 1001 660 930 1220 SWING = 1010 740 1020 1320 SWING = 1011 820 1110 1430 SWING = 1100 890 1180 1520 SWING = 1101 970 1270 1610 SWING = 1110 1060 1340 1680 SWING = 1111 1090 1400 1740 Transmitter disabled TX Output pre/post cursor emphasis voltage See register bits TWPOST1, TWPOST2, and TWPRE for deemphasis settings. See Figure 6-2 VCMT TX Output common mode voltage 100-Ω differential termination. DCcoupled. tskew Intra-pair output skew Serial Rate = 9.8304 Gbps Tr, Tf Differential output signal rise, fall time (20% to 80%), Differential Load = 100Ω Serial output total jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates) Serial Rate ≤ 3.072Gbps 0.35 JT1 Serial Rate > 3.072Gbps 0.28 Serial output deterministic jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates) Serial Rate ≤ 3.072Gbps 0.17 JD1 Serial Rate > 3.072Gbps 0.15 JR1 Serial output random jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates) Serial Rate > 3.072Gbps 0.15 JT2 Serial output total jitter (CPRI E.12.HV) Serial output deterministic jitter (CPRI E.12.HV) SDD22 Differential output return loss SCC22 Common-mode output return loss T(LATENCY) (1) (2) 10 Transmit path latency mVpp 30 Vpre/post JD2 UNIT –17.5/ –37.5% +17.5/ +37.5% VDDT - 0.25 * VOD(p-p) mV 0.045 24 UI ps UIpp UIpp UIpp 0.279 Serial Rate = 1.2288Gbps UIpp 0.14 50 MHz < f < 2.5 GHz 9 dB (1) dB 50 MHz < f < 2.5 GHz 6 dB 2.5 GHz < f < 7.5 GHz (2) dB 2.5 GHz < f < 7.5 GHz See See 10GBASE-KR mode see Figure 7-6 1GBASE-KX mode see Figure 7-9 General Purpose mode see Figure 7-13 Differential input return loss, SDD22 = 9 – 12 log10(f / 2500MHz)) dB Common-mode output return loss, SDD22 = 6 – 12 log10(f / 2500MHz)) dB Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 5.6 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Electrical Characteristics: High Speed Side Serial Receiver PARAMETER TEST CONDITIONS VID RX Input differential voltage, |RXP – RXN| VID(pp) RX Input differential peak-to-peak voltage swing, 2×|RXP – RXN| CI RX Input capacitance JTOL Differential input return loss tskew Intra-pair input skew t(LATENCY) (1) Receive path latency NOM MAX 50 600 Half/Quarter/Eighth Rate, AC Coupled 50 800 Full Rate, AC Coupled 100 1200 Half/Quarter/Eighth Rate, AC Coupled 100 1600 2 10GBASE-KR Jitter tolerance, test channel with mTC =1 (see Figure 5-1 for attenuation curve), PRBS31 test pattern at 10.3125 Gbps SDD11 MIN Full Rate, AC Coupled Applied sinusoidal jitter 0.115 Applied random jitter 0.130 Applied duty cycle distortion 0.035 Broadband noise amplitude (RMS) mV mVpp pF UIpp 5.2 50 MHz < f < 2.5 GHz 2.5 GHz < f < 7.5 GHz UNIT 9 See dB (1) 0.23 10GBASE-KR mode see Figure 7-6 1GBASE-KX mode see Figure 7-9 General Purpose mode see Figure 7-13 UI Differential input return loss, SDD11 = 9 – 12 log10(f / 2.5GHz)) dB Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 11 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 5.7 www.ti.com Electrical Characteristics: Low Speed Side Serial Transmitter PARAMETER VOD(pp) DE TEST CONDITIONS Transmitter output differential peak-to-peak voltage swing Transmitter output de-emphasis voltage swing reduction MIN NOM MAX SWING = 000 110 190 280 SWING = 001 280 380 490 SWING = 010 420 560 700 SWING = 011 560 710 870 SWING = 100 690 850 1020 SWING = 101 760 950 1150 SWING = 110 800 1010 1230 SWING = 111 830 1050 1270 DE = 0000 0 DE = 0001 0.42 DE = 0010 0.87 DE = 0011 1.34 DE = 0100 1.83 DE = 0101 2.36 DE = 0110 2.92 DE = 0111 3.52 DE = 1000 4.16 DE = 1001 4.86 DE = 1010 5.61 DE = 1011 6.44 DE = 1100 7.35 DE = 1101 8.38 DE = 1110 9.54 DE = 1111 10.87 100-Ω differential termination. DCcoupled. UNIT mVpp dB VDDT - 0.5 * VOD(p-p) VCMT Transmitter output common mode voltage tskew Intra-pair output skew tR, tF Differential output signal rise, fall time (20% to 80%) Differential Load = 100Ω JT Serial output total jitter 0.35 UI JD Serial output deterministic jitter 0.17 UI tskew Lane-to-lane output skew 50 ps 12 mV 0.045 Specifications 30 UI ps Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 5.8 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Electrical Characteristics: Low Speed Side Serial Receiver PARAMETER TEST CONDITIONS VID Receiver input differential voltage, |INP – INN| VID(pp) Receiver input differential peak-to-peak voltage swing 2×|INP – INN| CI Receiver input capacitance JTOL Jitter tolerance, total jitter at serial input (DJ + RJ) (BER 10-15) JDR Serial input deterministic jitter (BER 10-15) tskew Intra-pair input skew tlane-skew Lane-to-lane input skew 5.9 MIN NOM MAX Full Rate, AC Coupled 50 600 Half/Quarter Rate, AC Coupled 50 800 Full Rate, AC Coupled 100 1200 Half/Quarter Rate, AC Coupled 100 1600 2 Zero crossing, Half/Quarter Rate 0.66 Zero crossing, Full Rate 0.65 Zero crossing, Half/Quarter Rate 0.50 Zero crossing, Full Rate 0.35 UNIT mV mVdfpp pF UIp-p UIp-p 0.23 UI 30 UI Electrical Characteristics: LVCMOS (VDDO): PARAMETER VOH TEST CONDITIONS MIN NOM MAX IOH = 2 mA, Driver Enabled (1.8V) VDDO – 0.45 VDDO IOH = 2 mA, Driver Enabled (1.5V) 0.75 × VDDO VDDO IOL = –2 mA, Driver Enabled (1.8V) 0 0.45 IOL = –2 mA, Driver Enabled (1.5V) 0 0.25 × VDDO High-level output voltage UNIT V VOL Low-level output voltage VIH High-level input voltage 0.65 × VDDO VDDO + 0.3 V VIL Low-level input voltage –0.3 0.35 × VDDO V IIH, IIL Receiver only Low/High Input Current ±170 µA Driver only Driver Disabled Driver/Receiver With Pullup/Pulldown Driver disabled With Pull Up/Down Enabled IOZ CIN V ±25 ±195 Input capacitance 3 µA pF 5.10 Electrical Characteristics: Clocks PARAMETER TEST CONDITIONS MIN NOM MAX UNIT MHz Reference Clock (REFCLK0P/N, REFCLK1P/N) F Frequency FHSoffset Accuracy DC Duty cycle VID Differential input voltage CIN Input capacitance RIN Differential input impedance tRISE Rise/fall time 122.88 425 Relative to Nominal HS Serial Data Rate –100 100 Relative to Incoming HS Serial Data Rate –200 200 High Time 45% 50% 250 55% 2000 1 100 10% to 90% ppm mVpp pF Ω 50 350 ps 0 500 MHz Differential Output Clock (CLKOUTA/N) F Output frequency VOD Differential output voltage Peak to peak tRISE Output rise time 10% to 90%, 2pF lumped capacitive load, ACCoupled RTERM Output termination CLKOUTAP/N × P/N to DVDD 1000 2000 mVdfpp 350 50 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 ps Ω 13 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 5.11 Timing Requirements over recommended operating conditions (unless otherwise noted) TEST CONDITIONS MIN NOM MAX UNIT MDIO tperiod MDC period tsetup MDIO setup to ↑ MDC thold MDIO hold to ↑ MDC tvalid MDIO valid from MDC ↑ See Figure 6-3 100 ns 10 ns 10 ns 0 40 ns JTAG tperiod TCK period tsetup TDI/TMS/TRST_N setup to ↑ TCK thold TDI/TMS/TRST_N hold from ↑ TCK tvalid TDO delay from TCK Falling 14 See Figure 6-4 66.67 ns 3 ns 5 0 Specifications ns 10 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 5.12 Typical Characteristics 40 Fitted Attenuation (dB) 35 30 25 20 15 10 5 0 1000 2000 3000 4000 Frequency (MHz) 5000 6000 Time 20 ps/div G001 Figure 5-1. 10GBASE-KR Fitted Channel Attenuation Limit Figure 5-2. Eye Diagram of the TLK10031 at 10.3125 Gbps Under Nominal Conditions Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 15 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 6 Parametric Measurement Information 0.5 * VDE * VOD(pp) VCMT 0.5 * VOD(pp) 0.25 * VDE * VOD (pp) tr , t f bit time 0.25 * VOD (pp) Figure 6-1. Transmit Output Waveform Parameter Definitions +V 0/0 +V pst +Vpre +Vss 0 -Vss -Vpre -V pst -V 0/0 UI h -1 = TWPRE (0% -17 .5% for typical application) setting h 1 = TWPOST1 (0 % -37.5 % for typical application) setting h 0 = 1 - |h 1| - |h -1 | V0 /0 = Output Amplitude with TWPRE = 0% , TWPOST = 0 %. Vss = Steady State Output Voltage = V0/0 * | h1 + h 0 + h- 1| Vpre = PreCursor Output Voltage = V0 /0 * | -h 1 – h 0 + h -1| Vpst = PostCursor Output Voltage = V0/0 * | - h1 + h 0 + h- 1| Figure 6-2. Pre/Post Cursor Swing Definitions MDC tPERIOD tSETUP tHOLD MDIO Figure 6-3. MDIO Read/Write Timing 16 Parametric Measurement Information Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 TCK tPERIOD tSETUP tHOLD TDI/TMS/ TRST_N tVALID TDO Figure 6-4. JTAG Timing Parametric Measurement Information Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 17 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7 Detailed Description 7.1 Overview Various interfaces of the TLK10031 device are shown in Figure 7-1. A simplified block diagram of both the transmit and receive data path is shown in Figure 7-2. This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low speed side and the other on the high speed side. The core logic block that lies between the two SERDES blocks carries out all the logic functions including channel synchronization, lane alignment, 8B/10B and 64B/66B encoding/decoding, as well as test pattern generation and verification. The TLK10031 provides a management data input/output (MDIO Clause 22/45) interface as well as a JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10031 pin functions is provided in Section 4. 7.2 Functional Block Diagrams INA0P/N INA1P/N INA2P/N High Speed Outputs Low Speed Inputs HSTXAP/N INA3P/N DATA PATH High Speed Inputs OUTA0P/N OUTA1P/N OUTA2P/N Low Speed Outputs HSRXAP/N OUTA3P/N REFCLK0P/N CLOCKS CLKOUTAP/N REFCLK1P/N REFCLK_SEL LOSA PRTAD[4:0] LS_OK_IN_A MDC LS_OK_OUT_A MDIO MDIO PDTRXA_N RESET_N CONTROL, STATUS, TEST ST MODE_SEL JTAG TESTEN TDO TMS PRBSEN TRST_N PRBS_PASS TCK GPI0 TDI Figure 7-1. TLK10031 Interfaces 18 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 CHA_LN0_IP CHA_LN0_IN LS SERDES CHA_LN1_IP CHA_LN1_IN LS SERDES HS SERDES CHA_LN2_IP CHA_LN2_IN LS SERDES CHA_LN3_IP LS SERDES CHA_OP CHA_ON CHA_LN3_IN CHA_LN0_OP CHA_LN0_ON LS SERDES CHA_LN1_OP CHA_LN1_ON LS SERDES CHA_LN2_OP CHA_LN2_ON LS SERDES CHA_LN3_OP CHA_LN3_ON LS SERDES HS SERDES CHA_IP CHA_IN Figure 7-2. A Simplified Block Diagram of the TLK10031 Data Paths Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 19 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.3 7.3.1 www.ti.com Feature Description 10GBASE-KR Transmit Data Path Overview In 10GBASE-KR Mode, the TLK10031 takes in XAUI data on the four low speed input lanes. The serial data in each lane is deserialized into 10-bit parallel data, then byte aligned (channel synchronized) based on comma detection. The four XAUI lanes are then aligned with one another, and the aligned data is input to four 8B/10B decoders. The decoded data is then input to the transmit clock tolerance compensation (CTC) block which compensates for any frequency offsets between the incoming XAUI data and the local reference clock. The CTC block then delivers the data to a 64B/66B encoder and a scrambler. The resulting scrambled 10GBASE-KR data is then input to a transmit gearbox which in turn delivers it to the high speed side SERDES for serialization and output through the HSTXAP/N*P/N pins. 7.3.2 10GBASE-KR Receive Data Path Overview In the receive direction, the TLK10031 takes in 64B/66B-encoded serial 10GBASE-KR data on the HSTXAP/N*P/N pins. This data is deserialized by a high speed SERDES, then input to a receive gearbox. After the gearbox, the data is aligned to 66-bit frames, descrambled, 64B/66B decoded, and then input to the receive CTC block. After CTC, the data is encoded by four 8B/10B encoders, and the resulting four 10-bit parallel words are serialized by the low speed SERDES blocks. The four serial XAUI output lanes are transmitted out the OUTAP/N*P/N pins. 7.3.3 Channel Synchronization Block When parallel data is clocked into a parallel-to-serial converter, the byte boundary that was associated with the parallel data is lost in the serialization of the data. When the serial data is received and converted to parallel format again, a method is needed to be able to recognize the byte boundary again. Generally, this is accomplished through the use of a synchronization pattern. This is a unique pattern of 1’s and 0’s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B encoding contains a character called the comma (b’0011111’ or b’1100000’) which is used by the comma detect circuit to align the received serial data back to its original byte boundary. The TLK10031 channel synchronization block detects the comma pattern found in the K28.5 character, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding. It is important to note that the comma can be either a (b’0011111’) or the inverse (b’1100000’) depending on the running disparity. The TLK10031 decoder will detect both patterns. The TLK10031 performs channel synchronization per lane as shown in the flowchart of Figure 7-3. 20 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Reset | LOS(Loss of Signal) Loss Of Sync (Enable Alignment) Sync Status Not Ok No Comma Comma Comma Detect 1 (Disable Alignment) !Comma & !Invalid Decode Invalid Decode Comma Comma Detect 2 !Comma & !Invalid Decode Invalid Decode Comma Comma Detect 3 !Comma & !Invalid Decode Invalid Decode Note: If HS_CH_SYNC_HYSTERESIS[1:0] is equal to 2'b00), machine operates as drawn. If HS_CH_SYNC_HYSTERESIS[1:0] is equal to 2'b01/2'b10/2'b11, then a transition from all Sync Acquired states occurs immediately upon detection of 1, 2, or 3 adjacent invalid code words or disparity errors respectively. Comma A Sync Acquired 1 (Sync Status Ok) B Invalid Decode Sync Acquired 2 (good cgs = 0) C Invalid Decode Invalid Decode Sync Acquired 3 (good cgs = 0) Invalid Decode Invalid Decode Sync Acquired 3A good cgs++ !invalid Decode & good_cgs=3 B Sync Acquired 4A good cgs++ !Invalid Decode Invalid Decode !invalid Decode & good_cgs=3 A !Invalid Decode Invalid Decode Sync Acquired 4 (good cgs = 0) Sync Acquired 2A good cgs++ !Invalid Decode C !invalid Decode & good_cgs=3 !Invalid Decode & good_cgs !=3 !Invalid Decode & good_cgs !=3 !Invalid Decode & good_cgs !=3 Figure 7-3. Channel Synchronization Flowchart Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 21 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.3.4 www.ti.com 8B/10B Encoder Embedded-clock serial interfaces require a method of encoding to ensure sufficient transition density for the receiving CDR to acquire and maintain lock. The encoding scheme also maintains the signal DC balance by keeping the number of ones and zeros balanced which allows for AC coupled data transmission. The TLK10031 uses the 8B/10B encoding algorithm that is used by the 10 Gbps and 1 Gbps Ethernet and Fibre Channel standards. This provides good transition density for clock recovery and improves error checking. The 8B/10B encoder converts each 8-bit wide data to a 10-bit wide encoded data character to improve its transition density. This transmission code includes /D/ characters, used for transmitting data, and /K/ characters, used for transmitting protocol information. Each /K/ or /D/ character code word can also have both a positive and a negative disparity version. The disparity of a code word is selected by the encoder to balance the running disparity of the serialized data stream. 7.3.5 8B/10B Decoder Once the Channel Synchronization block has identified the byte boundaries from the received serial data stream, the 8B/10B decoder converts 10-bit 8B/10B-encoded characters into their respective 8-bit formats. When a code word error or running disparity error is detected in the decoded data, the error is reported in the status register (1E.000F) and the LOS pin is asserted (depending on the LOS overlay selection). 7.3.6 64B/66B Encoder/Scrambler To facilitate the transmission of data received from the media access control (MAC) layer, the TLK10031 encodes data received from the MAC using the 64B/66B encoding algorithm defined in the IEEE802.32008 standard. The TLK10031 takes two consecutive transfers from the XAUI interface and encodes them into a 66-bit code word. The information from the two XAUI transfers includes 64 bits of data and 8 bits of control information after 8B/10B decoding. If the 64B/66B encoder detects an invalid packet format from the XAUI interface, it replaces erroneous information with appropriately-encoded error information. The resulting 66-bit code word is then sent on to the transmit gearbox. The encoding process implemented in the TLK10031 includes two steps: 1. an encoding step, which converts the 72 bits of data (8 data bytes plus 8 control-code indicators) received from the transmit CTC FIFO into a 66-bit code word 2. a scrambling step, which scrambles 64 bits of encoded data using the scrambler polynomial x58+x39+1. The 66 bits created by the encoder consists of 64 bits of data and a 2-bit synchronization field consisting of either 01 or 10. Only the 64 bits of data are scrambled, leaving the two synchronization bits unmodified. The two synchronization bits allow the receive gearbox to obtain frame alignment and, in addition, ensure an edge transition of at least once in 66 bits of data. The encoding process allows a limited amount of control information to be sent in-line with the data. 7.3.7 Forward Error Correction Optionally enabled, Forward Error Correction (FEC) follows the IEEE 802.3-2008 standard, and is able to correct a burst errors up to 11 bits. In the TX data path, the FEC logic resides between the scrambler and gearbox. In the RX datapath, FEC resides between the gearbox and descrambler. Frame alignment is handled inside the RX FEC block during FEC operation, and the RX gearbox sync header alignment is bypassed. Because latency is increased in both the TX and RX data paths with FEC enabled, it is disabled by default and must be enabled through MDIO programming. Note that FEC by nature will add latency due to frame storage. 22 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.3.8 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 64B/66B Decoder/Descrambler The data received from the serial 10GBASE-KR is 64B/66B-encoded data. The TLK10031 decodes the data received using the 64B/66B decoding algorithm defined in the IEEE 802.3-2008 standard. The TLK10031 creates consecutive 72-bit data words from the encoded 66-bit code words for transfer over the XAUI interface to the MAC. The information for the two XAUI transfers includes 64 bits of data and 8 bits of control information before 8B/10B encoding. Not all 64B/66B block payloads are valid. Invalid block payloads are handled by the 64B/66B decoder block and appropriate error handling is provided, as defined in the IEEE 802.3-2008 standard. The decoding algorithm includes two steps: a descrambling step which descrambles 64 bits of the 66-bit code word with the scrambling polynomial x58+x39+1, and a decoding step which converts the 66 bits of data received into 64 bits of data and 8 bits of control information. These words are sent to the receive CTC FIFO. 7.3.9 Transmit Gearbox The function of the transmit gearbox is to convert the 66-bit encoded, scrambled data stream into a 16-bitwide data stream to be sent out to the serializer and ultimately to the physical medium attachment (PMA) device. The gearbox is needed because while the effective bit rate of the 66-bit data stream is equal to the effective bit rate of the 16-bit data, the clock rates of the two buses are of different frequencies. 7.3.10 Receive Gearbox While the transmit gearbox only performs the task of converting 66-bit data to be transported on to the 16bit serializer, the receive gearbox has more to do than just the reverse of this function. The receive gearbox must also determine where within the incoming data stream the boundaries of the 66-bit code words are. The receive gearbox has the responsibility of initially synchronizing the header field of the code words and continuously monitoring the ongoing synchronization. After obtaining synchronization to the incoming data stream, the gearbox assembles 66-bit code words and presents these to the 64B/66B decoder. Note that in FEC mode, the Receive Gearbox blindly converts 16-bit data to 66-bit data and depends on the RX FEC logic to frame align the data. 7.3.11 XAUI Lane Alignment / Code Gen (XAUI PCS) The XAUI interface standard is defined to allow for 21 UI of skew between lanes. This block is implemented to handle up to 30 UI (XAUI UI) of skew between lanes using /A/ characters. The state machine follows the standard 802.3-2008 defined state machine. 7.3.12 Inter-Packet Gap (IPG) Characters The XAUI interface transports information that consists of packets and inter-packet gap (IPG) characters. The IEEE 802.3-2008 standard defines that the IPG, when transferred over the XAUI interface, consists of alignment characters (/A/), control characters (/K/) and replacement characters (/R/). TLK10031 converts all AKR characters to IDLE characters, performs insertions or deletions on the IDLE characters, and transmits only encoded IDLE characters out to the 10GBASE-KR interface. The receive channel expects encoded IDLE characters to enter the 10GBASE-KR interface, and performs insertions and deletions on IDLE characters and then converts IDLE characters back to AKR characters. Any AKR characters received on the high speed interface are by default converted to IDLE characters for reconversion to AKR columns. Both the transmit and receive FIFOs rely upon a valid IDLE stream to perform clock tolerance compensation (CTC). Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 23 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.3.13 Clock Tolerance Compensation (CTC) The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the reference clocks for two devices on a XAUI link have the same specified frequencies, there can be slight differences that, if not compensated for, will lead to over or under run of the FIFO’s on the receive/transmit data path. The TLK10031 provides compensation for these differences in clock frequencies via the insertion or the removal of idle (/I/) characters on all lanes, as shown in Figure 7-4 and Figure 7-5. Packet IPG LANE 0 K R S D D D D ... D D D D I I I K S D LANE 1 K R D D D D D ... D D D T I I I K D D LANE 2 K R D D D D D ... D D D I I I I K D D LANE 3 K R D D D D D ... D D D I I I I K D D LANE 0 I I S D D D D ... D D D D I I I I I S LANE 1 I I D D D D D ... D D D T I I I I I D LANE 2 I I D D D D D ... D D D I I I I I I D LANE 3 I I D D D D D ... D D D I I I I I I D Input Output S = Start of Packet, D = Data, T = End of Packet, I = Idle Added Column Figure 7-4. Clock Tolerance Compensation: Add Packet IPG LANE 0 K R S D D D D ... D D D D I I I K S D LANE 1 K R D D D D D ... D D D T I I I K D D LANE 2 K R D D D D D ... D D D I I I I K D D LANE 3 K R D D D D D ... D D D I I I I K D D Input Dropped Column LANE 0 I I S D D D D ... D D D D I I I LANE 1 I I D D D D D ... D D D T I I I D D D LANE 2 I I D D D D D ... D D D I I I I D D D LANE 3 I I D D D D D ... D D D I I I I D D D S D D Output S = Start of Packet, D = Data, T = End of Packet, I = Idle Figure 7-5. Clock Tolerance Compensation: Drop The TLK10031 allows for provisioning of both the CTC FIFO depth and the low/high watermark thresholds that trigger idle insertion/deletion beyond the standard requirements. This allows for optimization between maximum clock tolerance and packet length. For more information on the TLK10031 CTC provisioning, see Section 7.4.20. 24 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.3.14 10GBASE-KR Auto-Negotiation When TLK10031 is selected to operate in 10GKR/1G-KX mode (MODE_SEL pin held low), Clause 73 Auto-Negotiation will commence after power up or hardware or software reset. The data path chosen from the result of Auto-Negotiation will be the highest speed of 10G-KR or 1G-KX as advertised in the MDIO ability fields (set to 10G-KR by default). If 10G-KR is chosen, link training will commence immediately following the completion of Auto-Negotiation. Legacy devices that operate in 1G-KX mode and do not support Clause 73 Auto Negotiation will be recognized through the Clause 73 parallel detection mechanism. 7.3.15 10GBASE-KR Link Training Link training for 10G-KR mode is performed after auto-negotiation, and follows the procedure described in IEEE 802.3-2008. The high speed TX SERDES side will update pre-emphasis tap coefficients as requested through the Coefficient update field. Received training patterns are monitored for bit errors (MDIO configurable), and requests are made to update partner channel TX coefficients until optimal settings are achieved. The RX link training algorithm consists of sending a series of requests to move the link partner’s transmitter tap coefficients to the center point of an error free region. Once link training has completed, the 10G-KR data path is enabled. If link is lost, the entire process repeats with auto-negotiation, link training, and 10G-KR mode. TLK10031 also offers a manual mode whereby coefficient update requests are handled through external software management. 7.3.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection The TLK10031 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers are available for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies for various applications. The external differential reference clock has a large operating frequency range allowing support for many different applications. A low-jitter reference clock should be used, and its frequency accuracy should be within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate). When the TLK10031 device is set to operate in the 10GBASE-KR mode with a low speed side line rate of 3.125 Gbps and a high speed side line rate of 10.3125 Gbps, the reference clock choices are as shown in Table 7-1. In general, using a higher reference clock frequency results in improved jitter performance. Table 7-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode: LOW SPEED SIDE HIGH SPEED SIDE Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) 3125 10 Full 156.25 10312.5 16.5 Full 156.25 3125 5 Full 312.5 10312.5 8.25 Full 312.5 7.3.17 10GBASE-KR Test Pattern Support The TLK10031 has the capability to generate and verify various test patterns for self-test and system diagnostic measurements. The following test patterns are supported: • High Speed (HS) Side: PRBS 27 – 1, PRBS 223 – 1, PRBS 231 – 1, Square Wave with Provisionable Length, and KR Pseudo-Random Pattern • Low Speed (LS) Side: PRBS 27 – 1, PRBS 223 – 1, PRBS 231 – 1, High Frequency, Low Frequency, Mixed Frequency, CRPAT, CJPAT. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 25 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com The TLK10031 provides two pins: PRBSEN and PRBS_PASS, for additional control and monitoring of PRBS pattern generation and verification. When PRBSEN is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides. PRBS 27-1 is selected by default, and can be changed through MDIO. When PRBS test is enabled (PRBSEN=1): • PRBS_PASS = 1 indicates that PRBS pattern reception is error free. • PRBS_PASS = 0 indicates that a PRBS error is detected. The side (high speed or low speed), and the lane (for low speed side) that this signal refers to is chosen through MDIO. 7.3.18 10GBASE-KR Latency The latency through the TLK10031 in 10GBASE-KR mode is as shown in Figure 7-6. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. Figure 7-6. 10GBASE-KR Mode Latency Per Block 7.4 Device Functional Modes The TLK10031 is a versatile high-speed transceiver device that is designed to perform various physical layer functions in three operating modes: 10GBASE-KR Mode, 1G-KX Mode, and General Purpose (10G) SERDES Mode. The three modes are described in three separate sections. The device operating mode is determined by the MODE_SEL and ST pin settings, as well as MDIO register 1E.0001 bit 10. 26 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.4.1 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 10GBASE-KR Mode Training HSTXAP HSTXAN Auto-Neg Gearbox Serializer TX FEC Scrambler 64b/66b Encoder TX CTC Data Switch 8b/10b Decoder Deserializer Training Arbitration RX FEC Gearbox HSRXAP HSRXAN Auto-Neg 8b/10b Decoder 8b/10b Decoder Descrambler OUTA3P OUTA3N 8b/10b Decoder XAUI Lane Alignment 8b/10b Encoder Serializer OUTA2N 64b/66b Decoder OUTA2P Data Switch Serializer OUTA1N RX CTC OUTA1P 8b/10b Encoder Serializer OUTA0N 8b/10b Encoder OUTA0P 8b/10b Encoder Channel Sync Channel Sync Channel Sync Channel Sync INA3P INA3N XAUI Code Gen INA2N Serializer INA2P Deserializer INA1N Deserializer INA1P Deserializer INA0P INA0N Deserializer A simplified block diagram of the transmit and receive data paths in 10GBASE-KR mode is shown in Figure 7-7. This section gives a high-level overview of how data moves through these paths, then gives a more detailed description of each block’s functionality. Figure 7-7. A Simplified KR Data Path Block Diagram Table 7-2. TLK10031 Operating Mode Selection ST = 0 (Clause 45) ST = 1 (Clause 22) 10G {MODE_SEL pin, Register 1E.0001 bit 10} 1x 10G 01 10G 10G 00 10G-KR/1G-KX (Determined by Auto Neg) 1G-KX (No Auto Neg) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 27 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.4.2 www.ti.com 1GBASE-KX Mode Serializer Test Pattern Generation 8b/10b Encoder TX CTC Data Switch 8b/10b Decoder INA0N Deserializer INA0P 1G-KX Sync A simplified block diagram of the 1GBASE-KX data path is shown in Figure 7-8. HSTXAP HSTXAN Test Pattern Verification Deserializer 1G-KX Sync 8b/10b Decoder Data Switch RX CTC Serializer OUTA0P OUTA0N 8b/10b Encoder Test Pattern Verification HSRXAP HSRXAN Test Pattern Generation Figure 7-8. A Simplified Block Diagram of the 1GKX Data Path 7.4.2.1 Channel Sync Block This block is used to align the deserialized signals to the proper 10-bit word boundaries. The Channel Sync block generates a synchronization flag indicating incoming data is synchronized to the correct word boundary. This module implements the synchronization state machine found in Figure 36-9 of the IEEE 802.3-2008 Standard. A synchronization status signal, latched low, is available to indicate synchronization errors. 7.4.2.2 8b/10b Encoder and Decoder Blocks As in the 10GBASE-KR operating mode, these blocks are used to convert between 10-bit (encoded) data and 8-bit data words. They can be optionally bypassed. A code invalid signal, latched low, is available to indicate 8b/10b encode and decode errors. 7.4.2.3 TX CTC The transmit clock tolerance compensation (CTC) block acts as a FIFO with add and delete capabilities, adding and deleting 2 cycles each time to support ±200ppm during IFG (no errors) between the read and write clocks. This block implements a 12 deep asynchronous FIFO with a usable space 8 deep. It has two separate pointer tracking systems. One determines when to delete or insert and another determines when to reset. Inserts and deletes are only allowed during non-errored inter-frame gaps and occurs 2 cycles at a time. It has an auto reset feature once collision occurs. If a collision occurs, the indication is latched high until read by MDIO. 7.4.2.4 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection When the TLK10031 is configured to operate in the 1GBASE-KX mode, the available line rates, reference clock frequencies, and corresponding PLL multipliers are summarized in Table 7-3. 28 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Table 7-3. Specific Line Rate and Reference Clock Selection for the 1GBASE-KX Mode LOW SPEED SIDE SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps (1) ) SERDES PLL Multiplier Rate REFCLKP/N (MHz) 3125 (2) 10 Full 156.25 3125 (2) 10 Full 156.25 3125 (1) (2) HIGH SPEED SIDE Line Rate (Mbps) (2) 3125 (2) 5 Full 312.5 5 Full 312.5 1250 10 Half 125 (2) 1250 20 Quarter 125 (2) 1250 8 Half 156.25 1250 16 Quarter 156.25 1250 8 Quarter 312.5 1250 8 Quarter 312.5 High Speed Side SERDES runs at 2x effective data rate. Manual mode only, as auto negotiation does not support 125Mhz REFCLK or line rate of 3125Mbps. To disable automatic setting of PLL and rate modes, write 1'b1 to bit 13 of register 0x1E.001D. 7.4.2.5 1GBASE-KX Mode Latency The latency through the TLK10031 in 1G-KX mode is as shown in Figure 7-9. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. Figure 7-9. 1G-KX Mode Latency Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 29 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.4.2.5.1 Test Pattern Generator In 1G-KX mode, this block can be used to generate test patterns allowing the 1G-KX channel to be tested for compliance while in a system environment or for diagnostic purposes. Test patterns generated are high/low/mixed frequency and CRPAT long or short. 7.4.2.5.2 Test Pattern Verifier The 1G-KX test pattern verifier performs the verification and error reporting for the CRPAT Long and Short test patterns specified in Annex 36A of the IEEE 802.3-2008 standard. Errors are reported to MDIO registers. 7.4.3 General Purpose (10G) Serdes Mode Functional Description Serializer 20-bit 8b/10b Encoder TPGEN TX FIFO 1 lane TX FIFO 2 or 4-lane Comma Lane Alignment 8b/10b decoder 8b/10b decoder Deserializer 20-bit ch_sync 20-bit 8b/10b Decoder RX FIFO (1 lane) 8b/10b encoder 8b/10b encoder 8b/10b decoder 8b/10b decoder ch_sync ch_sync ch_sync ch_sync HSTXAP HSTXAN HSRXAP HSRXAN TPVER OUTA3P OUTA3N RX FIFO (2 or 4-lane) OUTA2N Lane Alignment Gen OUTA2P 8b/10b encoder OUTA1P OUTA1N 8b/10b encoder OUTA0P OUTA0N serializer INA3P INA3N serializer INA2P INA2N serializer INA1N serializer INA1P deserializer deserializer INA0N deserializer INA0P deserializer A block diagram showing the transmit and receive data paths of the TLK10031 operating in General Purpose (10G) SerDes mode is shown in Figure 7-10. Figure 7-10. Block Diagram Showing General Purpose SerDes Mode 7.4.3.1 General Purpose SERDES Transmit Data Path The TLK10031 General Purpose SERDES low speed to high speed (transmit) data path with the device configured to operate in the normal transceiver (mission) mode is shown in the upper half of Figure 7-10. In this mode, 8B/10B encoded serial data (INA*P/N) in 2 or 4 lanes is received by the low speed side SERDES and deserialized into 10-bit parallel data for each lane. The data in each individual lane is then byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data for each lane. The lane data is then lane aligned by the Lane Alignment Slave. 32 bits of lane aligned parallel data is input to a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The resulting 20-bit 8B/10B encoded parallel data is sent to the high speed side SERDES for serialization and output through the HSTXAP*P/N pins. 30 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.4.4 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 General Purpose SERDES Receive Data Path With the device configured to operate in the normal transceiver (mission) mode, the high speed to low speed (receive) data path is shown in the lower half of Figure 7-10. 8B/10B encoded serial data (HSRXAP*P/N) is received by the high speed side SERDES and deserialized into 20-bit parallel data. The data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO. The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B encoded and the resulting 10-bit parallel data for each lane is input to the low speed side SERDES for serialization and output through the OUTAP*P/N pins. 7.4.5 Channel Synchronization As in the 10GBASE-KR mode, the channel synchronization block is used in the 10G General Purpose SERDES mode to align received serial data to a defined byte boundary. The channel synchronization block detects the comma pattern found in the K28.5 character, and follows the synchronization flowchart shown in Figure 7-3. 7.4.6 8B/10B Encoder and Decoder As in the 10GBASE-KR and 1GBASE-KX modes, the 8B/10B encoder and decoder blocks are used to convert between 10-bit (encoded) and 8-bit (unencoded) data words. 7.4.7 Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode Lower rate multi-lane serial signals must be byte aligned and lane aligned such that high speed multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10031 implements a special lane alignment scheme on the low speed (LS) side for 8b/10b data that does not contain XAUI alignment characters. During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate data ordering is restored. Lane alignment completes successfully when the LS receiver asserts a “Link Status OK” signal monitored by the LS transmitter on the link partner device such as an FPGA. The TLK10031 sends out the “Link Status OK” signals through the LS_OK_OUT_A output pins, and monitors the “Link Status OK” signals from the link partner device through the LS_OK_IN_A input pins. If the link partner device does not need the TLK10031 Lane Alignment Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A can be tied high on the application board or set through MDIO register bits. The lane alignment scheme is activated under any of the following conditions: • Device/System power up (after configuration/provisioning) • Loss of channel synchronization assertion on any enabled LS lane • Loss of signal assertion on any enabled LS lane • LS SERDES PLL Lock indication deassertion • After device configuration change • After software determined LS 8B/10B decoder error rate threshold exceeded • After device reset is deasserted • Any time the LS receiver deasserts “Link Status OK”. • Presence of reoccurring higher level / protocol framing errors All the above conditions are selectable through MDIO register provisioning. The block diagram of the lane alignment scheme is shown in Figure 7-11. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 31 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Link Partner Device TLK10031 LS _OK_ OUT _A LAM Lane Alignment Master 8B à 10B CH SYNC 10Bà8B 8B à 10B CH SYNC 10Bà8B CH SYNC 10Bà8B CH SYNC 10Bà8B INA[3:0]P/N 8B à 10B 8B à 10B Lane Align LAS Lane Alignment Slave Low Speed Side SERDES (4 RX/ 4 TX) Low Speed Side SERDES (4 RX/ 4 TX) 8B ß 10B CH SYNC 8B ß 10B CH SYNC 8B ß 10B CH SYNC 10B ß 8B 8B ß 10B CH SYNC 10B ß 8B LAS Lane Alignment Slave OUTA[3:0]P/N Lane Align 10B ß 8B 10B ß 8B LAM Lane Alignment Master LS _OK _IN_A Figure 7-11. Block Diagram of the Lane Alignment Scheme 7.4.8 Lane Alignment Components • • Lane Alignment Master (LAM) – Responsible for generating proprietary LS lane alignment initialization pattern – Resides in the TLK10031 receive path • Responsible for bringing up LS receive link for the data sent from the TLK10031 to a link partner device • Monitors the LS_OK_IN_A pins for “Link Status OK” signals sent from the Lane Alignment Slave (LAS) of the link partner device – Resides in the link partner device • Responsible for bringing up LS transmit link for the data sent from the link partner device to the TLK10031 • Monitors the “Link Status OK” signals sent from the LS_OK_OUT_A pins of the Lane Alignment Slave (LAS) of the TLK10031 Lane Alignment Slave (LAS) – Responsible for monitoring the LS lane alignment initialization pattern – Performs channel synchronization per lane (2 or 4 lanes) through byte rotation – Performs lane alignment and realignment of bytes across lanes – Resides in the TLK10031 transmit path • Generates the “Link Status OK” signal for the LAM on the link partner device – Resides in the link partner device • Generates the “Link Status OK” signal for the LAM on the TLK10031 device. Reference code from Texas Instruments is available for the LAM and LAS modules for easy integration into FPGAs. 32 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.4.9 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Lane Alignment Operation During lane alignment, the LAM sends a repeating pattern of 49 characters (control + data) simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders in parallel. The proprietary lane alignment pattern consists of the following characters: /K28.5/ (CTL=1, Data=0xBC) Repeat the following sequence of 12 characters four times: /D30.5/ (CTL=0, Data=0xBE) /D23.6/ (CTL=0, Data=0xD7) /D3.1/ (CTL=0, Data=0x23) /D7.2/ (CTL=0, Data=0x47) /D11.3/ (CTL=0, Data=0x6B) /D15.4/ (CTL=0, Data=0x8F) /D19.5/ (CTL=0, Data=0xB3) /D20.0/ (CTL=0, Data=0x14) /D30.2/ (CTL=0, Data=0x5E) /D27.7/ (CTL=0, Data=0xFB) /D21.1/ (CTL=0, Data=0x35) /D25.2/ (CTL=0, Data=0x59) The above 49-character sequence is repeated until LS_OK_IN_A is asserted. Once LS_OK_IN_A is asserted, the LAM resumes transmitting traffic received from the high speed side SERDES immediately. The TLK10031 performs lane alignment across the lanes similar in fashion to the IEEE 802.3-2008 (XAUI) specification. XAUI only operates across 4 lanes while LAS operates with 2 or 4 lanes. The lane alignment state machine is shown in Figure 7-12. The TLK10031 uses the comma (K28.5) character for lane to lane alignment by default, but can be provisioned to use XAUI's /A/ character as well. Lane alignment checking is not performed by the LAS after lane alignment is achieved. After LAM detects that the LS_OK_IN_A signal is asserted, normal system traffic is carried instead of the proprietary lane alignment pattern. Channel synchronization is performed during lane alignment and normal system operation. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 33 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Hard or Soft Reset Loss of Lane Alignment (enable deskew) Deassert LS_OK /C/ & CH_SYNC? no Align Detect 3 yes any deskew_err !deskew_err & /C/ no Align Detect 1 (disable deskew) yes any deskew_err !deskew_err & /C/ Lane Aligned (Assert LS_OK) no yes yes Align Detect 2 any deskew_err !deskew_err & /C/ no Any Lane Realign Conditions? no /C/ = Character matched In All Enabled Lanes deskew_err = Character matched in any lane, but not in all lanes at same time yes CH_SYNC = Channel Sync Asserted All Lanes Figure 7-12. Lane Alignment State Machine 34 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.4.10 Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode When the TLK10031 is set to operate in the General Purpose SERDES mode, the following tables show a summary of line rates and reference clock frequencies used for CPRI/OBSAI for 1:1, 2:1 and 4:1 operation modes. Table 7-4. Specific Line Rate Selection for the 1:1 General Purpose Operation Mode LOW SPEED SIDE Line Rate (Mbps) HIGH SPEED SIDE SERDES PLL Multiplier Rate REFCLKP/N (MHz) 122.88 SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) 4915.2 20 Full 122.88 4915.2 20 Half 3840 12.5 Full 153.6 3840 12.5 Half 153.6 3125 10 Full 156.25 3125 10 Half 156.25 3125 5 Full 312.5 3125 5 Half 312.5 3072 10 Full 153.6 3072 10 Half 153.6 2457.6 8/10 Full 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88 1920 12.5 Half 153.6 1920 12.5 Quarter 153.6 1536 10 Half 153.6 1536 10 Quarter 153.6 1228.8 8/10 Half 153.6/122.88 1228.8 16/20 Eighth 153.6/122.88 Table 7-5. Specific Line Rate and Reference Clock Selection for the 2:1 General Purpose Operation Mode LOW SPEED SIDE Line Rate (Mbps) HIGH SPEED SIDE SERDES PLL Multiplier Rate REFCLKP/N (MHz) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) 4915.2 20 Full 122.88 9830.4 20 Full 122.88 3840 12.5 Full 153.6 7680 12.5 Full 153.6 3072 10 Full 153.6 6144 10 Full 153.6 2457.6 8/10 Full 153.6/122.88 4915.2 16/20 Half 153.6/122.88 1920 12.5 Half 153.6 3840 12.5 Half 153.6 1536 10 Half 153.6 3072 10 Half 153.6 1228.8 8/10 Half 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88 768 10 Quarter 153.6 1536 10 Quarter 153.6 614.4 8/10 Quarter 153.6/122.88 1228.8 16/20 Eighth 153.6/122.88 Table 7-6. Specific Line Rate and Reference Clock Selection for the 4:1 General Purpose Operation Mode LOW SPEED SIDE HIGH SPEED SIDE Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) 2457.6 8/10 Full 153.6/122.88 9830.4 16/20 Full 153.6/122.88 1536 10 Half 153.6 6144 10 Full 153.6 1228.8 8/10 Half 153.6/122.88 4915.2 16/20 Half 153.6/122.88 768 10 Quarter 153.6 3072 10 Half 153.6 614.4 8/10 Quarter 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 35 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Table 7-4, Table 7-5, and Table 7-6 indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6MHz and 122.88MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has been given for each reference clock frequency respectively. The low speed side and the high speed side SERDES use the same reference clock frequency. For other line rates not shown in Table 7-4, Table 7-5, or Table 7-6, valid reference clock frequencies can be selected with the help of the information provided in Table 7-7 and Table 7-8 for the low speed and high speed side SERDES. The reference clock frequency has to be the same for the two SERDES and must be within the specified valid ranges for different PLL multipliers. Table 7-7. Line Rate and Reference Clock Frequency Ranges for the Low Speed Side SERDES (General Purpose Mode) SERDES PLL Multiplier (MPY) Reference Clock (MHz) Full Rate (Gbps) Half Rate (Gbps) Quarter Rate (Gbps) Min Max Min Max Min Max Min 4 250 425 2 3.4 1 1.7 0.5 Max 0.85 5 200 425 2 4.25 1 2.125 0.5 1.0625 6 166.667 416.667 2 5 1 2.5 0.5 1.25 8 125 312.5 2 5 1 2.5 0.5 1.25 10 122.88 250 2.4576 5 1.2288 2.5 0.6144 1.25 12 122.88 208.333 2.94912 5 1.47456 2.5 0.73728 1.25 12.5 122.88 200 3.072 5 1.536 2.5 0.768 1.25 15 122.88 166.667 3.6864 5 1.8432 2.5 0.9216 1.25 20 122.88 125 4.9152 5 2.4576 2.5 1.2288 1.25 RateScale: Full Rate = 0.5, Half Rate = 1, Quarter Rate = 2 Table 7-8. Line Rate and Reference Clock Frequency Ranges for the High Speed Side SERDES (General Purpose Mode) Full Rate (Gbps) Half Rate (Gbps) Min Max Min Max Min Max Min Max 4 375 425 6 6.8 3 3.4 1.5 1.7 5 300 425 6 8.5 3 4.25 1.5 6 250 416.667 6 10 3 5 1.5 8 187.5 312.5 6 10 3 5 10 150 250 6 10 3 12 125 208.333 6 10 12.5 153.6 200 7.68 15 122.88 166.667 16 122.88 20 122.88 SERDES PLL Multiplier (MPY) Reference Clock (MHz) Quarter Rate (Gbps) Eighth Rate (Gbps) Min Max 2.125 1.0 1.0625 2.5 1.0 1.25 1.5 2.5 1.0 1.25 5 1.5 2.5 1.0 1.25 3 5 1.5 2.5 1.0 1.25 10 3.84 5 1.92 2.5 1.0 1.25 7.3728 10 3.6864 5 1.8432 2.5 1.0 1.25 156.25 7.86432 10 3.932 5 1.966 2.5 1.0 1.25 125 9.8304 10 4.9152 5 2.4576 2.5 1.2288 1.25 RateScale: Full Rate = 0.25, Half Rate = 0.5, Quarter Rate = 1, Eighth Rate = 2 For example, in the 2:1 operation mode, if the low speed side line rate is 1.987Gbps, the high-speed side line rate will be 3.974Gbps. The following steps can be taken to make a reference clock frequency selection: 1. Determine the appropriate SERDES rate modes that support the required line rates. Table 7-7 shows that the 1.987Gbps line rate on the low speed side is only supported in the half rate mode (RateScale = 1). Table 7-8 shows that the 3.974Gbps line rate on the high speed side is only supported in the half rate mode (RateScale = 1). 2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding reference clock frequencies using the formula: Reference Clock Frequency = (LineRate x RateScale)/MPY The computed reference clock frequencies are shown in Table 7-9 along with the valid minimum and maximum frequency values. 36 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall outside the allowed range. In this example, the common frequencies are highlighted in Table 7-9. The highest and lowest computed reference clock frequencies must be discarded because they exceed the recommended range. 4. Select any of the remaining marked common reference clock frequencies. Higher reference clock frequencies are generally preferred. In this example, any of the following reference clock frequencies can be selected: 397.4MHz, 331.167MHz, 248.375MHz, 198.7MHz, 165.583MHz, 158.96MHz, and 132.467MHz Table 7-9. Reference Clock Frequency Selection Example LOW SPEED SIDE SERDES HIGH SPEED SIDE SERDES REFERENCE CLOCK FREQUENCY (MHz) REFERENCE CLOCK FREQUENCY (MHz) SERDES PLL MULTIPLIER COMPUTED MIN MAX SERDES PLL MULTIPLIER COMPUTED MIN MAX 4 496.750 250 425 4 496.750 375 425 5 397.400 200 425 5 397.400 300 425 6 331.167 166.667 416.667 6 331.167 250 416.667 8 248.375 125 312.5 8 248.375 187.5 312.5 10 198.700 122.88 250 10 198.700 150 250 208.333 12 165.583 122.88 208.333 12 165.583 125 12.5 158.960 122.88 200 12.5 158.960 153.6 200 15 132.467 122.88 166.667 15 132.467 122.88 166.667 20 99.350 122.88 125 20 99.350 122.88 125 7.4.11 General Purpose SERDES Mode Test Pattern Support The TLK10031 has the capability to generate and verify various test patterns for self-test and system diagnostic measurements. Most of the same test pattern support is available for 10G General Purpose Mode as for 10G-KR. (See Register 1E.000B for details). 7.4.12 General Purpose SERDES Mode Latency The latency through the TLK10031 in General Purpose SERDES mode is as shown in Figure 7-13. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 37 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Figure 7-13. General Purpose SERDES Mode Latency 7.4.12.1 Clocking Architecture (All Modes) A simplified clocking architecture for the TLK10031 is captured in Figure 7-14. The device has an option of operating with a differential reference clock provided either on pins REFCLK0P/N or REFCLK1P/N. The choice is made either through MDIO or through REFCLK_SEL pins. The low speed side SERDES, high speed side SERDES and the associated part of the digital core can operate from the same or different reference clock. 38 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 MDIO REG REFCLK0P/N H igh Speed SERDES Clock Multiplier LS MDIO REG Clock Multiplier SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Low Speed SERDES www.ti.com HS REFCLK1P/N Figure 7-14. Reference Clock Architecture The TLK10031 has one output port - CLKOUTAP/N. This output port can be configured to output the byte clock from either the low speed or high speed serdes. The output clock can also be chosen to be synchronous with the transmit clock rate. Various divider values can be chosen using the MDIO interface. The maximum CLKOUT frequency is 500 MHz. 7.4.12.2 Integrated Smart Switch The TLK10031 allows for adjustable routing of data within the device. Each output port may be configured to output data corresponding to any input port. Figure 7-15 illustrates the different possible data path routings. Data Switch LS IN Low Speed Deserialization and TX Logic (Synchronization, Decoding, etc.) LS OUT Low Speed RX Logic (Encoding, etc.) and Serialization 00 01 HS Output Selection 00 LS Output Selection 01 High Speed TX Logic (Encoding, Scrambling, etc.) and Serialization HSTX High Speed Deserialization and RX Logic (Decoding, Descrambling, etc.) HSRX Figure 7-15. Signal Routings for Integrated Smart Switch 7.4.13 Intelligent Switching Modes The TLK10031 supports various switching modes that allow for the user to choose when changes in data routing take effect. There are three options: 1. Wait for the end of the current packet, insert IDLEs, then switch to the new input source at the start of its next packet. This option allows the current packet to complete so that data is not lost. 2. Drop current packet and insert a programmable character (such as Local Fault), then switch to the new input source at the start of its next packet. This can provide a more immediate switch-over at the expense of the current packet’s data. 3. Immediately switch lanes without packet monitoring. For more information on selecting different intelligent switching modes, see MDIO register bits 0x1E.0017 through 0x1E.001B. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 39 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.4.14 Serial Loopback Modes The TLK10031 supports internal loopback of the serial output signals for self-test and system diagnostic purposes. Loopback mode can be enabled independently for each SERDES via MDIO register bits. When loopback mode is enabled for a particular SERDES, the serial output data will be internally routed to the SERDES’s serial input port. The output data will remain available for monitoring on the output pins. 7.4.15 Latency Measurement Function (General Purpose SerDes Mode) The TLK10031 includes a latency measurement function to support CPRI and OBSAI type applications. There are two start and two stop locations for the latency counter as shown in Figure 7-16. The start and stop locations are selectable through MDIO register bits. The elapsed time from a comma detected at an assigned counter start location to a comma detected at an assigned counter stop location is measured and reported through the MDIO interface. The following three control characters (containing commas) are monitored: 1. K28.1 (control = 1, data = 0x3C) 2. K28.5 (control = 1, data = 0xBC) 3. K28.7 (control = 1, data = 0xFC). INA2P/N 10 10 10 LS PRBS Generator OUTA3P/N 32 10 10 TX FIFO 16 16 Pattern 16 Generator Stop Counter 20 10 10 Receive Data Path Covered Start Counter 10 10 32 16 RX FIFO HS PRBS Generator HSTXAP /N High Speed Side SERDES Transmit Data Path Covered Latency Counter Stop Counter OUTA0P/N OUTA2P/N 10 Start Counter Low Speed Side SERDES OUTA1P/N 10 8B/10 B Encode r Lane Align Ma ster INA3P/N 10 8B/10B Dec oder Channel Sync 10 8B/10B Dec oder La ne Align Slave 10 10 Comma Detec tion for Latency Measurement INA1P/N LS PRBS Verifier Channe l Sync 10 INA0P/N 8 B/10B Encoder The first comma found at the assigned counter start location will start up the latency counter. The first comma detected at the assigned counter stop location will stop the latency counter. The 20-bit latency counter result of this measurement is readable through the MDIO interface. The accuracy of the measurement is a function of the serial bit rate. The register will return a value of 0xFFFFF if the duration between transmit and receive comma detection exceeds the depth of the counter. Only one measurement value is stored internally until the 20-bit results counter is read. The counter will return zero in cases where a transmit comma was never detected (indicating the results counter never began counting). In addition, the stopwatch counter can be configured to be started or stopped manually based on the state of the PRTAD0 pin (see MDIO register map for details). 20 HS PRBS Verifier HSRXAP /N Pattern Verifier Figure 7-16. Location of TX and RX Comma Character Detection 40 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 In high speed side SERDES full rate mode, the latency measurement function runs off of an internal clock which is equal to the frequency of the transmit serial bit rate divided by 8. In half rate mode, the latency measurement function runs off of an internal clock which is equal to the serial bit rate divided by 4. In quarter rate mode, the latency measurement function runs off of an internal clock which is equal to the serial bit rate divided by 2. In eighth rate mode, the latency measurement function runs off of a clock which is equal to the serial bit rate. The latency measurement does not include the low speed side transmit SERDES contribution as well as part of the channel synchronization block. The latency introduced by those two is up to (18 + 10) x N high speed side unit intervals (UIs), where N = 2, 4 is the multiplex factor. The latency measurement also doesn’t account for the low speed side receive SERDES contribution which is estimated to be up to 20 x N high speed side UIs. The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock period. The measurement clock can be divided down if a longer duration measurement is required, in which case the accuracy of the measurement is accordingly reduced. The high speed latency measurement clock is divided by either 1, 2, 4, or 8 via register settings. The high speed latency measurement clock may only be used when operating at one of the serial rates specified in the CPRI/OBSAI specifications. It is also possible to run the latency measurement function off of the recovered byte clock (giving a latency measurement clock frequency equal to the serial bit rate divided by 20). The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 7-10, and assumes the latency measurement clock is not divided down per user selection (division is required to measure a duration greater than 682 µs). For each division of 2 in the measurement clock, the accuracy is also reduced by a factor of two. Table 7-10. CPRI/OBSAI Latency Measurement Function Accuracy (Undivided Measurement Clock) LINE RATE (Gbps) RATE LATENCY CLOCK FREQUENCY (GHz) ACCURACY (± ns) 1.2288 Eighth 1.2288 0.8138 1.536 Quarter 0.768 1.302 2.4576 Quarter 1.2288 0.8138 3.072 Half 0.768 1.302 3.84 Half 0.96 1.0417 4.9152 Half 1.2288 0.8138 6.144 Full 0.768 1.302 7.68 Full 0.96 1.0417 9.8304 Full 1.2288 0.8138 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 41 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.4.16 Power Down Mode The TLK10031 can be put in power down either through device input pins or through MDIO control register 1E.0001. • PDTRXA_N: Active low, power down 7.4.16.1 High Speed CML Output The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up resistors. The transmit outputs must be AC coupled. HSTXAP HSRXAP 50 ohm transmission line 50 VTERM 50 GND 50 ohm transmission line HSTXAN TRANSMITTER HSRXAN MEDIA RECEIVER Figure 7-17. Example of High Speed I/O AC Coupled Mode Current Mode Logic (CML) drivers often require external components. The disadvantage of the external component is a limited edge rate due to package and line parasitic. The CML driver on TLK10031 has onchip 50 Ω termination resistors terminated to VDDT, providing optimum performance for increased speed requirements. The transmitter output driver is highly configurable allowing output amplitude and deemphasis to be tuned to the channel's individual requirements. Software programmability allows for very flexible output amplitude control. Only AC coupled output mode is supported. When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is attenuated due to dielectric losses and the skin effect of the media. This causes a “smearing” of the data eye when viewed on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to provide equalization for the high frequency loss, 4-tap finite impulse response (FIR) transmit de-emphasis is implemented Output swing control is via MDIO. 42 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.4.16.2 High Speed Receiver The high speed receiver is differential CML with internal termination resistors. The receiver requires AC coupling. The termination impedances of the receivers are configured as 100 Ω with the center tap weakly tied to 0.7×VDDT, and a capacitor is used to create an AC ground (see Figure 7-17). TLK10031 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion loss by amplifying the high frequency components of the signal, reducing inter-symbol interference. Equalization can be enabled or disabled per register settings. Both feed-forward equalization (FFE) and decision feedback equalization (DFE) are used to minimize the pre-cursor and post-cursor components (respectively) of intersymbol interference. 7.4.16.3 Loss of Signal Output Generation (LOS) Loss of input signal detection is based on the voltage level of each serial input signal INA*P/N, HSRXAP/N. When LOS indication is enabled and the channel's differential serial receive input level is < 75 mVpp, the channel's respective LOS indicator (LOSA) are asserted (high true). If the input signal is >150 mVpp, the LOS indicator will be deasserted (low false). Outside of these ranges, the LOS indicator is undefined. The LOS indicators can also directly be read through the MDIO interface. The following additional critical status conditions can be combined with the loss of signal condition enabling additional real-time status signal visibility on the LOSA output: 1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of channel synchronization can be optionally logically OR’d (disabled by default) with the internally generated LOS condition. 2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled. The internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions. 3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with LOS condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or disparity error) is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions. 4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s) when enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions. 5. AZDONE (Auto Zero Calibration Done) - Inverted and Logically OR’d with LOS conditions(s) when enabled. HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions. Refer to Figure 7-18, which shows the detailed implementation of the LOSA signal along with the associated MDIO control registers for the General Purpose SERDES mode. More details about LOS settings including configurations related to the 10GBASE-KR mode can be found in the Programmers Reference section. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 43 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Loss of Signal (HS) ENABLE LOS INA0 ENABLE LOS INA1 ENABLE LOS INA2 Loss of Signal (LS) ENABLE LOS INA3 ENABLE PLL Locked (HS) ENABLE PLL Locked (LS) ENABLE 8B/10B Invalid (HS) ENABLE 8B/10B Invalid Code INA0 LOSA ENABLE 8B/10B Invalid Code INA1 ENABLE 8B/10B Invalid Code INA2 ENABLE 8B/10B Invalid Code INA3 8B/10B Invalid Code (LS) ENABLE Loss of CH Signal (HS) ENABLE Loss of Sync INA0 ENABLE Loss of Sync INA1 ENABLE Loss of Sync INA2 Loss of CH Signal (LS) ENABLE Loss of Sync INA3 ENABLE AGCLOCK (HS) ENABLE AZDONE (HS) ENABLE Figure 7-18. LOSA – Logic Circuit Implementation 44 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.4.17 MDIO Management Interface The TLK10031 supports the Management Data Input/Output (MDIO) Interface as defined in Clauses 22 and 45 of the IEEE 802.3-2008 Ethernet specification. The MDIO allows register-based management and control of the serial links. The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference (MDC). The device identification and port address are determined by control pins (see Section 4). Also, whether the device responds as a Clause 22 or Clause 45 device is also determined by control pin ST (see Section 4). In Clause 45 (ST = 0) and Clause 22 (ST = 1), the top 4 control pins PRTAD[4:1] determine the device port address. In this mode, TLK10031 responds if the PHY address field on the MDIO protocol (PA[4:1]) matches PRTAD[4:1] pin value, and the PHY address field PA[0] = 0. In Clause 22 (ST = 1) mode, only 32 (5’b00000 to 5’b11111) register addresses can be accessed through standard protocol. Due to this limitation, an indirect addressing method (More description in Clause 22 Indirect Addressing section) is implemented to provide access to all device specific control/status registers that cannot be accessed through the standard Clause 22 register address space. Write transactions which address an invalid register or device or a read only register will be ignored. Read transactions which address an invalid register or device will return a 0. 7.4.18 MDIO Protocol Timing Timing for a Clause 45 address transaction is shown in Figure 7-19. The Clause 45 timing required to write to the internal registers is shown in Figure 7-20. The Clause 45 timing required to read from the internal registers is shown in Figure 7-21. The Clause 45 timing required to read from the internal registers and then increment the active address for the next transaction is shown in Figure 7-22. The Clause 22 timing required to read from the internal registers is shown in Figure 7-23. The Clause 22 timing required to write to the internal registers is shown in Figure 7-24. MDC 0 MDIO 0 0 > 32 "1's" Preamble 0 Addr Code Start PA[4:0] PHY Addr DA[4:0] Dev Addr 1 0 Turn Around A15 A0 Reg Addr 1 Idle Figure 7-19. CL45 - Management Interface Extended Space Address Timing MDC 0 MDIO 0 > 32 "1's" Preamble Start 0 1 Write Code PA[4:0] PHY Addr DA[4:0] Dev Addr 1 0 Turn Around D15 D0 Data 1 Idle Figure 7-20. CL45 - Management Interface Extended Space Write Timing Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 45 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com MDC 0 MDIO 0 1 > 32 "1's" Preamble 1 Read Code Start PA[4:0] PHY Addr Z DA[4:0] Dev Addr 0 Turn Around D15 D0 1 Idle Data Figure 7-21. CL45 - Management Interface Extended Space Read Timing MDC 0 MDIO 0 > 32 "1's" Preamble Start 1 0 PA[4:0] Read Inc Code PHY Addr Z DA[4:0] Dev Addr 0 Turn Around D15 D0 1 Idle Data Figure 7-22. CL45 - Management Interface Extended Space Read And Increment Timing MDC MDIO 0 1 1 > 32 "1's" Read Code Start Preamble 0 PA[4:0] PHY Addr RA4 RA0 Z 0 Turn Around REG Addr D15 D0 Data 1 Idle Figure 7-23. CL22 - Management Interface Read Timing MDC MDIO 0 1 > 32 "1's" Preamble Start 0 1 Write Code PA[4:0] PHY Addr RA4 RA0 REG Addr 1 0 Turn Around D15 D0 Data 1 Idle Figure 7-24. CL22 - Management Interface Write Timing The IEEE 802.3 Clause 22/45 specification defines many of the registers, and additional registers have been implemented for expanded functionality. 7.4.19 Clause 22 Indirect Addressing Due to Clause 22 register space limitations, an indirect addressing method is implemented so that the extended register space can be accessed through Clause 22. All the device specific control and status registers that cannot be accessed through Clause 22 direct addressing can be accessed through this indirect addressing method. To access this register space, an address control register (Reg 30, 5’h1E) should be written with the register address followed by a read/write transaction to address content register (Reg 31, 5’h1F) to access the contents of the address specified in address control register. Following timing diagrams illustrate an example write transaction to Register 16’h9000 using indirect addressing in Clause 22. 46 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 MDC MDIO 0 1 0 > 32 "1's" Write Code Start Preamble 1 PA[4:0] 5'h1E PHY Addr REG Addr 1 0 16'h9000 Turn Around Data 1 Idle Figure 7-25. CL22 – Indirect Address Method – Address Write MDC MDIO 0 1 0 > 32 "1's" Write Code Start Preamble 1 PA[4:0] 5'h1F PHY Addr REG Addr 1 0 DATA Turn Around Data 1 Idle Figure 7-26. CL22 - Indirect Address Method – Data Write Following timing diagrams illustrate an example read transaction to read contents of Register 16’h9000 using indirect addressing in Clause 22. MDC MDIO 0 1 0 > 32 "1's" Write Code Start Preamble 1 PA[4:0] 5'h1E PHY Addr REG Addr 1 0 16'h9000 Turn Around Data 1 Idle Figure 7-27. CL22 - Indirect Address Method – Address Write MDC MDIO 0 1 > 32 "1's" Preamble Start 1 0 Read Code PA[4:0] PHY Addr 5'h1F REG Addr Z 0 Turn Around D15 D0 Data 1 Idle Figure 7-28. CL22 - Indirect Address Method – Data Read 7.4.20 Provisionable XAUI Clock Tolerance Compensation The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the reference clocks for two devices on a XAUI/KR link have the same specified frequencies, there are slight differences that, if not compensated for, will lead to over or under run of the FIFOs on the receive/transmit data paths. The XAUI CTC block performs the clock domain transition and rate compensation by utilizing a FIFO that is 32 deep and 40-bits wide. The usable FIFO size in the RX and TX directions is dependent upon the RX_FIFO_DEPTH and TX_FIFO_DEPTH MDIO fields, respectively. The word format is illustrated in Figure 7-29. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 47 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com ctrl[0] data_ln1_in[8:0] data_ln0_in[8:0] lane 0 lane 1 ctrl[1] data_ln2_in[8:0] lane 2 data_ln3_in[8:0] ctrl[2] 0 lane 3 ctrl[3] 39 Figure 7-29. XAUI CTC FIFO Word Format The XAUI CTC performs one of the following operations to compensate the clock rate difference: 1. Delete Idle column from the data stream 2. Delete Sequence column from the data stream (enabled via MDIO) 3. Insert Idle column to the data stream. The following rules apply for insertion/removal: • Idle insertion/deletion occurs in groups of 4 idle characters (i.e., in columns) • Idle characters are added following Idle or Sequence ordered_set • Idle characters are not added while data is being received • When deleting Idle characters, minimum IPG of 5 characters is maintained. /T/ characters are counted towards IPG. • The first Idle column after /T/ is never deleted • Sequence ordered_sets are deleted only when two consecutive Sequence columns are received. In this case, only one of the two Sequence columns will be deleted. 7.4.20.1 Insertion: When the FIFO fill level is at or below LOW watermark (insertion is triggered), the XAUI CTC needs to insert an IDLE column. It does so by skipping a read from the FIFO and inserting IDLE column to the data stream. It continues the insertion until the FIFO fill level is above the mid point. This occurs on the read side of the FIFO. 7.4.20.2 Removal: When the FIFO fill level is at or above HIGH watermark (deletion is triggered), the XAUI CTC needs to remove an IDLE column. It does so by skipping a write to the FIFO and discarding the IDLE column or Sequence ordered_set. It continues the deletion until the FIFO fill level is below the mid point. This occurs on the write side of the FIFO. On the write side of the XAUI CTC FIFO a 40-bit write is performed at every cycle of the 312.5 MHz clock except during removal when it discards the IDLE or sequence ordered_set. On the read side of the XAUI CTC FIFO a 40-bit read is performed at every cycle of the 312.5 MHz clock except during insertion when it generates IDLE columns to the output while not reading the FIFO at all. In IEEE 802.3-2008 the XAUI clock rate tolerance is given as 3.125 GHz ± 100 ppm, the XGMII clock rate tolerance is given as 156.25 MHz ± 0.02% (which is equivalent to 200ppm), and the Jumbo packet size is 9600 bytes which is equivalent to 2400 cycles of 312.5 MHz clock. The average inter-frame gap is 12 bytes (3 columns), which implies that there is one opportunity to insert/delete a column in between every packet on average. This gives one column deletion/insertion in every 2400 columns which results in a 400 ppm tolerance capability. If the IPG increases, then more clock rate variance or larger packet size can be supported. Note that the maximum frequency tolerance is limited by the frequency accuracy requirement of the reference clock. 48 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 The number of words in the FIFO (fifo_depth[2:0]) and the HIGH/LOW watermark levels (wmk_sel[1:0]) are set through MDIO register 01.8001, and determine the allowable difference between the write clock and the read clock as well as the maximum packet size that can be processed without FIFO collision. At these watermarks the drop and insert start respectively and must happen before it hits overflow/underflow condition. Although the FIFO is supposed to never overflow/underflow given the average IPG, if it ever happens the overflow/underflow indications signal the error to the MDIO interface and the FIFO is reset. Note that the overflow/underflow status indications are latched high and cleared when read. Table 7-11 shows XAUI CTC FIFO configuration and capabilities: IPG to support the max pkt size Max pkt size (100ppm) Max pkt size (50ppm) Min #of removable columns in Max pkt size (200ppm) 8 Max pkt size (400ppm) 12 000 Min Latency (Cycles) 001 Nom Latency (Cycles) 16 Max Latency (Cycles) 010 HIGH Watermark 24 LOW Watermark 011 32 wmk_sel[1:0] 1xx FIFO Depth fifo_depth[2:0] Table 7-11. XAUI CTC FIFO Configurations 11 15 18 28 16 4 100KB 200KB 400KB 800KB 10 10 13 20 28 16 4 80KB 160KB 320KB 640KB 8 01 10 23 28 16 4 50KB 100KB 200KB 400KB 5 00 6 27 28 16 4 10KB 20KB 40KB 80KB 1 11 11 14 20 12 4 60KB 120KB 240KB 480KB 6 10 9 16 20 12 4 40KB 80KB 160KB 320KB 4 0x 6 19 20 12 4 10KB 20KB 40KB 80KB 1 1x 7 10 13 8 3 30KB 60KB 120KB 240KB 3 0x 5 12 13 8 3 10KB 20KB 40KB 80KB 1 xx 5 8 9 6 3 10KB 20KB 40KB 80KB 1 Plain FIFO, No CTC 7 4 1 default No limit on pkt size (needs 0 ppm to work) NOTE To support the max packet sizes as shown in Table 7-11, it is assumed that there are enough IDLE columns in IPG for deletion. Below is one example: Configure the FIFO to be 32-deep (fifo_depth[2:0] = 3’b1xx) and set the LOW/HIGH Watermarks to 10/23 (wmk_sel[1:0] = 2’b01). If the write clock is faster than the read clock by 200ppm, to support the max packet size of 100KB, a minimum of 5 removable columns in IPG is required (either IDLE columns or Sequence ordered_sets). If there are only 4 removable columns in IPG, the max packet size supported is dropped to 80KB. If there are only 3 removable columns in IPG, the max packet size supported is dropped to 60KB, and so on. As a rule of thumb, one removable column in IPG corresponds to 10KB at 400ppm, 20KB at 200ppm, 40KB at 100ppm, and 80KB at 50ppm Figure 7-30 through Figure 7-40 illustrate XAUI CTC FIFO configuration and capabilities. The green region (the middle of the FIFO fill level) indicates that the FIFO is operating stability without insertion or deletion. The more green bars in the figure, the more clock wander it can tolerate. The more yellow bars in the figure, the bigger packet size it can support. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 49 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 32 words (fifo_depth=3'b1xx, wmk_sel=2'b00) 40 bits Underflow Drop Overflow Insert HIGH Watermark LOW Watermark Figure 7-30. Organization of the XAUI CTC FIFO (32-Deep, Low Watermark) 32 words (fifo_depth=3'b1xx, wmk_sel=2'b01) 40 bits Underflow Insert Drop Overflow HIGH Watermark LOW Watermark Figure 7-31. Organization of the XAUI CTC FIFO (32-Deep, Mid Watermark) 50 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 32 words (fifo_depth=3'b1xx, wmk_sel=2'b10) 40 bits Underflow Insert Drop Overflow HIGH Watermark LOW Watermark Figure 7-32. Organization of the XAUI CTC FIFO (32-Deep, Mid-High Watermark) 32 words (fifo_depth=3'b1xx, wmk_sel=2'b11) 40 bits Underflow Insert Drop Overflow HIGH Watermark LOW Watermark Figure 7-33. Organization of the XAUI CTC FIFO (32-Deep, High Watermark) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 51 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 24 words (fifo_depth=3'b011, wmk_sel=2'b0x) 40 bits Underflow Insert Drop LOW Watermark Overflow HIGH Watermark Figure 7-34. Organization of the XAUI CTC FIFO (24-Deep, Low Watermark) 24 words (fifo_depth=3'b011, wmk_sel=2'b10) 40 bits Underflow Insert Drop LOW Watermark Overflow HIGH Watermark Figure 7-35. Organization of the XAUI CTC FIFO (24-Deep, Mid Watermark) 24 words (fifo_depth=3'b011, wmk_sel=2'b11) 40 bits Underflow Insert Drop LOW Watermark Overflow HIGH Watermark Figure 7-36. Organization of the XAUI CTC FIFO (24-Deep, High Watermark) 52 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 16 words (fifo_depth=3'b010 wmk_sel=2'b0x) 40 bits Underflow Insert Overflow Drop HIGH Watermark LOW Watermark Figure 7-37. Organization of the XAUI CTC FIFO (16-Deep, Low Watermark) 16 words (fifo_depth=3'b010 wmk_sel=2'b1x) 40 bits Underflow Insert LOW Watermark Overflow Drop HIGH Watermark Figure 7-38. Organization of the XAUI CTC FIFO (16-Deep, High Watermark) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 53 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 12 words (ctc_depth=3'b001) 40 bits Underflow Insert LOW Watermark Overflow Drop HIGH Watermark Figure 7-39. Organization of the XAUI CTC FIFO (12-Deep) 8 words (ctc_depth=3'b000), no CTC 40 bits Underflow Overflow Figure 7-40. Organization of the XAUI CTC FIFO (8-Deep) 54 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Register Maps 7.5.1 Register Bit Definitions 7.5.1.1 RW: Read-Write User can write 0 or 1 to this register bit. Reading this register bit returns the same value that has been written. 7.5.1.2 RW/SC: Read-Write Self-Clearing User can write 0 or 1 to this register bit. Writing a "1" to this register creates a high pulse. Reading this register bit always returns 0. 7.5.1.3 RO: Read-Only This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its current value. 7.5.1.4 RO/LH: Read-Only Latched High This register can only be read. Writing to this register bit has no effect. Reading a "1" from this register bit indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a "0" from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last time the register was read. A latched high register, when read high, should be read again to distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read will read low. If it is still occurring, the second read will read high. Reading this register bit automatically resets its value to 0. 7.5.1.5 RO/LL: Read-Only Latched Low This register can only be read. Writing to this register bit has no effect. Reading a "0" from this register bit indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a "1" from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last time the register was read. A latched low register, when read low, should be read again to distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read will read high. If it is still occurring, the second read will read low. Reading this register bit automatically sets its value to 1. 7.5.1.6 COR: Clear-On-Read This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its current value, then resets its value to 0. Counter value freezes at Max. Following code letters in Name field of each control/status register bit(s) indicate the mode that they are applicable/valid. R = Indicates control/status bit(s) valid in 10GKR mode X = Indicates control/status bit(s) valid in 1GKX mode G = Indicates control/status bit(s) valid in 10G general purpose serdes mode 7.5.2 Vendor Specific Device Registers Below registers can be accessed directly through Clause 22 and Clause 45. In Clause 45 mode, these registers can be accessed by setting device address field to 0x1E (DA[4:0] = 5’b11110). In Clause 22 mode, these registers can be accessed by setting 5 bit register address field to same value as 5 LSB bits of Register Address field specified for each register. For example, 16 bit register address 0x001C in clause 45 mode can be accessed by setting register address field to 5’h1C in clause 22 mode. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 55 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.2.1 www.ti.com GLOBAL_CONTROL_1 (register: 0x0000) (default: 0x0610) (device address: 0x1E) Figure 7-41. GLOBAL_CONTROL_1 Register 15 GLOBAL_RESET (RXG) R/W 14 7 6 13 12 PRTAD0_PIN_EN_SEL[2:0] (RXG) R/W RESERVED R/W 5 PRTAD0_ PIN_EN (RXG) R/W 4 11 10 RESERVED 9 8 RESERVED R/W R/W 3 2 1 0 PRBS_PASS_OVERLAY[4:0] (RXG) R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-12. GLOBAL_CONTROL_1 Field Description Bit Field Type 15 GLOBAL_RESET (RXG) R/W (1) Global reset. 0 = Normal operation (Default 1’b0) 1 = Resets TX and RX data path including MDIO registers. Equivalent to asserting RESET_N. PRTAD0_PIN_EN_SEL[2:0] (RXG) R/W PRTAD0 pin selection control. Valid only when 1E.0000 bit 5 is 1. PRTAD0 is used for the assignment specified below 000 = Stopwatch (Default 3’b000) 001 = Reserved 010 = Tx data switch 011 = Rx data switch 100 = Reserved 101 = Reserved 11x = Reserved 14:12 11 Reserved (RXG) Reset Description Reserved For TI use only. Always reads 0. 10:7 RESERVED R/W For TI use only (Default 5’b1100) 6 RESERVED R/W For TI use only. Always reads 0. 5 PRTAD0_PIN_EN (RXG) R/W PRTAD0 pin enable control. 0 = Input pin (PRTAD0) is used for the assignment specified in 1E.0000 bits 14:12 (Default 1’b0) 1 = Input pin (PRTAD0) is not used for the assignment specified in 1E.0000 bits 14:12 PRBS_PASS_OVERLAY[4:0] (RXG) R/W PRBS_PASS pin status selection. Applicable only when PRBS test pattern verification is enabled on HS side or LS side. PRBS_PASS pin reflects PRBS verification status on HS/LS side. LS Serdes lanes 1/2/3 are not applicable in 1GKX modes. 1xx00 = PRBS_PASS reflects HS serdes PRBS verification. If PRBS verification fails on HS serdes, PRBS_PASS will be asserted low. (Default 5’b10000) 00000 = Status from HS Serdes side 00001 = Reserved 000x1 = Reserved 00100 = Status from LS Serdes side Lane 0 00101 = Status from LS Serdes side Lane 1 00110 = Status from LS Serdes side Lane 2 00111 = Status from LS Serdes side Lane 3 01000 = Reserved 01001 = Reserved 0101x = Reserved 01100 = Reserved 01101 = Reserved 01110 = Reserved 01111 = Reserved 4:0 (1) 56 After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5.2.2 (1) SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 CHANNEL_CONTROL_1 (register: 0x0001) (default: 0x0B00) (device address: 0x1E) (1) This global register is channel independent. Figure 7-42. CHANNEL_CONTROL_1 Register 15 14 13 LT_TRAINING_ 10G_RX_MOD POWERDOWN CONTROL E_SEL (RXG) (XG) (G) R/W R/W R/W 7 6 12 10G_TX_MOD E_SEL (G) R/W 5 4 11 10 SW_DEV_MOD SW_PCS_SEL E_SEL (RX) (RXG) R/W R/W 3 RESERVED R 2 9 10G_RX_DEM UX_SEL (G) R/W 8 10G_TX_MUX_ SEL (G) R/W 1 REFCLK_SW_ SEL (RXG) R/W 0 LS_REFCLK_S EL (RXG) R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-13. CHANNEL_CONTROL_1 Field Description Bit Field Type 15 POWERDOWN (RXG) R/W Setting this bit high powers down entire data path with exception that MDIO interface stays active. 0 = Normal operation (Default 1’b0) 1 = Power Down mode is enabled. 14 LT_TRAINING_CONTROL (XG) R/W Link training control. Valid in 10G and 1GKX modes only. 0 = Link training disabled(Default 1’b0) 1 = Link training enable control dependent on LT_TRAINING_ENABLE (1E.0036 bit 1). 13 10G_RX_MODE_SEL (G) R/W RX mode selection. Valid in 10G only. 0 = RX mode dependent upon RX_DEMUX_SEL(Default 1’b0) 1 = Enables 1 to 1 mode on receive channel. 12 10G_TX_MODE_SEL (G) R/W TX mode selection Valid in 10G only. 0 = TX mode dependent upon TX_MUX_SEL (Default 1’b0) 1 = Enables 1 to 1 mode on transmit channel. 11 SW_PCS_SEL (RX) R/W Applicable in Clause 45 mode only. Valid only when MODE_SEL pin is 0, AN_ENABLE (07.0000 bit 12) is 0 and SW_DEV_MODE_SEL (1E.0001 bit 10) is 0. 0 = Set device to 10G-KR mode(Default 1’b1) 1 = Set device to 1G-KX mode 10 SW_DEV_MODE_SEL (RXG) R/W Valid only when MODE_SEL pin is 0 0 = Device set to 10G mode 1 = In clause 45 mode, device mode is set using Auto negotiation. In clause 22 mode, device set to 1G-KX mode(Default 1’b0) 9 10G_RX_DEMUX_SEL (G) R/W RX De-Mux selection control for lane de-serialization on receive channel. Valid in 10G and when 10G_RX_MODE_SEL (1E.0001 bit 13) is LOW 0 = 1 to 2 1 = 1 to 4 (Default 1’b1) 8 10G_TX_MUX_SEL (G) R/W TX Mux selection control for lane serialization on transmit channel. Valid in 10G and when 10G_TX_MODE_SEL (1E.0001 bit 12) is LOW 0 = 2 to 1 1 = 4 to 1 (Default 1’b1) 7:2 Reset Description RESERVED R/O For TI use only 1 REFCLK_SW_SEL (RXG) R/W HS Reference clock selection. 0 = Selects REFCLK_0_P/N as clock reference to HS side serdes macro(Default 1’b0) 1 = Selects REFCLK_1_P/N as clock reference to HS side serdes macro 0 LS_REFCLK_SEL (RXG) R/W LS Reference clock selection. 0 = LS side serdes macro reference clock is same as HS side serdes reference clock (E.g. If REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_0_P/N is selected as LS side serdes macro reference clock and vice versa) (Default 1’b0) 1 = Alternate reference clock is selected as clock reference to LS side serdes macro (E.g. If REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_1_P/N is selected as LS side serdes macro reference clock and vice versa) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 57 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.2.3 www.ti.com HS_SERDES_CONTROL_1 (register: 0x0002 ) (default: 0x831D) (device address: 0x1E) Figure 7-43. HS_SERDES_CONTROL_1 Register 15 14 13 12 11 10 4 HS_ENPLL (RXG) R/W 3 2 1 HS_PLL_MULT[3:0] (RXG) R/W RESERVED R/W 7 6 HS_VRANGE (RXG R/W RESERVED R/W 5 RESERVED R/W 9 8 HS_LOOP_BANDWIDTH[1:0] (RXG) R/W 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-14. HS_SERDES_CONTROL_1 Field Description Bit Field Type Reset HS_LOOP_BANDWIDTH[1:0] (RXG) R/W HS Serdes PLL Loop Bandwidth settings 00 = Medium Bandwidth 01 = Low Bandwidth 10 = High Bandwidth 11 = Ultra High Bandwidth. (Default 2'b11) 7 RESERVED R/W For TI use only (Default 1’b0) 6 HS_VRANGE (RXG) R/W HS Serdes PLL VCO range selection. 0 = VCO runs at higher end of frequency range (Default 1’b0) 1 = VCO runs at lower end of frequency range This bit needs to be set HIGH if VCO frequency (REFCLK *HS_PLL_MULT) is below 2.5 GHz. 5 RESERVED R/W For TI use only (Default 1’b0) 4 HS_ENPLL (RXG) R/W HS Serdes PLL enable control. HS Serdes PLL is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables PLL in HS serdes 1 = Enables PLL in HS serdes (Default 1’b1) HS_PLL_MULT[3:0] (RXG) R/W HS Serdes PLL multiplier setting (Default 4’b1101). Refer : Table 7-15 HS PLL multiplier control 15:10 9:8 3:0 Description For TI use only (Default 6’b100000) Table 7-15. HS PLL Multiplier Control HS_PLL_MULT[3:0] 58 HS_PLL_MULT[3:0] Value PLL Multiplier factor Value PLL Multiplier factor 0000 Reserved 1000 12x 0001 Reserved 1001 12.5x 0010 4x 1010 15x 0011 5x 1011 16x 0100 6x 1100 16.5x 0101 8x 1101 20x 0110 8.25x 1110 25x 0111 10x 1111 Reserved Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5.2.4 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 HS_SERDES_CONTROL_2 (register: 0x0003) (default: 0xA848) (device address: 0x1E) Figure 7-44. HS_SERDES_CONTROL_2 Register 15 14 13 HS_SWING[3:0] (RXG) R/W 7 6 HS_AGCCTRL[1:0] (RXG R/W 12 11 HS_ENTX (RXG) R/W 10 HS_EQHLD (RXG) R/W 4 3 HS_ENRX (RXG) R/W 2 5 HS_AZCAL[1:0] (RXG) R/W 9 8 HS_RATE_TX [1:0] (RXG) R/W 1 HS_RATE_RX [2:0] (RXG) R/W 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-16. HS_SERDES_CONTROL_2 Field Description Bit Field Type HS_SWING[3:0] (RXG) R/W Transmitter Output swing control for HS Serdes. (Default 4’b1010) Refer Table 7-17. 11 HS_ENTX (RXG) R/W HS Serdes transmitter enable control. HS Serdes transmitter is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables HS serdes transmitter 1 = Enables HS serdes transmitter (Default 1’b1) 10 HS_EQHLD (RXG) R/W HSRX Equalizer hold control. 0 = Normal operation (Default 1’b0) 1 = Holds equalizer and long tail correction in its current state 9:8 HS_RATE_TX [1:0] (RXG) R/W HS Serdes TX rate settings. 00 = Full rate (Default 2’b00) 01 = Half rate 10 = Quarter rate 11 = Eighth rate 7:6 HS_AGCCTRL[1:0] (RXG) R/W Adaptive gain control loop. 00 = Attenuator will not change after lock has been achieved, even if AGC becomes unlocked 01 = Attenuator will not change when in lock state, but could change when AGC becomes unlocked (Default 2’b01) 10 = Force the attenuator off 11 = Force the attenuator on 5:4 HS_AZCAL[1:0] (RXG) R/W Auto zero calibration. 00 = Auto zero calibration initiated when receiver is enabled (Default 2’b00) 01 = Auto zero calibration disabled 10 = Forced with automatic update. 11 = Forced without automatic update HS_ENRX (RXG) R/W HS Serdes receiver enable control. HS Serdes receiver is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables HS serdes receiver 1 = Enables HS serdes receiver (Default 1’b1) HS_RATE_RX [2:0] (RXG) R/W HS Serdes RX rate settings. This setting is automatically controlled and value set through these register bits is ignored unless REFCLK_FREQ_SEL_1 or related OVERRIDE bit is set. 000 = Full rate (Default 3’b000) 001 = Half rate 110 = Quarter rate 111 = Eighth rate 001 = Reserved 01x = Reserved 100 = Reserved 15:12 3 2:0 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 59 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Table 7-17. HSTX AC Mode Output Swing Control HS_SWING[3:0] AC MODE TYPICAL AMPLITUDE (mVdfpp) 7.5.2.5 0000 130 0001 220 0010 300 0011 390 0100 480 0101 570 0110 660 0111 750 1000 830 1001 930 1010 1020 1011 1110 1100 1180 1101 1270 1110 1340 1111 1400 HS_SERDES_CONTROL_3 (register: 0x0004) (default: 0x1500) (device address: 0x1E) Figure 7-45. HS_SERDES_CONTROL_3 Register 15 HS_ENTRACK (RXG) R/W 7 RESERVED R/W 14 13 HS_EQPRE[2:0] (RXG) R/W 12 6 5 HS_PEAK_DIS HS_H1CDRMO ABLE DE (RXG) (RXG) R/W R/W 4 11 10 HS_CDRFMULT[1:0] (RXG) R/W 3 2 9 8 HS_CDRTHR[1:0] (RXG) R/W 1 0 HS_TWCRF[4:0] (RXG) R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-18. HS_SERDES_CONTROL_3 Field Description Bit Field Type 15 HS_ENTRACK (RXG) R/W HSRX ADC Track mode. 0 = Normal operation (Default 1’b0) 1 = Forces ADC into track mode 14:12 HS_EQPRE[2:0] (RXG) R/W Serdes Rx precursor equalizer selection 000 = 1/9 cursor amplitude 001 = 3/9 cursor amplitude (Default 3’b001) 010 = 5/9 cursor amplitude 011 = 7/9 cursor amplitude 100 = 9/9 cursor amplitude 101 = 11/9 cursor amplitude 110 = 13/9 cursor amplitude 111 = Disable 11:10 HS_CDRFMULT[1:0] (RXG) R/W Clock data recovery algorithm frequency multiplication selection (Default 2'b01) 00 =First order. Frequency offset tracking disabled 01 = Second order. 1x mode 10 = Second order. 2x mode 11 = Reserved HS_CDRTHR[1:0] (RXG) R/W Clock data recovery algorithm threshold selection (Default 2'b01) 00 = Four vote threshold 01 = Eight vote threshold 10 = Sixteen vote threshold 11 = Thirty two vote threshold 9:8 60 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Table 7-18. HS_SERDES_CONTROL_3 Field Description (continued) Bit Field Type 7 RESERVED R/W For TI use only (Default 1’b0) 6 HS_PEAK_DISABLE (RXG) R/W HS Serdes PEAK_DISABLE control 0 = Normal operation (Default 1’b0) 1 = Disables high frequency peaking. Suitable for 32 24 26 12/8 11 High High High NA 10 Mid-high Mid High 01 Mid Low Low 00 Low Low Low 9 RX_Q_CNT_IPG (R) RW 0 = Normal operation. (Default 1’b0) 1 = Sequence columns are counted as IPG. 8 RX_CTC_Q_DROP_EN (R) RW 0 = Normal operation. (Default 1’b0) 1 = Enable Q column drop in RX CTC. 7 XMIT_IDLE (R) RW 1 = Transmit idle pattern onto LS side 0 = Normal operation (Default 1’b0) 6:4 TX_FIFO_DEPTH[2:0] (R) RW Tx CTC FIFO depth selection 1xx = 32 deep (Default 3’b100)011 = 24 deep 010 = 16 deep001 = 12 deep 000 = 8 deep (No CTC function) 3:2 TX_CTC_WMK_SEL[1:0] (R) RW Water mark selection for receive CTC Works in conjunction with TX_FIFO_DEPTH_SEL setting (Default 2’b11) Depth-> 32 24 26 12/8 11 High High High NA 10 Mid-high Mid High 01 Mid Low Low 00 Low Low Low 1 TX_Q_CNT_IPG (R) RW 0 = Normal operation. (Default 1’b0) 1 = Sequence columns are counted as IPG. 0 TX_CTC_Q_DROP_EN (R) RW 0 = Normal operation. (Default 1’b0) 1 = Enable Q column drop in TX CTC 104 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.3.25 KR_VS_TP_GEN_CONTROL (register =0x8002) (default = 0x0000) (device address: 0x01) Figure 7-112. KR_VS_TP_GEN_CONTROL Register 15 14 13 12 11 10 9 8 RESERVED RW 7 RESERVED 6 5 4 RX_TPG_HLM_TEST_SEL[1:0] (R) RW RW 3 2 1 RX_TPG_CRP RX_TPG_CJPA RX_TPG_10GF AT_TEST_EN T_TEST_EN C_TEST_EN (R) (R) (R) RW RW RW 0 RX_TPG_HLM _TEST_EN (R) RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-94. KR_VS_TP_GEN_CONTROL Field Descriptions Bit Name Type Reset Description 15:6 RESERVED 5:4 RX_TPG_HLM_TEST_SEL[1:0] (R) RW For TI use only. Always reads 0. XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 00 = High Frequency test pattern(Default 2’b00) 01 = Low Frequency test pattern 10 = Mixed Frequency test pattern 11 = Normal operation 3 RX_TPG_CRPAT_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CRPAT test pattern generation 2 RX_TPG_CJPAT_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CJPAT test pattern generation 1 RX_TPG_10GFC_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables 10 GFC CJPAT test pattern generation 0 RX_TPG_HLM_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables H/L/M test pattern generation Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 105 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.3.26 KR_VS_TP_VER_CONTROL (register = 0x8003) (default = 0x0000) (device address: 0x01) Figure 7-113. KR_VS_TP_VER_CONTROL Register 15 14 RESERVED 13 12 11 TX_TPV_HLM_TEST_ TX_TPV_CRPAT_T SEL[1:0] EST_EN (R) (R) RW RW RW 7 6 5 4 10 TX_TPV_CJPAT_T EST_EN (R) RW 9 TX_TPV_10GFC_T EST_EN (R) RW 8 TX_TPV_HLM_TES T_EN (R) RW 2 1 0 3 RESERVED RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-95. KR_VS_TP_VER_CONTROL Field Descriptions Name Type 15:14 Bit RESERVED RW For TI use only. Always reads 0. 13:12 TX_TPV_HLM_TEST_SEL[1:0] (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 00 = High Frequency test pattern(Default 2’b00) 01 = Low Frequency test pattern 10 = Mixed Frequency test pattern 11 = Normal operation 11 TX_TPV_CRPAT_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CRPAT test pattern verification 10 TX_TPV_CJPAT_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CJPAT test pattern verification 9 TX_TPV_10GFC_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables 10 GFC CJPAT test pattern verification 8 TX_TPV_HLM_TEST_EN (R) RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables HL/M test pattern verification RESERVED RW For TI use only(Default 8’b00000000) 7:0 Reset Description 7.5.3.27 KR_VS_CTC_ERR_CODE_LN0 (register = 0x8005) (default = 0xCE00) (device address: 0x01) Figure 7-114. KR_VS_CTC_ERR_CODE_LN0 Register 15 14 13 12 11 10 KR_CTC_ERR_CODE_LN0 (R) RW 9 8 7 6 5 4 3 2 RESERVED 1 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-96. KR_VS_CTC_ERR_CODE_LN0 Field Descriptions Name Type 15:7 Bit KR_CTC_ERR_CODE_LN0 (R) RW Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 0 corresponds to 8’h9C with the control bit being 1’b1. The default values for lanes 0~3 correspond to ||LF|| 6:0 RESERVED RW For TI use only. Always reads 0. 106 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.3.28 KR_VS_CTC_ERR_CODE_LN1 (register = 0x8006) (default =0x0000) (device address: 0x01) Figure 7-115. KR_VS_CTC_ERR_CODE_LN1 Register 15 14 13 12 11 10 KR_CTC_ERR_CODE_LN1 (R) RW 9 8 7 6 5 4 3 2 RESERVED 1 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-97. KR_VS_CTC_ERR_CODE_LN1 Field Descriptions Name Type 15:7 Bit KR_CTC_ERR_CODE_LN1 (R) RW Reset Description Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 1 corresponds to 8’h00 with the control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF|| 6:0 RESERVED RW For TI use only. Always reads 0. 7.5.3.29 KR_VS_CTC_ERR_CODE_LN2 (register = 0x8007) (default = 0x0000) (device address: 0x01) Figure 7-116. KR_VS_CTC_ERR_CODE_LN2 Register 15 14 13 12 11 10 KR_CTC_ERR_CODE_LN2 (R) RW 9 8 7 6 5 4 3 2 RESERVED 1 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-98. KR_VS_CTC_ERR_CODE_LN2 Field Descriptions Bit(s) Name Type 15:7 KR_CTC_ERR_CODE_LN2 (R) RW Reset Description Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 2 corresponds to 8’h00 with the control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF|| 6:0 RESERVED RW For TI use only. Always reads 0. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 107 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.3.30 KR_VS_CTC_ERR_CODE_LN3 (register = 0x8008) (default = 0x0080) (device address: 0x01) Figure 7-117. KR_VS_CTC_ERR_CODE_LN3 Register 15 14 13 12 11 10 KR_CTC_ERR_CODE_LN3 (R) RW 9 8 7 6 5 4 3 2 RESERVED 1 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-99. KR_VS_CTC_ERR_CODE_LN3 Field Descriptions Name Type 15:7 Bit KR_CTC_ERR_CODE_LN3 (R) RW Reset Description Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 3 corresponds to 8’h01 with the control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF|| 6:0 RESERVED RW For TI use only. Always reads 0. 7.5.3.31 KR_VS_LN0_EOP_ERROR_COUNTER (register = 0x8010) (default = 0xFFFD) (device address: 0x01) Figure 7-118. KR_VS_LN0_EOP_ERROR_COUNTER Register 15 14 13 12 11 10 9 8 7 6 KR_LN0_EOP_ERR_COUNT (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-100. KR_VS_LN0_EOP_ERROR_COUNTER Field Descriptions Bit 15:0 Name Type KR_LN0_EOP_ERR_COUNT (R) COR Reset Description Lane 0 End of packet Error counter. End of packet error is detected when Terminate character is in lane 0 and 1 or both of the following holds: ● Terminate character is not followed by /K/ characters in lanes 1, 2 & 3 ● The column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. 7.5.3.32 KR_VS_LN1_EOP_ERROR_COUNTER (register = 0x8011) (default = 0xFFFD) (device address: 0x01) Figure 7-119. KR_VS_LN1_EOP_ERROR_COUNTER Register 15 14 13 12 11 10 9 8 7 6 KR_LN1_EOP_ERR_COUNT (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-101. KR_VS_LN1_EOP_ERROR_COUNTER Field Descriptions Bit 15:0 Name Type KR_LN1_EOP_ERR_COUNT (R) COR Reset Description Lane 1 End of packet Error counter. End of packet error is detected when Terminate character is in lane 1 and one or both of the following holds: ● Terminate character is not followed by /K/ characters in lanes 1, 2 & 3 ● The column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. 108 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.3.33 KR_VS_LN2_EOP_ERROR_COUNTER (register = 0x8012) (default = 0xFFFD) (device address: 0x01) Figure 7-120. KR_VS_LN2_EOP_ERROR_COUNTER Register 15 14 13 12 11 10 9 8 7 6 KR_LN2_EOP_ERR_COUNT (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-102. KR_VS_LN2_EOP_ERROR_COUNTER Field Descriptions Bit 15:0 Name Type KR_LN1_EOP_ERR_COUNT (R) COR Reset Description Lane 2 End of packet Error counter. End of packet error is detected when Terminate character is in lane 2 and 1 or both of the following holds: ● Terminate character is not followed by /K/ characters in lanes 1, 2 & 3 ● The column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. 7.5.3.34 KR_VS_LN3_EOP_ERROR_COUNTER (register =0x8013 ) (default = 0xFFFD) (device address: 0x01) Figure 7-121. KR_VS_LN3_EOP_ERROR_COUNTER Register 15 14 13 12 11 10 9 8 7 6 KR_LN3_EOP_ERR_COUNT (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-103. KR_VS_LN3_EOP_ERROR_COUNTER Field Descriptions Bit(s) 15:0 Name Type KR_LN3_EOP_ERR_COUNT (R) COR Reset Description Lane 3 End of packet Error counter. End of packet error is detected when Terminate character is in lane 3 and the column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 109 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.3.35 KR_VS_TX_CTC_DROP_COUNT (register = 0x8014) (default = 0xFFFD) (device address: 0x01) Figure 7-122. KR_VS_TX_CTC_DROP_COUNT Register 15 14 13 12 11 10 9 8 7 6 TX_CTC_DROP_COUNT (R) COR 5 4 3 2 1 0 2 1 0 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-104. KR_VS_TX_CTC_DROP_COUNT Field Descriptions Bit 15:0 Field Type TX_CTC_DROP_COUNT (R) COR Reset Description Counter for number of idle drops in the transmit CTC. 7.5.3.36 KR_VS_TX_CTC_INSERT_COUNT (register = 0x8015) (default = 0xFFFD) (device address: 0x01) Figure 7-123. KR_VS_TX_CTC_INSERT_COUNT Register 15 14 13 12 11 10 9 8 7 6 TX_CTC_INS_COUNT (R) COR 5 4 3 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-105. KR_VS_TX_CTC_INSERT_COUNT Field Descriptions Bit 15:0 Field Type TX_CTC_INS_COUNT (R) COR Reset Description Counter for number of idle inserts in the transmit CTC. 7.5.3.37 KR_VS_RX_CTC_DROP_COUNT (register = 0x8016) (default = 0xFFFD) (device address: 0x01) Figure 7-124. KR_VS_RX_CTC_DROP_COUNT Register 15 14 13 12 11 10 9 8 7 6 5 4 3 RX_CTC_DROP_COUNT (R) COR LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-106. KR_VS_RX_CTC_DROP_COUNT Field Descriptions Bit 15:0 110 Field Type RX_CTC_DROP_COUNT (R) COR Reset Description Counter for number of idle drops in the receive CTC. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.3.38 KR_VS_RX_CTC_INSERT_COUNT (register = 0x8017) (default = 0xFFFD) (device address: 0x01) Figure 7-125. KR_VS_RX_CTC_INSERT_COUNT Register 15 14 13 12 11 10 9 8 7 6 RX_CTC_INS_COUNT (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-107. KR_VS_RX_CTC_INSERT_COUNT Field Descriptions Bit 15:0 Field Type RX_CTC_INS_COUNT (R) COR Reset Description Counter for number of idle inserts in the receive CTC. 7.5.3.39 KR_VS_STATUS_1 (register = 0x8018) (default = 0x0000) (device address: 0x01) Figure 7-126. KR_VS_STATUS_1 Register 15 TX_TPV_TP_ SYNC (R) RO 14 7 6 13 12 11 RESERVED 10 9 8 RO RESERVED RO 5 INVALID_S_ COL_ERR (R) RO/LH 4 INVALID_T_ COL_ERR (R) RO/LH 3 2 1 0 INVALID_XGMI INVALID_XGMI INVALID_XGMI INVALID_XGMI I_LN3 I_LN2 I_LN1 I_LN0 (R) (R) (R) (R) RO/LH RO/LH RO/LH RO/LH LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-108. KR_VS_STATUS_1 Field Descriptions Bit Field Type 15 TX_TPV_TP_SYNC (R) RO 0 = Test pattern sync is not achieved on on Tx side 1 = Test pattern sync is achieved on on Tx side 14:6 Reset Description RESERVED RO For TI use only 5 INVALID_S_COL_ERR (R) RO/LH 1 = Indicates invalid start (S) column error detected 4 INVALID_T_COL_ERR (R) RO/LH 1 = Indicates invalid terminate (T) column error detected 3 INVALID_XGMII_LN3 (R) RO/LH 1 = Indicates invalid XGMII character detected in Lane 3 2 INVALID_XGMII_LN2 (R) RO/LH 1 = Indicates invalid XGMII character detected in Lane 2 1 INVALID_XGMII_LN1 (R) RO/LH 1 = Indicates invalid XGMII character detected in Lane 1 0 INVALID_XGMII_LN0 (R) RO/LH 1 = Indicates invalid XGMII character detected in Lane 0 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 111 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.3.40 KR_VS_TX_CRCJ_ERR_COUNT_1 (register = 0x8019) (default = 0xFFFF) (device address: 0x01) Figure 7-127. KR_VS_TX_CRCJ_ERR_COUNT_1 Register 15 14 13 12 11 10 9 8 7 6 5 TX_TPV_CR_CJ_ERR_COUNT[31:16] (R) COR 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-109. KR_VS_TX_CRCJ_ERR_COUNT_1 Field Descriptions Bit 15:0 Field Type TX_TPV_CR_CJ_ERR_COUNT[31:16] (R) COR Reset Description Error Counter for CR/CJ test pattern verification on Tx side. MSBs [31:16] 7.5.3.41 KR_VS_TX_CRCJ_ERR_COUNT_2 (register = 0x801A) (default = 0xFFFD) (device address: 0x01) Figure 7-128. KR_VS_TX_CRCJ_ERR_COUNT_2 Register 15 14 13 12 11 10 9 8 7 6 TX_TPV_CR_CJ_ERR_COUNT[15:0] (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-110. KR_VS_TX_CRCJ_ERR_COUNT_2 Field Descriptions Bit 15:0 Field Type TX_TPV_CR_CJ_ERR_COUNT[15:0] (R) COR Reset Description Error Counter for CR/CJ test pattern verification on Tx side. MSBs [15:0] 7.5.3.42 KR_VS_TX_LN0_HLM_ERR_COUNT (register = 0x801B) (default = 0xFFFD) (device address: 0x01) Figure 7-129. KR_VS_TX_LN0_HLM_ERR_COUNT Register 15 14 13 12 11 10 9 8 7 6 TX_TPV_LN0_ERR_COUNT[15:0] (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-111. KR_VS_TX_LN0_HLM_ERR_COUNT Field Descriptions Bit 15:0 112 Field Value TX_TPV_LN0_ERR_COUNT[15:0] (R) COR Reset Description Error Counter for H/L/M test pattern verification on Lane 0 of Tx side Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.3.43 KR_VS_TX_LN1_HLM_ERR_COUNT (register = 0x801C) (default = 0xFFFD) (device address: 0x01) Figure 7-130. KR_VS_TX_LN1_HLM_ERR_COUNT Register 15 14 13 12 11 10 9 8 7 6 TX_TPV_LN1_ERR_COUNT[15:0] (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-112. KR_VS_TX_LN1_HLM_ERR_COUNT Field Descriptions Bit 15:0 Field Value TX_TPV_LN1_ERR_COUNT[15:0] (R) COR Reset Description Error Counter for H/L/M test pattern verification on Lane 1 of Tx side 7.5.3.44 KR_VS_TX_LN2_HLM_ERR_COUNT (register = 0x801D) (default = 0xFFFD) (device address: 0x01) Figure 7-131. KR_VS_TX_LN2_HLM_ERR_COUNT Register 15 14 13 12 11 10 9 8 7 6 TX_TPV_LN2_ERR_COUNT[15:0] (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-113. KR_VS_TX_LN2_HLM_ERR_COUNT Field Descriptions Bit 15:0 Field Type TX_TPV_LN2_ERR_COUNT[15:0] (R) COR Reset Description Error Counter for H/L/M test pattern verification on Lane 2 of Tx side 7.5.3.45 KR_VS_TX_LN3_HLM_ERR_COUNT (register = 0x801E) (default = 0xFFFD) (device address: 0x01) Figure 7-132. KR_VS_TX_LN3_HLM_ERR_COUNT Register 15 14 13 12 11 10 9 8 7 6 TX_TPV_LN3_ERR_COUNT[15:0] (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-114. KR_VS_TX_LN3_HLM_ERR_COUNT Field Descriptions Bit 15:0 Field Type TX_TPV_LN3_ERR_COUNT[15:0] (R) COR Reset Description Error Counter for H/L/M test pattern verification on Lane 3 of Tx side Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 113 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.3.46 LT_VS_CONTROL_2 (register = 0x9001) (default = 0x0000) (device address: 0x01) Figure 7-133. LT_VS_CONTROL_2 Register 15 14 RESERVED 13 12 RESERVED RW RW/SC 11 10 9 AP_SEARCH_MODE [2:0] (RXG) RW 8 7 6 5 4 3 RESERVED 2 1 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-115. LT_VS_CONTROL_2 Field Descriptions Field Type 15:14 Bit RESERVED RW For TI use only (Default 2'b00) 13:12 RESERVED RW/SC For TI use only (Default 2'b00) 11:9 AP_SEARCH_MODE[2:0] (RXG) RW 000 = Auto search, autotrain disabled (Default 3'b000) 001 = Full region search, autotrain disabled 010 = Auto search, autotrain enabled 011 = Full region search, autotrain enabled 1xx = Manual search 8:0 RESERVED RW For TI use only (Default 9'b000000000) 7.5.4 Reset Description PCS Registers The registers below can be accessed only in Clause 45 mode and with device address field set to 0x03 (DEVADD [4:0] = 5’b00011). Valid only when device is in 10GBASE-KR mode. 7.5.4.1 PCS_CONTROL (register = 0x0000) (default = 0x0000) (device address: 0x03) Figure 7-134. PCS_CONTROL Register XXX 15 PCS_RESET (R) 13 RW/SC 14 PCS_LOOPBA CK (R) RW 7 6 5 12 RESERVED RW 11 PCS_LP_MOD E (R) RW 10 3 2 4 9 RESERVED 8 RW 1 0 RESERVED RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-116. PCS_CONTROL Field Descriptions Bit Field Type 15 PCS_RESET (R) RW/SC 1 = Resets datapath and MDIO registers. Equivalent to asserting RESET_N. 0 = Normal operation (Default 1’b0) 14 PCS_LOOPBACK (R) RW 1 = Enables PCS loopback 0 = Normal operation (Default 1’b0) Requires Auto Negotiation and Link Training to be disabled. RESERVED RW For TI use only. Always reads 0. PCS_LP_MODE (R) RW 1 = Enable power down mode 0 = Normal operation (Default 1’b0) RESERVED RW For TI use only. Always reads 0. 13:12 11 10:0 114 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5.4.2 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 PCS_STATUS_1 (register = 0x0001) (default = 0x0002) (device address: 0x03) Figure 7-135. PCS_STATUS_1 Register 15 14 13 12 11 10 9 8 3 2 PCS_RX_LINK (R) 1 PCS_LP_ABILI TY (R) RO 0 RESERVED RESERVED 7 PCS_FAULT (R) 6 5 4 RESERVED RO RO/LL LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-117. PCS_STATUS_1 Field Descriptions Bit Field TYPE 15:8 RESERVED 7 PCS_FAULT (R) 6:3 RESERVED Reset Description For TI use only. RO 1 = Fault condition detected on either PCS TX or PCS RX 0 = No fault condition detected This bit is cleared after Register 03.0008 is read and no fault condition occurs after 03.0008 is read. For TI use only. 2 PCS_RX_LINK (R) RO/LL 1 = PCS receive link is up 0 = PCS receive link is down 1 PCS_LP_ABILITY (R) RO Always reads 1. 1 = Supports low power mode 0 = Does not support low power mode 0 RESERVED 7.5.4.3 For TI use only. PCS_STATUS_2 (register = 0x0008) (default = 0x8001) (device address: 0x03) Figure 7-136. PCS_STATUS_2 Register 15 14 DEV_PRESENT (R) 13 12 11 10 PCS_TX_FAUL PCS_RX_FAUL T T (R) (R) RO/LH RO/LH RESERVED RO 7 6 5 4 RESERVED 3 2 9 8 RESERVED 1 0 PCS_10GBAS ER_CAPABLE (R) RO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-118. PCS_STATUS_2 Field Descriptions Field Type 15:14 Bit DEV_PRESENT (R) RO 13:12 RESERVED Reset Description Always reads 2’b10. 0x = No device responding at this address 10 = Device responding at this address 11 = No device responding at this address For TI use only. 11 PCS_TX_FAULT (R) RO/LH 1 = Fault condition detected on transmit path 0 = No fault condition detected on transmit path 10 PCS_RX_FAULT (R) RO/LH 1 = Fault condition detected on receive path 0 = No fault condition detected on receive path 9:1 RESERVED 0 PCS_10GBASER_CAPABLE (R) For TI use only. RO Always reads 1. 1 = PCS is able to support 10GBASE-R PCS type 0 = PCS not able to support 10GBASE-R PCS type Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 115 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.4.4 www.ti.com KR_PCS_STATUS_1 (register = 0x0020) (default = 0x0004) (device address: 0x03) Figure 7-137. KR_PCS_STATUS_1 Register 15 14 RESERVED 13 RO 7 6 5 RESERVED 12 PCS_RX_LINK _STATUS (R) RO 11 4 3 10 9 8 1 PCS_HI_BER (R) 0 PCS_BLOCK_L OCK (R) RO RESERVED 2 PCS_PRBS31_ ABILITY (R) RO RO RO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-119. KR_PCS_STATUS_1 Field Descriptions Bit 15:13 12 11:3 Field Type RESERVED RO Reset Description For TI use only. PCS_RX_LINK_STATUS (R) RO 1 = 10GBASE-R PCS receive link up 0 = 10GBASE-R PCS receive link down RESERVED RO For TI use only. 2 PCS_PRBS31_ABILITY (R) RO Always reads 1. 1 = PCS is able to support PRBS31 pattern testing 0 = PCS is not able to support PRBS31 testing 1 PCS_HI_BER (R) RO 1 = High BER condition detected 0 = High BER condition not detected 0 PCS_BLOCK_LOCK (R) RO 1 = PCS locked to receive blocks 0 = PCS not locked to receive blocks 7.5.4.5 KR_PCS_STATUS_2 (register = 0x0021) (default = 0x0000) (device address: 0x03) Figure 7-138. KR_PCS_STATUS_2 Register 15 PCS_BLOCK_ LOCK_LL (R) RO/LL 14 PCS_HI_BER_ LH (R) RO/LH 13 7 6 5 12 11 10 PCS_BER_COUNT[5:0] (R) 9 8 1 0 COR 4 3 PCS_ERR_BLOCK_COUNT[7:0] (R) COR 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-120. KR_PCS_STATUS_2 Field Descriptions Bit Field Type 15 PCS_BLOCK_LOCK_LL (R) RO/LL 1 = PCS locked to receive blocks 0 = PCS not locked to receive blocks 14 PCS_HI_BER_LH (R) RO/LL 1 = High BER condition detected 0 = High BER condition not detected 13:8 PCS_BER_COUNT[5:0] (R) COR Value indicating number of times BER state machine enters BER_BAD_SH state 7:0 PCS_ERR_BLOCK_COUNT[7:0] (R) COR Value indicating number of times RX decode state machine enters RX_E state. Same value is also reflected in 1E.0010 and reading either register clears the counter value. 116 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5.4.6 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 PCS_TP_SEED_A0 (register = 0x0022) (default = 0x0000) (device address: 0x03) Figure 7-139. PCS_TP_SEED_A0 Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_SEED_A[15:0] (R) RW 5 4 3 2 1 0 2 1 0 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-121. PCS_TP_SEED_A0 Field Descriptions Bit 15:0 7.5.4.7 Field Type PCS_TP_SEED_A[15:0] (R) RW Reset Description Test pattern seed A bits 15-0 PCS_TP_SEED_A1 (register = 0x0023) (default = 0x0000) (device address: 0x03) Figure 7-140. PCS_TP_SEED_A1 Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_SEED_A[31:16] (R) RW 5 4 3 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-122. PCS_TP_SEED_A1 Field Descriptions Bit 15:0 7.5.4.8 Field Type PCS_TP_SEED_A[31:16] (R) RW Reset Description Test pattern seed A bits 31-16 PCS_TP_SEED_A2 (register = 0x0024) (default = 0x0000) (device address: 0x03) Figure 7-141. PCS_TP_SEED_A2 Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_SEED_A[47:32] (R) RW 5 4 3 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-123. PCS_TP_SEED_A2 Field Descriptions Bit 15:0 Field Type PCS_TP_SEED_A[47:32] (R) RW Reset Description Test pattern seed A bits 47-32 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 117 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.4.9 www.ti.com PCS_TP_SEED_A3 (register = 0x0025) (default = 0x0000) (device address: 0x03) Figure 7-142. PCS_TP_SEED_A3 Register 15 14 13 12 RESERVED 11 10 9 8 7 RW 6 5 4 3 PCS_TP_SEED_A[57:48] (R) RW 2 1 0 1 0 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-124. PCS_TP_SEED_A3 Field Descriptions Bit 15:10 9:0 Field Type RESERVED RW Reset Description For TI use only. Always reads 0. PCS_TP_SEED_A[57:48] (R) RW Test pattern seed A bits 57-48 7.5.4.10 PCS_TP_SEED_B0 (register = 0x0026) (default = 0x0000) (device address: 0x03) Figure 7-143. PCS_TP_SEED_B0 Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_SEED_B[15:0] (R) RW 5 4 3 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-125. PCS_TP_SEED_B0 Field Descriptions Bit 15:0 Field Type PCS_TP_SEED_B[15:0] (R) RW Reset Description Test pattern seed B bits 15-0 7.5.4.11 PCS_TP_SEED_B1 (register = 0x0027) (default = 0x0000) (device address: 0x03) Figure 7-144. PCS_TP_SEED_B1 Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_SEED_B[31:16] (R) RW 5 4 3 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-126. PCS_TP_SEED_B1 Field Descriptions Bit 15:0 118 Field Type PCS_TP_SEED_B[31:16] (R) RW Reset Description Test pattern seed B bits 31-16 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.4.12 PCS_TP_SEED_B2 (register = 0x0028) (default = 0x0000) (device address: 0x03) Figure 7-145. PCS_TP_SEED_B2 Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_SEED_B[47:32] (R) RW 5 4 3 2 1 0 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-127. PCS_TP_SEED_B2 Field Descriptions Bit 15:0 Field Type PCS_TP_SEED_B[47:32] (R) RW Reset Description Test pattern seed B bits 47-32 7.5.4.13 PCS_TP_SEED_B3 (register = 0x0029) (default = 0x0000) (device address: 0x03) Figure 7-146. PCS_TP_SEED_B3 Register 15 14 13 12 RESERVED 11 10 9 8 7 RW 6 5 4 3 PCS_TP_SEED_B[57:48] (R) RW 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-128. PCS_TP_SEED_B3 Field Descriptions Bit 15:10 9:0 Field Type RESERVED RW Reset Description For TI use only. Always reads 0. PCS_TP_SEED_B[57:48] (R) RW Test pattern seed B bits 57-48 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 119 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.4.14 PCS_TP_CONTROL (register = 0x002A) (default = 0x0000) (device address: 0x03) Figure 7-147. PCS_TP_CONTROL Register 15 14 13 12 11 10 9 8 1 PCS_TP_SEL (R) 0 PCS_DP_SEL (R) RW RW RESERVED RW 7 6 5 4 3 2 PCS_PRBS31_ PCS_PRBS31_ PCS_TX_TP_E PCS_RX_TP_E RX_TP_EN TX_TP_EN N N (R) (R) (R) (R) RW RW RW RW RESERVED RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-129. PCS_TP_CONTROL Field Descriptions Bit Field Type RESERVED RW For TI use only. Always reads 0. 5 PCS_PRBS31_RX_TP_EN (R) RW 1 = Enable PRBS31 test pattern verification on receive path 0 = Normal operation (Default 1’b0) 4 PCS_PRBS31_TX_TP_EN (R) RW 1 = Enable PRBS31 test pattern generation on transmit path 0 = Normal operation (Default 1’b0) 3 PCS_TX_TP_EN (R) RW 1 = Enable transmit test pattern generation 0 = Normal operation (Default 1’b0) 2 PCS_RX_TP_EN (R) RW 1 = Enable receive test pattern verification 0 = Normal operation (Default 1’b0) 1 PCS_TP_SEL (R) RW 1 = Square wave test pattern 0 = Pseudo random test pattern (Default 1’b0) 0 PCS_DP_SEL (R) RW 1 = 0’S data pattern 0 = LF data pattern (Default 1’b0) 15:6 Reset Description 7.5.4.15 PCS_TP_ERR_COUNT (register = 0x002B) (default = 0x0000) (device address: 0x03) Figure 7-148. PCS_TP_ERR_COUNT Register 15 14 13 12 11 10 9 8 7 6 PCS_TP_ERR_COUNT[15:0] (R) COR 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-130. PCS_TP_ERR_COUNT Field Descriptions Bit 15:0 120 Field Type PCS_TP_ERR_COUNT[15:0] (R) COR Reset Description Test pattern error counter. This counter reflects number of errors occurred during the test pattern mode selected through PCS_TP_CONTROL. In PRBS31 test pattern verification mode, counter value indicates the number of received bytes that have 1 or more bit errors. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.4.16 PCS_VS_CONTROL (register = 0x8000) (default = 0x00B0) (device address: 0x03) Figure 7-149. PCS_VS_CONTROL Register 15 14 13 12 11 10 9 8 3 RESERVED 2 PCS_RX_DEC _CTRL_CHAR (R) RW 1 PCS_DESCR_ DISABLE (R) RW 0 PCS_SCR_DIS ABLE (R) RW RESERVED RW 7 6 5 PCS_SQWAVE_N (R) 4 RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-131. PCS_VS_CONTROL Field Descriptions Field Type 15:8 Bit RESERVED RW Reset Description For TI use only. Always reads 0. 7:4 PCS_SQWAVE_N (R) RW Sets number of repeating 0’s followed by repeating 1’s during square wave test pattern generation mode (Default 4’1011) 3 RESERVED RW For TI use only (Default 1’b0) 2 PCS_RX_DEC_CTRL_CHAR (R) RW PCS RX Decode control character selection. Determines what control characters are passed 0 = A/K/R control characters are changed to Idles. Reserved characters passed through (Default 1’b0) 1 = A/K/R control characters are passed through as is RW 1 PCS_DESCR_DISABLE (R) RW De-scrambler control in 10GKR RX PCS 1 = Disable descrambler 0 = Enable descrambler (Default 1’b0) 0 PCS_SCR_DISABLE (R) RW Scrambler control in 10GKR TX PCS 1 = Disable scrambler 0 = Enable scrambler (Default 1’b0) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 121 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.4.17 PCS_VS_STATUS (register = 0x8010) (default = 0x00FD) (device address: 0x03) Figure 7-150. PCS_VS_STATUS Register 15 14 RESERVED RO/LF 7 6 13 12 UNCORR_ERR CORR_ERR_S _STATUS TATUS (R) (R) RO/LF RO/LF 5 11 4 10 RESERVED 9 8 PCS_TP_ERR (R) RO/LF 3 2 1 0 RESERVED COR LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-132. PCS_VS_STATUS Field Descriptions Bit Field Type RESERVED RO/LF For TI use only. 13 UNCORR_ERR_STATUS (R) RO/LF 1 = Uncorrectable block error found 12 CORR_ERR_STATUS (R) RO/LF 1 = Correctable block error found RESERVED COR For TI use only. PCS_TP_ERR (R) RO/LF PCS test pattern verification status PCS_SCR_DISABLE 1 = Error occurred during pseudo random test pattern verification Number of errors can be checked by reading PCS_TP_ERR_COUNT (03.002B) register RESERVED COR For TI use only. 15:14 11:9 8 7:0 122 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5.5 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Auto-Negotiation Registers The registers below can be accessed only in Clause 45 mode and with device address field set to 0x07 (DA[4:0] = 5’b00111) 7.5.5.1 AN_CONTROL (register = 0x0000) (default = 0x3000) (device address: 0x07) Figure 7-151. AN_CONTROL Register 15 AN_RESET (RX) RW/SC 14 7 6 13 RESERVED RW 12 AN_ENABLE (RX) RW 11 4 3 5 10 RESERVED RW 2 9 AN_RESTART (RX) RW/SC (1) 8 RESERVED 1 0 RW RESERVED RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset (1) If set, a read of register 07.0000 is required to clear AN_RESTART bit. Table 7-133. AN_CONTROL Field Descriptions Bit Field Type 15 AN_RESET (RX) RW/SC 1 = Resets Auto Negotiation 0 = Normal operation (Default 1’b0) 14 RESERVED RW For TI use only. Always reads 0. 13 RESERVED RW For TI use only (Default 1’b1) 12 AN_ENABLE (RX) RW 1 = Enable Auto Negotiation (Default 1’b1) 0 = Disable Auto Negotiation 11:10 RESERVED RW For TI use only. Always reads 0. AN_RESTART (RX) RW/SC 1 = Restart Auto Negotiation 0 = Normal operation (Default 1’b0) If set, a read of this register is required to clear AN_RESTART bit. RESERVED RW For TI use only. Always reads 0. 9 8:0 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 123 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.5.2 www.ti.com AN_STATUS (register = 0x0001) (default = 0x0088) (device address: 0x07) Figure 7-152. AN_STATUS Register 15 14 13 12 11 10 9 AN_PAR_DET_FAULT (RX) RO/LH 8 RESERVED 4 REMOTE_FA ULT (RX) RO/LH 3 AN_ABILITY (RX) 2 LINK_STATU S (RX) RO/LL 1 RESERVED 0 AN_LP_ABILI TY (RX) RO RESERVED 7 AN_EXP_NP_ STATUS (RX) RO 6 AN_PAGE_R CVD (RX) RO/LH 5 AN_COMPLE TE (RX) RO RO RO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-134. AN_STATUS Field Descriptions Bit Field Type RESERVED RO For TI use only. 9 AN_PAR_DET_FAULT (RX) RO/LH 1 = Fault has been detected via parallel detection function 0 = Fault has not been detected via parallel detection function 8 RESERVED RO For TI use only. 7 AN_EXP_NP_STATUS (RX) RO/LH 1 = Extended next page is used 0 = Extended next page is not allowed 6 AN_PAGE_RCVD (RX) RO 1 = A page has been received 0 = A page has not been received 5 AN_COMPLETE (RX) RO/LH 1 = Auto Negotiation process is completed 0 = Auto Negotiation process not completed 4 REMOTE_FAULT (RX) RO/LH 1 = Remote fault detected by AN 0 = Remote fault not detected by AN 3 AN_ABILITY (RX) RO Always reads 1. 1 = Device is able to perform Auto Negotiation 0 = Device not able to perform Auto Negotiation 2 LINK_STATUS (RX) RO/LH 1 = Link is up 0 = Link is down 1 RESERVED RO For TI use only. 0 AN_LP_ABILITY (RX) RO 1 = LP is able to perform Auto Negotiation 0 = LP not able to perform Auto Negotiation 15:10 124 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 7.5.5.3 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 AN_DEV_PACKAGE (register = 0x0005) (default = 0x0080) (device address: 0x07) Figure 7-153. AN_DEV_PACKAGE Register XXX 15 14 13 12 11 10 9 8 3 RESERVED 2 1 0 RESERVED RO 7 AN_ PRESENT (RX) RO 6 5 4 RO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-135. AN_DEV_PACKAGE Field Descriptions Bit 15:8 7 6:0 Field Type RESERVED RO For TI use only. AN_PRESENT (RX) RO Always reads 1 1 = Auto Negotiation present in the package 0 = Auto Negotiation not present in the package RESERVED RO For TI use only. 7.5.5.4 Reset Description AN_ADVERTISEMENT_1 (register = 0x0010) (default = 0x1001) (device address: 0x07) Figure 7-154. AN_ADVERTISEMENT_1 Register 15 AN_NEXT_PA GE (RX) RW 7 14 13 AN_ACKNOWL AN_REMOTE_ EDGE FAULT (RX) (RX) RO RW 6 AN_ECHO_NONCE[4:0] (RX) RW 12 11 AN_CAPABILITY[2:0] (RX) 10 9 8 AN_ECHO_NONCE[4:0] (RX) RW 5 4 3 RW 2 AN_SELECTOR[4:0] (RX) RW 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-136. AN_ADVERTISEMENT_1 Field Descriptions Bit Field Type 15 AN_NEXT_PAGE (RX) RW Reset Description NP bit (D15) in base link codeword 1 = Next page available 0 = Next page not available (Default 1’b0) 14 AN_ACKNOWLEDGE (RX) RO Acknowledge bit (D14) in base link codeword. Always reads 0. 13 AN_REMOTE_FAULT (RX) RW RF bit (D13) in base link codeword 1 = Sets RF bit to 1 0 = Normal operation (Default 1’b0) 12:10 AN_CAPABILITY[2:0] (RX) RW Value to be set in D12:D10 bits of the base link codeword. Consists of abilities like PAUSE, ASM_DIR (Default 3’b100) 9:5 AN_ECHO_NONCE[4:0] (RX) RW Value to be set in D9:D5 bits of the base link codeword. Consists of Echo nonce value. Transmitted in base page only until local device and link Partner have exchanged unique Nonce values, at which time transmitted Echoed Nonce will change to Link Partner's Nonce value. Read value always reflects the value written, not the actual Echoed Nonce. (Default 5’b00000) 4:0 AN_SELECTOR[4:0] (RX) RW Value to be set in D4:D0 bits of the base link codeword. Consists of selector field value (Default 5’b00001) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 125 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.5.5 AN_ADVERTISEMENT_2 (register = 0x0011) (default = 0x0080) (device address: 0x07) Figure 7-155. AN_ADVERTISEMENT_2 Register 15 14 13 7 AN_ABILITY[2] (RX) RW 6 AN_ABILITY[1] (RX) RW 5 AN_ABILITY[0] (RX) RW 12 11 AN_ABILITY[10:3] (RX) RW 4 3 10 9 8 2 1 AN_TRANS_NONCE_ FIELD[4:0] (RX) RW 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-137. AN_ADVERTISEMENT_2 Field Descriptions Bit Field Value AN_ABILITY[10:3] (RX) RW Value to be set in D31:D24 bits of the base link codeword. Consists of technology ability field bits [10:3] (Default 9’b000000000) 7 AN_ABILITY[2] (RX) RW Value to be set in D23 bits of the base link codeword. Consists of technology ability field bits [2]. When set, indicates device supports 10GBASE-KR (Default 1’b1) 6 AN_ABILITY[1] (RX) RW Value to be set in D22 bits of the base link codeword. Consists of technology ability field bits [1]. Always set to 0 (Default 1’b0) 5 AN_ABILITY[0] (RX) RW Value to be set in D21 bits of the base link codeword. Consists of technology ability field bit [0]. When set, indicates device supports 1000BASE-KX (Default 1’b0) AN_TRANS_NONCE_ FIELD[4:0] (RX) RW Not used. Transmitted Nonce field is generated by hardware random number generator. Read value always reflects value written, not the actual Transmitted Nonce (Default 5’b00000) 15:8 4:0 Reset Description 7.5.5.6 AN_ADVERTISEMENT_3 (register = 0x0012) (default = 0x4000) (device address: 0x07) Figure 7-156. AN_ADVERTISEMENT_3 Register 15 AN_FEC_REQ UESTED (RX) RW 14 AN_FEC_ABILI TY (RX) RW 13 7 6 5 12 11 10 AN_ABILITY[24:11] (RX) 9 8 1 0 RW 4 3 AN_ABILITY[24:11] (RX) RW 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-138. AN_ADVERTISEMENT_3 Field Descriptions Bit Field Type 15 AN_FEC_REQUESTED (RX) RW Value to be set in D47 bits of the base link codeword. When set, indicates a request to enable FEC on the link (Default 1’b0) 14 AN_FEC_ABILITY (RX) RW Value to be set in D46 bits of the base link codeword. When set, indicates 10GBASE-KR has FEC ability (Default 1’b1) 13:0 AN_ABILITY[24:11] (RX) RW Value to be set in D45:D32 bits of the base link codeword. Consists of technology ability field bits [24:11] (Default 14’b00000000000000) 126 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.5.7 AN_LP_ADVERTISEMENT_1 (register = 0x0013) (default = 0x0001) (device address: 0x07) Figure 7-157. AN_LP_ADVERTISEMENT_1 Register 15 AN_LP_NEXT_ PAGE (RX) RO 7 14 AN_LP_ACKN OWLEDGE (RX) RO 13 AN_LP_REMO TE_FAULT (RX) RO 6 AN_ LP_ECHO_NONCE (RX) RO 12 11 AN_ LP_CAPABILITY (RX) 10 9 8 AN_ LP_ECHO_NONCE (RX) RO 5 4 3 RO 2 AN_LP_SELECTOR[4:0] (RX) RO 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-139. AN_LP_ADVERTISEMENT_1 (1) Field Descriptions Bit Field Type 15 AN_LP_NEXT_PAGE (RX) RO NP bit (D15) in link partner base page 1 = Next page available in link partner 0 = Next page not available in link partner 14 AN_LP_ACKNOWLEDGE (RX) RO Acknowledge bit (D14) in link partner base page. 13 AN_LP_REMOTE_FAULT (RX) RO RF bit (D13) in link partner base page 1 = Remote fault detected in link partner 0 = Remote fault not detected in link partner AN_ LP_CAPABILITY (RX) RO D12:D10 bits of the link partner base page. Consists of abilities like PAUSE, ASM_DIR 9:5 AN_ LP_ECHO_NONCE (RX) RO D9:D5 bits of the link partner base page. Consists of Echo nonce value 4:0 AN_LP_SELECTOR[4:0] (RX) RO D4:D0 bits of the link partner base page. Consists of selector field value Always reads 5’b00001 12:10 (1) Reset Description To get accurate AN_LP_ADVERTISEMENT read value, Register 07.0013 should be read first before reading 07.0014 and 07.0015 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 127 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.5.8 AN_LP_ADVERTISEMENT_2 (register = 0x0014) (default = 0x0000) (device address: 0x07) Figure 7-158. AN_LP_ADVERTISEMENT_2 Register 15 14 13 7 AN_LP_ABILIT Y[2] (RX) RO 6 AN_LP_ABILIT Y[1] (RX) RO 5 AN_LP_ABILIT Y[0] (RX) RO 12 11 AN_ LP_ABILITY[10:3] (RX) RO 4 3 10 9 8 2 1 AN_LP_TRANS_NONCE_FIELD (RX) 0 RO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-140. AN_LP_ADVERTISEMENT_2 Field Descriptions Bit Field Type AN_ LP_ABILITY[10:3] (RX) RO D31:D24 bits of the link partner base page. Consists of technology ability field bits [10:3] 7 AN_LP_ABILITY[2] (RX) RO D23 bits of the link partner base page. Consists of technology ability field bits [2]. When high, indicates link partner supports 10GBASE-KR 6 AN_LP_ABILITY[1] (RX) RO D22 bits of the link partner base page. Consists of technology ability field bits [1]. 5 AN_LP_ABILITY[0] (RX) RO D21 bits of the link partner base page. Consists of technology ability field bit [0]. When high, indicates link partner supports 1000BASE-KX AN_LP_TRANS_NONCE_FIELD (RX) RO D20:D16 bits of the link partner base page. Consists of transmitted nonce value 15:8 4:0 128 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.5.9 AN_LP_ADVERTISEMENT_3 (register = 0x0015) (default = 0x0000) (device address: 0x07) Figure 7-159. AN_LP_ADVERTISEMENT_3 Register 15 14 AN_LP_FEC_R AN_LP_FEC_A EQUESTED BILITY (RX) (RX) RO RO 7 6 13 12 11 10 AN_LP_ABILITY[24:11] (RX) 9 8 1 0 RO 5 4 3 AN_LP_ABILITY[24:11] (RX) RO 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-141. AN_LP_ADVERTISEMENT_3 Field Descriptions Bit Field Type 15 AN_LP_FEC_REQUESTED (RX) RO Reset Description D47 bits of the link partner base page. When high, indicates link partner request to enable FEC on the link 14 AN_LP_FEC_ABILITY (RX) RO D46 bits of the link partner base page. When high, indicates link partner has FEC ability 13:0 AN_LP_ABILITY[24:11] (RX) RO D45:D32 bits of the link partner base page. Consists of link partner technology ability field bits [24:11] 7.5.5.10 AN_XNP_TRANSMIT_1 (register = 0x0016) (default = 0x2000) (device address: 0x07) Figure 7-160. AN_XNP_TRANSMIT_1 Register 15 AN_XNP_NEX T_PAGE (RX) RW 14 RESERVED 13 AN_MP (RX) RO RW 7 6 5 12 AN_ACKNOWL EDGE_2 (RX) RW 11 AN_TOGGLE (RX) 10 9 AN_CODE_FIELD (RX) RW 4 3 AN_CODE_FIELD (RX) RW 8 RW 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-142. AN_XNP_TRANSMIT_1 Field Descriptions Bit Field Type 15 AN_XNP_NEXT_PAGE (RX) RW NP bit (D15) in next page code word 1 = Next page available 0 = Next page not available (Default 1’b0) 14 RESERVED RO Always reads 0. 13 AN_MP (RX) RW Message page bit (D13) in next page code word 1 = Sets MP bit to 1 indicating next page is a message page (Default 1’b1) 0 = Sets MP bit to 0 indicating next page is unformatted next page 12 AN_ACKNOWLEDGE_2 (RX) RW Value to be set in D12 bit of the next page code word. When set, indicates device is able to act on the information defined in the message (Default 1’b0) 11 AN_TOGGLE (RX) RW Not used. Toggle value is generated by hardware. Read value always reflects value written, not the actual Toggle field (Default 1’b0) AN_CODE_FIELD (RX) RW Value to be set in D10:D0 bits of the next page code word. Consists of Message/Unformatted code field value (Default 11’b00000000000) 10:0 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 129 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.5.11 AN_XNP_TRANSMIT_2 (register = 0x0017) (default = 0x0000) (device address: 0x07) Figure 7-161. AN_XNP_TRANSMIT_2 Register 15 14 13 12 11 10 9 8 7 AN_MSG_CODE_1 (RX) RW 6 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-143. AN_XNP_TRANSMIT_2 Field Descriptions Bit 15:0 Field Value AN_MSG_CODE_1 (RX) RW Reset Description Value to be set in D31:D16 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) 7.5.5.12 AN_XNP_TRANSMIT_3 (register = 0x0018) (default = 0x0000) (device address: 0x07) Figure 7-162. AN_XNP_TRANSMIT_3 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN_MSG_CODE_2 (RX) RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-144. AN_XNP_TRANSMIT_3 Field Descriptions Bit 15:0 130 Field Type AN_MSG_CODE_2 (RX) RW Reset Description Value to be set in D47:D32 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 7.5.5.13 AN_LP_XNP_ABILITY_1 (register = 0x0019) (default = 0x0000) (device address: 0x07) Figure 7-163. AN_LP_XNP_ABILITY_1 Register 15 14 AN_LP_XNP_N AN_LP_XNP_A EXT_PAGE CKNOWLEDG (RX) E (RX) RO RO 7 6 13 AN_LP_MP (RX) 12 AN_LP_ACKN OWLEDGE_2 (RX) 11 AN_LP_TOGG LE (RX) RO RO RO 5 4 3 AN_ LP_CODE_FIELD (RX) RO 10 9 AN_ LP_CODE_FIELD (RX) 8 RO 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-145. AN_LP_XNP_ABILITY_1 (1) Field Descriptions Bit Field Type 15 AN_LP_XNP_NEXT_PAGE (RX) RO NP bit (D15) in next page code word 1 = Next page available 0 = Next page not available (Default 1’b0) 14 AN_LP_XNP_ACKNOWLEDGE (RX) RO Value in D14 bit of the next page code word. When set, indicates device is able to act on the information defined in the message (Default 1’b0) 13 AN_LP_MP (RX) RO Message page bit (D13) in next page code word 1 = Sets MP bit to 1 indicating next page is a message page 0 = Sets MP bit to 0 indicating next page is unformatted next page (Default 1’b0) 12 AN_LP_ACKNOWLEDGE_2 (RX) RO Value in D12 bit of the next page code word. When set, indicates device is able to act on the information defined in the message (Default 1’b0) 11 AN_LP_TOGGLE (RX) RO Value of D11 bit of the next page code word. Consists of Toggle field value(Default 1’b0) AN_ LP_CODE_FIELD (RX) RO Value in D10:D0 bits of the next page code word. Consists of Message/Unformatted code field value (Default 11’b00000000000) 10:0 (1) Reset Description To get accurate AN_LP_XNP_ABILITYT read value, Register 07.0019 should be read first before reading 07.001A and 07.001B Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 131 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 7.5.5.14 AN_LP_XNP_ABILITY_2 (register = 0x001A) (default = 0x0000) (device address: 0x07) Figure 7-164. AN_LP_XNP_ABILITY_2 Register 15 14 13 12 11 10 9 8 7 6 AN_LP_MSG_CODE_2 (RX) RO 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-146. AN_LP_XNP_ABILITY_2 Field Descriptions Bit 15:0 Field Type AN_LP_MSG_CODE_1 (RX) RO Reset Description Value to be set in D31:D16 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) 7.5.5.15 AN_LP_XNP_ABILITY_3 (register = 0x001B) (default = 0x0000) (device address: 0x07) Figure 7-165. AN_LP_XNP_ABILITY_3 Register 15 14 13 12 11 10 9 8 7 6 AN_LP_MSG_CODE_2 (RX) RO 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-147. AN_LP_XNP_ABILITY_3 Field Descriptions Bit 15:0 Field Type AN_LP_MSG_CODE_2 (RX) RO Reset Description Value to be set in D47:D32 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) 7.5.5.16 AN_BP_STATUS (register = 0x0030) (default = 0x0001) (device address: 0x07) Figure 7-166. AN_BP_STATUS Register 15 14 13 12 11 10 9 8 3 AN_10G_KR (RX) 2 RESERVED 1 AN_1G_KX (RX) RO RO RO 0 AN_BP_AN_AB ILITY (RX) RO RESERVED RO 7 6 RESERVED 5 4 AN_10G_KR_F EC (RX) RO RO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-148. AN_BP_STATUS Field Descriptions Bit Field Type RESERVED RO For TI use only. 4 AN_10G_KR_FEC (RX) RO 1 = PMA/PMD is negotiated to perform 10GBASE-KR FEC 3 AN_10G_KR (RX) RO 1 = PMA/PMD is negotiated to perform 10GBASE-KR 2 RESERVED RO For TI use only. 1 AN_1G_KX (RX) RO 1 = PMA/PMD is negotiated to perform 1000BASE-KX 0 AN_BP_AN_ABILITY (RX) RO Always reads 1. 1 = Indicates 1000BASE-KX, 10GBASE-KR is implemented 15:5 132 Reset Description Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Table 7-149. TI_Reserved Control and Status Registers Register Name Register Address Default Value Access Register Name Register Address Default Value Access TI_RESERVED_CONTROL 1E.8000 0x04C0 RW TI_RESERVED_STATUS 1E.A014 0x0000 RO TI_RESERVED_CONTROL 1E.8001 0x0207 RW TI_RESERVED_STATUS 1E.A015 0x0000 RO TI_RESERVED_CONTROL 1E.8002 0x02FE RW TI_RESERVED_STATUS 1E.A016 0x0000 RO TI_RESERVED_CONTROL 1E.8005 0x0000 RW TI_RESERVED_STATUS 1E.A017 0x0000 RO TI_RESERVED_CONTROL 1E.8006 0x0000 RW TI_RESERVED_STATUS 1E.A018 0x0000 RO TI_RESERVED_CONTROL 1E.8007 0x8000 RW TI_RESERVED_CONTROL 1E.A116 0x0000 RW TI_RESERVED_CONTROL 1E.8008 0x0000 RW TI_RESERVED_CONTROL 1E.A117 0x0000 RW TI_RESERVED_CONTROL 1E.8009 0xFC00 RW TI_RESERVED_STATUS 1E.A118 0x0000 RO TI_RESERVED_CONTROL 1E.800A 0xBC3C RW TI_RESERVED_STATUS 1E.A119 0x0000 RO TI_RESERVED_CONTROL 1E.800B 0x0000 RW TI_RESERVED_CONTROL 01.8000 0x4800 RW TI_RESERVED_CONTROL 1E.800C 0x0000 RW TI_RESERVED_STATUS 01.801F 0xFFFD COR TI_RESERVED_CONTROL 1E.800D 0x01FC RW TI_RESERVED_STATUS 01.8020 0xFFFD COR TI_RESERVED_CONTROL 1E.800E 0x0000 RW TI_RESERVED_STATUS 01.8021 0xFFFD COR TI_RESERVED_CONTROL 1E.800F 0x00C0 RW TI_RESERVED_STATUS 01.8022 0xFFFD COR TI_RESERVED_CONTROL 1E.8011 0x7F00 RW TI_RESERVED_STATUS 01.8023 0xFFFF COR TI_RESERVED_STATUS 1E.8012 0xFFFD COR TI_RESERVED_STATUS 01.8024 0xFFFD COR TI_RESERVED_STATUS 1E.8013 0xFFFD COR TI_RESERVED_CONTROL 01.9000 0x0249 RW TI_RESERVED_STATUS 1E.8014 0x0000 RO/LH TI_RESERVED_CONTROL 01.9002 0x1335 RW TI_RESERVED_STATUS 1E.8015 0x0000 RO TI_RESERVED_CONTROL 01.9003 0x5E29 RW TI_RESERVED_CONTROL 1E.8019 0xFC00 RW TI_RESERVED_CONTROL 01.9004 0x007F RW TI_RESERVED_CONTROL 1E.801A 0xBC3C RW TI_RESERVED_CONTROL 01.9005 0x1C00 RW TI_RESERVED_CONTROL 1E.801C 0x0000 RW TI_RESERVED_CONTROL 01.9006 0x0000 RW TI_RESERVED_CONTROL 1E.801D 0x01FC RW TI_RESERVED_CONTROL 01.9007 0x5120 RW TI_RESERVED_CONTROL 1E.801E 0x0000 RW TI_RESERVED_CONTROL 01.9008 0xC018 RW TI_RESERVED_CONTROL 1E.801F 0x00C0 RW TI_RESERVED_CONTROL 01.9009 0xE667 RW TI_RESERVED_CONTROL 1E.8020 0x0200 RW TI_RESERVED_CONTROL 01.900A 0x5E8F RW TI_RESERVED_CONTROL 1E.8022 0x0000 RW TI_RESERVED_CONTROL 01.900B 0xAFAF RW TI_RESERVED_CONTROL 1E.8023 0x0000 RW TI_RESERVED_CONTROL 01.900C 0x0800 RW TI_RESERVED_CONTROL 1E.8024 0x0000 RW TI_RESERVED_CONTROL 01.900D 0x461A RW TI_RESERVED_CONTROL 1E.8025 0xF000 RW TI_RESERVED_CONTROL 01.900E 0x1723 RW TI_RESERVED_STATUS 1E.8030 0x0000 RO TI_RESERVED_CONTROL 01.900F 0x7003 RW TI_RESERVED_STATUS 1E.8031 0x0000 RO TI_RESERVED_CONTROL 01.9010 0x0851 RW TI_RESERVED_STATUS 1E.8032 0x0000 RO TI_RESERVED_CONTROL 01.9011 0x1EFF RW TI_RESERVED_STATUS 1E.8033 0x0000 RO TI_RESERVED_STATUS 01.9020 0x0000 RO TI_RESERVED_STATUS 1E.8034 0x0000 RO TI_RESERVED_STATUS 01.9021 0xFFFD COR TI_RESERVED_STATUS 1E.8035 0x0000 RO TI_RESERVED_STATUS 01.9022 0x0000 RO TI_RESERVED_CONTROL 1E.8050 0x0000 RW TI_RESERVED_STATUS 01.9023 0x0000 RO TI_RESERVED_CONTROL 1E.8102 0xF280 RW TI_RESERVED_STATUS 01.9024 0x0000 RO TI_RESERVED_CONTROL 1E.A000 0x0000 RW TI_RESERVED_STATUS 01.9025 0x0000 RO TI_RESERVED_STATUS 1E.A010 0x0000 RO TI_RESERVED_STATUS 01.9026 0x0000 RO TI_RESERVED_STATUS 1E.A011 0x0000 RO TI_RESERVED_STATUS 01.9027 0x0000 RO TI_RESERVED_STATUS 1E.A012 0x0000 RO TI_RESERVED_STATUS 01.9028 0x0000 RO TI_RESERVED_STATUS 1E.A013 0x0000 RO TI_RESERVED_STATUS 01.9029 0x0000 RO Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 133 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TLK10031 device can be used to convert between XAUI (on the low speed port) and 10GBASE-R signaling (on the high speed port). The high speed side of the device meets the requirements of the 10GBASE-KR physical layer standard for 10 Gbps data transmission over a PCB backplane. The device can also be used for optical physical layers (like 10GBASE-SR or 10GBASE-LR) by interfacing to optical modules requiring SFI or XFI electrical signaling. For optical use cases, KR-specific features like Clause 73 auto-negotiation and link training should be disabled. 8.2 Typical Application A typical application for TLK10031 is to support 10 Gbps Ethernet data transmission over a backplane, e.g., between a network processor or MAC and switch ASIC located on separate cards within a router chassis. A block diagram of this application is shown in Figure 8-1. Line Card NPU Backplane Switch 10-KR TLK10031 10 GbE MAC 10 GbE PHY XAUI Interfaces Figure 8-1. Typical Application Circuit 134 Applications and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com 8.2.1 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Design Requirements For this design example, use the parameters shown in Table 8-1. Table 8-1. Design Parameters PARAMETER VALUE 10GBASE-KR Interface Requirements Signaling rate 10.3125 Gbps ±100 ppm Differential peak-to-peak output voltage (maximum) 1200 mV Total jitter (maximum) 0.28 UI Encoding 64b/66b Scrambling? Yes Auto-negotation? Yes Link training Yes XAUI Interface Requirements 8.2.2 Signaling rate per lane 3.125 Gbps ±100 ppm Differential peak-to-peak output voltage (maximum) 1600 mV Total jitter (maximum) 0.35 UI Detailed Design Procedure The TLK10031 should be powered via a 1-V (nominal) supply on the VDDD, VDDA, DVDD, VDDT, and VPP rails and by a 1.5-V or 1.8-V (nominal) supply on the VDDR and VDDO rails. The power supply accuracy should be 5% or better, and the user should be careful that resistive losses across the application PCB’s power distribution network do not cause the voltage present at the TLK10031 BGA balls to be below specification. If a switched-mode power supply is used, care should be taken to ensure low supply ripple A differential reference clock must be provided to either the REFCLK0P/N or REFCLK1P/N input port. The clock signal should be AC-coupled and have a differential amplitude between 250 mV and 2000 mV peakto-peak. For 10GBASE-R applications, the clock frequency should be either 156.25 MHz or 312.5 MHz and have an accuracy of 100 ppm. Because jitter on the reference clock can transfer through the TLK10031 PLLs and onto the serial outputs, it is best to keep the reference clock’s jitter as low as possible (that is, under 1 ps from 10 kHz to 20 MHz) in order to meet the requirements of IEEE 802.3. All serial inputs and outputs should be laid out on the PCB following best practices for high speed signal integrity. Detailed layout recommendations are given in the Section 10 section. Applications and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 135 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 8.2.3 www.ti.com Application Curves The output eye diagram of the TLK10031 (operated at 10.3125 Gbps under nominal conditions) is shown Figure 8-2. Time 20 ps/div Figure 8-2. Eye Diagram of the TLK10031 9 Power Supply Recommendations The TLK10031 allows either the core or I/O power supply to be powered up for an indefinite period of time while the other supply is not powered up, if all of the following conditions are met: 1. All maximum ratings and recommending operating conditions are followed 2. Bus contention while 1.5/1.8V power is applied (>0V) must be limited to 100 hours over the projected lifetime of the device. 3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the absolute maximum voltage values for up to 100 hours of lifetime operation at a TJ of 105°C or lower will minimally impact reliability. The TLK10031 LVCMOS I/O are not failsafe (i.e. cannot be driven with the I/O power disabled). TLK10031 inputs should not be driven high until their associated power supply is active. 136 Power Supply Recommendations Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 10 Layout 10.1 Layout Guidelines 10.1.1 TLK10031 High-Speed Data Path 10.1.1.1 Layout Recommendations for High-Speed Signals Both “low-speed” side and “high-speed” side serial signals are referred to as “high-speed” signals for the purpose of this document as they support high data rates. For that reason, care must be taken to realize them on a printed circuit board with signal integrity. The high-speed data path CML input pins INA[3:0]P/INA[3:0]N and HSRXAP/HSRXAN, and the CML output pins OUTA[3:0]P/OUTA[3:0]N and HSTXAP/HSTXAN, have to be connected with loosely-coupled 100-Ω differential transmission lines. Differential intra-pair skew needs to be minimized to within ±1 mil. Inter-pair (lane-to-lane) skew for the low-speed signals can be as high as 30 UI. An example of FR-4 printed circuit board (PCB) realization of such differential transmission lines in microstrip format is shown in Figure 10-1. Figure 10-1. Differential Microstrip PCB Trace Geometry Example To avoid impedance discontinuities the high-speed serial signals should be routed on a PCB on either the top or bottom PCB layers in microstrip format with no vias. If vias are unavoidable, an absolute minimum number of vias need to be used. The vias should be made to stretch through the entire PCB thickness (as shown in Figure 10-2) to connect microstrip traces on the top and bottom layers of the PCB so as to leave no via stubs that can severely impact the performance. If stripline traces are absolutely necessary, and if via back-drilling is not possible, then the routing layers should be chosen so as to have via stubs that are shorter than 10 mils. All unused internal layer via pads on high-speed signal vias should be removed to further improve impedance matching. On the high-speed side, the HSRXAP/HSRXAN signals are more sensitive to impedance discontinuities introduced by vias than HSTXAP/HSTXAN signals. For that reason, if only some of those signals need to be routed with vias, then the latter should be routed with vias and the former with no vias. Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 137 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Figure 10-2. Examples of High-speed PCB Traces With Vias That Have no Via Stubs and no Via Pads on Internal Layers To further improve on impedance matching, differential vias with neighboring ground vias can be used as shown in Figure 10-3. The optimum dimensions of such a differential via structure depend on various parameters such as the trace geometry, dielectric material, as well as the PCB layer stack-up. A 3D electromagnetic field solver can be used to find the optimum via dimensions. Figure 10-3. A Differential PCB Via Structure (Top View) PCB traces connected to the HSRXAP/HSRXAN pins should have differential insertion loss of less than 25 dB at 5 GHz. 138 Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 Surface-mount connector pads such as those used with the SFP/SFP+ module connectors are wider and hence have characteristic impedance that is lower than the regular high-speed PCB traces. If the pads are more than 2 times wider than the PCB traces, the pads’ impedance needs to be increased to minimize impedance discontinuities. The easy way of increasing the pads’ impedance is to cut out the reference plane immediately under those pads as shown in Figure 10-4 so as to have the pads refer to a reference plane on lower layers while maintaining 100 Ω differential characteristic impedance. Figure 10-4. Surface-mount Connector Pads 10.1.1.2 AC-coupling A 0.1-uF series AC-coupling capacitor should be connected to each of the high-speed data path pins INA[3:0]P/INA[3:0]N, HSRXAP/HSRXAN, OUTA[3:0]P/OUTA[3:0]N, and HSTXAP/HSTXAN. If the TLK10031 high-speed side data path pins are connected to SFP/SFP+ optical modules with internal ACcoupling capacitors, then no external capacitors should be used. Adding additional series capacitors may severely impact the performance. To avoid impedance discontinuities, it is strongly recommended where possible to make the transmission line trace width closely match the AC-coupling capacitor pad size. Smaller capacitor packages such as 0201 make it easy to meet that condition. 10.1.2 TLK10031 Clocks: REFCLK, CLKOUT 10.1.2.1 General Information The TLK10031 device requires a low-jitter reference clock to work. The reference clock can be provided on the REFCLK0P/N or REFCLK1P/N pins. Both reference clock input pins have internal 100-Ω differential terminations, so they do not need any external terminations. Both reference clock inputs must be AC-coupled with preferably 0.1-µF capacitors. The two channels (A and B) can have same or different reference clocks. The TLK10031 serial receiver recovers clock and data from the incoming serial data. The recovered byte clock is made available on the CLKOUTAP/N pins. The CLKOUTAP/N CML output pins must be ACcoupled with 0.1-µF AC-coupling capacitors. Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 139 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 10.1.2.2 External Clock Connections An external clock jitter cleaner, such as Texas Instruments CDCE72010 or CDCM7005, may be used when needed to provide a low jitter reference clock. An example external clock jitter cleaner connection for channel A is shown in Figure 10-5. HSRXAP/N OUTA[3:0] CLKOUTAP/N REFCLK0P/N External Clock Jitter Cleaner TLK10031 FPGA VCXO HSTXAP/N INA[3:0] Figure 10-5. An External Clock Jitter Cleaner Connection Example for Channel A 10.1.2.3 TLK10031 Control Pins and Interfaces The TLK10031 device features a number of control pins and interfaces, some of which are described as follows. 10.1.2.3.1 MDIO Interface The TLK10031 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links. The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference (MDC). The port address is determined by the PRTAD[4:0] control pins. The MDIO pin requires a pullup to VDDO[1:0]. No pullup is needed on the MDC pin if driven with a pushpull MDIO master, but a pullup to VDDO[1:0] is needed if driven with an open-drain MDIO master. 10.1.2.3.2 JTAG Interface The JTAG interface is mostly used for device test. The JTAG interface operates through the TDI, TDO, TMS, TCK, and TRST_N pins. If not used, all the pins can be left unconnected except TDI and TCK which must be grounded. 10.1.2.3.3 Unused Pins As a general guideline, any unused LVCMOS input pin needs to be grounded and any unused LVCMOS output pin can be left unconnected. Unused CML differential output pins can be left unconnected. Unused CML differential input pins should be tied to ground through a shared 100-Ω resistor. 140 Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 TLK10031 www.ti.com SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 10.2 Layout Example Figure 10-6. Pinout and Routing Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10031 141 TLK10031 SLLSEL3C – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical Packaging and Orderable Information 12.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 142 Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Links: TLK10031 Copyright © 2015–2017, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLK10031CTR ACTIVE FCBGA CTR 144 119 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 85 TLK10031 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of